Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206134
G. Lojewski, N. Militaru, M. Banciu
In this paper a bandpass planar filter, with cross-couplings and with a pair of attenuation poles, is investigated. The equi-ripple in-band response and the location of the poles on the frequency axis can be precisely controlled by using a new technique which combines accurate electromagnetic field simulations and fast linear circuit optimization, allowing the design of bandpass filters with improved performances. To illustrate the procedure, a microstrip bandpass filter was designed, verified by em-field simulation, fabricated and tested. The response of the designed filter is in good agreement with the specification, confirming the possibilities of realizing microwave bandpass filters with rigorously controlled characteristics, with reduced design time and non-prohibitive computational effort.
{"title":"Microwave bandpass filters with multiple couplings, designed using electromagnetic simulations and linear circuit optimization","authors":"G. Lojewski, N. Militaru, M. Banciu","doi":"10.1109/ISSCS.2009.5206134","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206134","url":null,"abstract":"In this paper a bandpass planar filter, with cross-couplings and with a pair of attenuation poles, is investigated. The equi-ripple in-band response and the location of the poles on the frequency axis can be precisely controlled by using a new technique which combines accurate electromagnetic field simulations and fast linear circuit optimization, allowing the design of bandpass filters with improved performances. To illustrate the procedure, a microstrip bandpass filter was designed, verified by em-field simulation, fabricated and tested. The response of the designed filter is in good agreement with the specification, confirming the possibilities of realizing microwave bandpass filters with rigorously controlled characteristics, with reduced design time and non-prohibitive computational effort.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132299164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206137
Mohammad Hekmat Kashtiban, S. J. Azhari
In this work a novel CMOS Current Output Stage (COS) is presented whose Common-Mode Rejection Ratio is remarkably increased exploiting a novel Common Mode Feed Forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13µm technology and simulated with ADS and Hspice. The proposed COS achieved 105dB CMRR and 85dB PSRR while can work under ±1V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50dB and 30dB respectively.
{"title":"A novel high CMRR low voltage current output stage","authors":"Mohammad Hekmat Kashtiban, S. J. Azhari","doi":"10.1109/ISSCS.2009.5206137","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206137","url":null,"abstract":"In this work a novel CMOS Current Output Stage (COS) is presented whose Common-Mode Rejection Ratio is remarkably increased exploiting a novel Common Mode Feed Forward (CMFF) technique to compensate the output common mode signal. The complete stage is designed in 0.13µm technology and simulated with ADS and Hspice. The proposed COS achieved 105dB CMRR and 85dB PSRR while can work under ±1V power supply. Compared to the traditional COS the CMRR and PSRR improvement are higher than 50dB and 30dB respectively.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130741076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206226
R. Bozomitu, V. Cehan
In this paper, a new linearization technique using a second generation of current conveyor doublet (CCIID) in CMOS technology is presented. The proposed CCIID is made up a mixed parallel and cross connection of two CCII stages. The output current is given by the difference between the two output currents provided by the two CCII stages. Due to the cross-connection of the two CCII stages, the nonlinearities of these currents are canceled, which determines a linear output current in a large dynamic range.
{"title":"A new linearization technique using a CCII doublet transconductor in CMOS technology","authors":"R. Bozomitu, V. Cehan","doi":"10.1109/ISSCS.2009.5206226","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206226","url":null,"abstract":"In this paper, a new linearization technique using a second generation of current conveyor doublet (CCIID) in CMOS technology is presented. The proposed CCIID is made up a mixed parallel and cross connection of two CCII stages. The output current is given by the difference between the two output currents provided by the two CCII stages. Due to the cross-connection of the two CCII stages, the nonlinearities of these currents are canceled, which determines a linear output current in a large dynamic range.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127449262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206179
A. A. Kamal, A. Youssef
Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various applications. On the other hand, a straightforward implementation of the AES is vulnerable to different forms of side channel attacks. In this paper, we explore several countermeasure techniques against power analysis attacks. In particular, we present an area optimized design that combines shuffling, as a hiding countermeasure, with some recently proposed masking techniques. The developed power analysis resistant AES-128 ECB encryption/decryption engine requires 3090 slices of a Xilinx Virtex-II xc2v1000-6-bg575 FPGA, runs at a maximum clock speed of 51.75 MHz and produces a throughput of up to 15.33 Mbps.
{"title":"An area-optimized implementation for AES with hybrid countermeasures against power analysis","authors":"A. A. Kamal, A. Youssef","doi":"10.1109/ISSCS.2009.5206179","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206179","url":null,"abstract":"Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various applications. On the other hand, a straightforward implementation of the AES is vulnerable to different forms of side channel attacks. In this paper, we explore several countermeasure techniques against power analysis attacks. In particular, we present an area optimized design that combines shuffling, as a hiding countermeasure, with some recently proposed masking techniques. The developed power analysis resistant AES-128 ECB encryption/decryption engine requires 3090 slices of a Xilinx Virtex-II xc2v1000-6-bg575 FPGA, runs at a maximum clock speed of 51.75 MHz and produces a throughput of up to 15.33 Mbps.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129016416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206165
D. Tarniceriu, V. Munteanu, G. Zaharia
In this paper an information analysis for lossless compression of a large class of discrete sources is performed. The lossless compression is performed by means of a Huffman code with an alphabet A of size M. Matrix characterization of the encoding as a source with memory is realized. The information quantities H(S,A), H(S), H(A), H(A|S), H(S|A), I(S,A) as well as the minimum average code word length are derived. Three extreme cases, p=M-1, p=0 and M=2, p=1 have been analyzed.
{"title":"Information analysis for a large class of discrete sources","authors":"D. Tarniceriu, V. Munteanu, G. Zaharia","doi":"10.1109/ISSCS.2009.5206165","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206165","url":null,"abstract":"In this paper an information analysis for lossless compression of a large class of discrete sources is performed. The lossless compression is performed by means of a Huffman code with an alphabet A of size M. Matrix characterization of the encoding as a source with memory is realized. The information quantities H(S,A), H(S), H(A), H(A|S), H(S|A), I(S,A) as well as the minimum average code word length are derived. Three extreme cases, p=M-1, p=0 and M=2, p=1 have been analyzed.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129070798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206089
Iulian Nita, V. Lazarescu, R. Constantinescu
Our goal in this paper is to simulate the behavior of multiprocessor system on chip. We used an open virtual platform - OVPSim made by Imperas Company, which offers the possibility of programming and running application on the platforms architectures. With this platform we simulated both hardware architectures and running software applications. We used two types of processors - ARM7 IP core and MIPS32 IP core, shared memory, local memory and BUS for interconnections and simulated three systems on chip models and for each architecture we simulated the running of the same applications.
{"title":"A new Hw/Sw co-design method for multiprocessor system on chip applications","authors":"Iulian Nita, V. Lazarescu, R. Constantinescu","doi":"10.1109/ISSCS.2009.5206089","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206089","url":null,"abstract":"Our goal in this paper is to simulate the behavior of multiprocessor system on chip. We used an open virtual platform - OVPSim made by Imperas Company, which offers the possibility of programming and running application on the platforms architectures. With this platform we simulated both hardware architectures and running software applications. We used two types of processors - ARM7 IP core and MIPS32 IP core, shared memory, local memory and BUS for interconnections and simulated three systems on chip models and for each architecture we simulated the running of the same applications.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127131959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206150
D. Alexa, T. Goras, I. Pletea, R. Buzatu, M. Moisa, R. Chiper
A new topology for a two-quadrant converter is presented. In the AC/DC transfer mode, the converter works as a rectifier with near sinusoidal input currents and capacitors connected on the AC side (RNSIC-2), whereas in the DC/AC transfer mode, it works as a square-wave pulse switching inverter. The converter is characterized by smaller power losses and reduced electromagnetic interference problems. Possible applications in adjustable speed drive with regenerative braking, wind energy conversion systems and small hydro interconnections with induction generators.
{"title":"Analysis of the two-quadrant converter having rectifier with near sinusoidal input currents and capacitors connected on the AC side","authors":"D. Alexa, T. Goras, I. Pletea, R. Buzatu, M. Moisa, R. Chiper","doi":"10.1109/ISSCS.2009.5206150","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206150","url":null,"abstract":"A new topology for a two-quadrant converter is presented. In the AC/DC transfer mode, the converter works as a rectifier with near sinusoidal input currents and capacitors connected on the AC side (RNSIC-2), whereas in the DC/AC transfer mode, it works as a square-wave pulse switching inverter. The converter is characterized by smaller power losses and reduced electromagnetic interference problems. Possible applications in adjustable speed drive with regenerative braking, wind energy conversion systems and small hydro interconnections with induction generators.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129034807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206186
I. Buciu, I. Nafornita
Face recognition task is of primary interest in many computer vision applications, including access control for security systems, forensic or surveillance. Most commercial biometric systems based on face recognition are claimed to perform satisfactory when the enrollment and testing process takes place under controlled environmental conditions such as constant illumination, constant pose scale, non-occluded faces or frontal view. More or less deviation from those conditions might lead to poor recognition performances or even recognition system's failure when a test identity has to be recognized under new modified testing conditions. Three non-negative matrix factorization (NMF) methods, namely, the standard one, the local NMF (LNMF) and the discriminant NMF (DNMF) are employed in this paper where their robustness against extreme lighting variations are tested for the face recognition task. Principal Component Analysis (PCA) method was also chosen as baseline. Experiments revealed that the best recognition performance is obtained with NMF, followed by DNMF and LNMF.
{"title":"Non-negative matrix factorization methods for face recognition under extreme lighting variations","authors":"I. Buciu, I. Nafornita","doi":"10.1109/ISSCS.2009.5206186","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206186","url":null,"abstract":"Face recognition task is of primary interest in many computer vision applications, including access control for security systems, forensic or surveillance. Most commercial biometric systems based on face recognition are claimed to perform satisfactory when the enrollment and testing process takes place under controlled environmental conditions such as constant illumination, constant pose scale, non-occluded faces or frontal view. More or less deviation from those conditions might lead to poor recognition performances or even recognition system's failure when a test identity has to be recognized under new modified testing conditions. Three non-negative matrix factorization (NMF) methods, namely, the standard one, the local NMF (LNMF) and the discriminant NMF (DNMF) are employed in this paper where their robustness against extreme lighting variations are tested for the face recognition task. Principal Component Analysis (PCA) method was also chosen as baseline. Experiments revealed that the best recognition performance is obtained with NMF, followed by DNMF and LNMF.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123273810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206201
S. Rodriguez, A. Rusu, M. Ismail
This paper presents the design challenges and solutions for 4G nanometer radio receivers for mobile devices. The specifications for the ZERO-IF/LOW-IF 4G receiver architecture are derived. Limitations due to the use of low-voltage nanometer technologies are described and novel circuit techniques, such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are proposed. Finally, a 1.2-V 90nm CMOS receiver front-end for the proposed WiMAX/LTE receiver is designed employing novel circuit techniques. The front-end covers 700 MHz – 6 GHz, providing a total gain of 34 dB, noise figure of 4 dB, flicker noise corner of 10 kHz, and a third order intercept point of −10dBm/0dBm, while consuming a total power of 10.2 mW.
{"title":"4G CMOS nanometer receivers for mobile systems: Challenges and solutions","authors":"S. Rodriguez, A. Rusu, M. Ismail","doi":"10.1109/ISSCS.2009.5206201","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206201","url":null,"abstract":"This paper presents the design challenges and solutions for 4G nanometer radio receivers for mobile devices. The specifications for the ZERO-IF/LOW-IF 4G receiver architecture are derived. Limitations due to the use of low-voltage nanometer technologies are described and novel circuit techniques, such as wideband noise reduction, inductoreless peaking, passive mixing, and low flicker noise amplification are proposed. Finally, a 1.2-V 90nm CMOS receiver front-end for the proposed WiMAX/LTE receiver is designed employing novel circuit techniques. The front-end covers 700 MHz – 6 GHz, providing a total gain of 34 dB, noise figure of 4 dB, flicker noise corner of 10 kHz, and a third order intercept point of −10dBm/0dBm, while consuming a total power of 10.2 mW.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114605851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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