Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206086
M. Petouris, A. Kalantzopoulos, E. Zigouris
Field Programmable Gate Arrays (FPGAs) are in use to build high performance image processing systems. This paper presents the design and implementation of such an open FPGA-based Digital Camera System for image capturing and real-time image processing. Images captured with a CMOS sensor are initially stored in the system's memory and then they are displayed on an LCD Touch Panel. The main goal of this proposed architecture is to be used as a platform to implement and test advance image processing algorithms. Apart of this, the system supports the control of the image sensor, through the LCD Touch Panel. In addition, has the ability to communicate with a PC through a JTAG interface for storing the images on it. The structural element for this proposed architecture was chosen to be the low cost and widely used at universities, Altera's DE2 development board.
{"title":"An FPGA-based Digital Camera System controlled from an LCD Touch Panel","authors":"M. Petouris, A. Kalantzopoulos, E. Zigouris","doi":"10.1109/ISSCS.2009.5206086","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206086","url":null,"abstract":"Field Programmable Gate Arrays (FPGAs) are in use to build high performance image processing systems. This paper presents the design and implementation of such an open FPGA-based Digital Camera System for image capturing and real-time image processing. Images captured with a CMOS sensor are initially stored in the system's memory and then they are displayed on an LCD Touch Panel. The main goal of this proposed architecture is to be used as a platform to implement and test advance image processing algorithms. Apart of this, the system supports the control of the image sensor, through the LCD Touch Panel. In addition, has the ability to communicate with a PC through a JTAG interface for storing the images on it. The structural element for this proposed architecture was chosen to be the low cost and widely used at universities, Altera's DE2 development board.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125653925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206156
X. Xu
A jitter auto-attenuating phase locked loop (PLL) is proposed to reduce the jitter and achieve fast settling. The proposed PLL starts with a fast acquisition loop dynamics, then slips into a low jitter loop dynamics when the loop gains lock. The transition is seamlessly triggered by lock detection circuitry. This jitter auto attenuating technique can achieve both fast frequency acquisition and low jitter performance in PLL design.
{"title":"A phase locked loop with jitter auto-attenuating loop dynamics","authors":"X. Xu","doi":"10.1109/ISSCS.2009.5206156","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206156","url":null,"abstract":"A jitter auto-attenuating phase locked loop (PLL) is proposed to reduce the jitter and achieve fast settling. The proposed PLL starts with a fast acquisition loop dynamics, then slips into a low jitter loop dynamics when the loop gains lock. The transition is seamlessly triggered by lock detection circuitry. This jitter auto attenuating technique can achieve both fast frequency acquisition and low jitter performance in PLL design.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124667299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206200
M. Xiao, S. W. Cheung, T. Yuk
This paper proposes to use nonlinear mixer circuits to generate the intermodulation (IM) products for high-power amplifier (HPA) predistortion using the difference-frequency technique. The design of a 3rd-order nonlinear circuit is used for illustration purpose. The circuit employs two mixers using Schottky diodes as non-linear devices to generate the difference-frequency signals. The circuit has a simple structure, requires no DC bias or additional filters, and is easy to fabricate and low cost. Simulation and measurement results show that the design has a low conversion loss and a low-frequency spurious.
{"title":"A simple mixer for generating the 3rd-order intermodulation products used for HPA predistortion","authors":"M. Xiao, S. W. Cheung, T. Yuk","doi":"10.1109/ISSCS.2009.5206200","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206200","url":null,"abstract":"This paper proposes to use nonlinear mixer circuits to generate the intermodulation (IM) products for high-power amplifier (HPA) predistortion using the difference-frequency technique. The design of a 3rd-order nonlinear circuit is used for illustration purpose. The circuit employs two mixers using Schottky diodes as non-linear devices to generate the difference-frequency signals. The circuit has a simple structure, requires no DC bias or additional filters, and is easy to fabricate and low cost. Simulation and measurement results show that the design has a low conversion loss and a low-frequency spurious.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123140300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206157
Chun-Chieh Chen, Yu-Lun Chung, C. Chiu
This work presents a novel flash analog-to-digital converter (ADC) with distributed track-and-hold pre-comparators (THPCs). Utilizing the proposed architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 300mW from a 1.8-V supply at full operating speed.
{"title":"6-b 1.6-GS/s flash ADC with distributed track-and-hold pre-comparators in a 0.18µm CMOS","authors":"Chun-Chieh Chen, Yu-Lun Chung, C. Chiu","doi":"10.1109/ISSCS.2009.5206157","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206157","url":null,"abstract":"This work presents a novel flash analog-to-digital converter (ADC) with distributed track-and-hold pre-comparators (THPCs). Utilizing the proposed architecture, the loading capacitances of the ADC front-end sampling sub-circuits can be markedly reduced, thereby improving operation speed. In a standard 0.18µm CMOS process, a 1.6GS/s 6-bit flash ADC is implemented to demonstrate the feasibility of the proposed distributed THPC architecture. The equivalent input capacitance of each input port of the proposed flash ADC is only 400fF, which is an easily driven interface. Furthermore, clocked timing buffers are inserted in the encoder to accelerate the operational speed of the proposed flash ADC. Post-layout simulation results demonstrate that the proposed ADC achieves an SNDR of 35.81dB, which is 5.66 ENOB at 1.6GS/s with a 793.8MHz input signal frequency. The proposed ADC consumes 300mW from a 1.8-V supply at full operating speed.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129595789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206213
M. Fira, L. Goras
This paper presents a discussion concerning ECG signals compression using the basis pursuit (BP) approach applied for several overcomplete wavelet dictionaries. The compression is based on an “optimal” superposition of dictionary elements, by minimizing the l1 norm of the error. The best results have been obtained with the Coiflet 4 dictionary.
{"title":"Basis pursuit for ECG compression","authors":"M. Fira, L. Goras","doi":"10.1109/ISSCS.2009.5206213","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206213","url":null,"abstract":"This paper presents a discussion concerning ECG signals compression using the basis pursuit (BP) approach applied for several overcomplete wavelet dictionaries. The compression is based on an “optimal” superposition of dictionary elements, by minimizing the l1 norm of the error. The best results have been obtained with the Coiflet 4 dictionary.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"176 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133290334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206118
H. Teodorescu
We present an adaptive filtering and echolocator system that is able to adapt to the change in air temperature, pressure and humidity, preserving its capabilities of correctly detecting the echo position. The adaptive system is intended to work in conjunction with an air ultrasonic visualization system working at low frequencies, in the band 50–500 kHz. Topics addressed include: computation of the changes in received spectra due to changes in humidity of the air; determining the required adaptive filters responding to the air humidity changes, compensating for the distance-dependent attenuation, and preserving spectra of the reflected impulse; characterization of the reflecting surface; algorithms for the above. This paper proposes a preliminary algorithm, not yet tested.
{"title":"Algorithm for adaptive distance estimators for echolocation in air","authors":"H. Teodorescu","doi":"10.1109/ISSCS.2009.5206118","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206118","url":null,"abstract":"We present an adaptive filtering and echolocator system that is able to adapt to the change in air temperature, pressure and humidity, preserving its capabilities of correctly detecting the echo position. The adaptive system is intended to work in conjunction with an air ultrasonic visualization system working at low frequencies, in the band 50–500 kHz. Topics addressed include: computation of the changes in received spectra due to changes in humidity of the air; determining the required adaptive filters responding to the air humidity changes, compensating for the distance-dependent attenuation, and preserving spectra of the reflected impulse; characterization of the reflecting surface; algorithms for the above. This paper proposes a preliminary algorithm, not yet tested.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115138686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206129
S. Oniga, A. Tisan, D. Mic, C. Lung, I. Orha, A. Buchman, A. Vida-Ratiu
This paper presents the results obtained in the implementation of Feed-Forward Artificial Neural Networks (FF-ANN) with one or several layers, used in the development of smart devices that needs learning capability and adaptive behavior. The networks were implemented using ANN specific blocks created by the authors using the System Generator software. The training and the testing of the networks was conducted using sets of 150 training and test vectors with 7 elements.
{"title":"FPGA implementation of Feed-Forward Neural Networks for smart devices development","authors":"S. Oniga, A. Tisan, D. Mic, C. Lung, I. Orha, A. Buchman, A. Vida-Ratiu","doi":"10.1109/ISSCS.2009.5206129","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206129","url":null,"abstract":"This paper presents the results obtained in the implementation of Feed-Forward Artificial Neural Networks (FF-ANN) with one or several layers, used in the development of smart devices that needs learning capability and adaptive behavior. The networks were implemented using ANN specific blocks created by the authors using the System Generator software. The training and the testing of the networks was conducted using sets of 150 training and test vectors with 7 elements.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":" 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206092
C. Vladeanu, S. El Assad, J. Carlach, R. Quéré, I. Marghescu
In this paper, optimum recursive systematic convolutional (RSC) encoders over Galois field GF(2N) are designed using a nonlinear function, i.e., left-circulate function (LCIRC). The LCIRC function performs a bit left circulation over the representation word; it is used in microprocessors as an accumulator operation, and in chaotic sequence generators working in finite precision. Different encoding rates are obtained for these encoders when using different representation wordlengths at the input and the output, denoted as Nin and N, respectively. A generalized 1-delay GF(2N) RSC encoder scheme using LCIRC is proposed for performance analysis and optimization, for any possible encoding rate, Nin/N. The minimum Euclidian distance is estimated for these optimum encoders and a general expression is found as a function of the wordlengths Nin and N. The symbol error rate (SER) is estimated by simulation for a quaternary pulse amplitude modulation - trellis-coded modulation (PAM-TCM) transmission over an additive white Gaussian noise (AWGN) channel. The simulation results confirm the expected coding gains determined theoretically.
{"title":"Optimum PAM-TCM schemes using left-circulate function over GF(2N)","authors":"C. Vladeanu, S. El Assad, J. Carlach, R. Quéré, I. Marghescu","doi":"10.1109/ISSCS.2009.5206092","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206092","url":null,"abstract":"In this paper, optimum recursive systematic convolutional (RSC) encoders over Galois field GF(2N) are designed using a nonlinear function, i.e., left-circulate function (LCIRC). The LCIRC function performs a bit left circulation over the representation word; it is used in microprocessors as an accumulator operation, and in chaotic sequence generators working in finite precision. Different encoding rates are obtained for these encoders when using different representation wordlengths at the input and the output, denoted as Nin and N, respectively. A generalized 1-delay GF(2N) RSC encoder scheme using LCIRC is proposed for performance analysis and optimization, for any possible encoding rate, Nin/N. The minimum Euclidian distance is estimated for these optimum encoders and a general expression is found as a function of the wordlengths Nin and N. The symbol error rate (SER) is estimated by simulation for a quaternary pulse amplitude modulation - trellis-coded modulation (PAM-TCM) transmission over an additive white Gaussian noise (AWGN) channel. The simulation results confirm the expected coding gains determined theoretically.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116165514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206203
O. Pastravanu, M. Matcovschi
The class of instruments available for set invariance analysis with respect to linear system dynamics is significantly wider for sets that are symmetrical (relative to the state-space origin), compared with the non-symmetrical case. Our work provides a new result for testing the invariance of non-symmetrical sets, described by general forms. For any considered set, the instantaneous shape is defined by the help of a Hőlder p-norm, 1 ≤ p ≤ ∞, applied to a smooth vector function, whose components are time-and region-dependent. We also show that our invariance testing procedure incorporates, as particular cases, some results already known, separately proved by different authors.
{"title":"The non-symmetrical case of invariant-set analysis with respect to linear dynamics","authors":"O. Pastravanu, M. Matcovschi","doi":"10.1109/ISSCS.2009.5206203","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206203","url":null,"abstract":"The class of instruments available for set invariance analysis with respect to linear system dynamics is significantly wider for sets that are symmetrical (relative to the state-space origin), compared with the non-symmetrical case. Our work provides a new result for testing the invariance of non-symmetrical sets, described by general forms. For any considered set, the instantaneous shape is defined by the help of a Hőlder p-norm, 1 ≤ p ≤ ∞, applied to a smooth vector function, whose components are time-and region-dependent. We also show that our invariance testing procedure incorporates, as particular cases, some results already known, separately proved by different authors.","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117200427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-07-09DOI: 10.1109/ISSCS.2009.5206211
M. Bohme, M. Haker, T. Martinetz, E. Barth
We present a facial feature detector for time-of-flight (TOF) cameras that extends previous work by combining a nose detector based on geometric features with a face detector. The goal is to prevent false detections outside the area of the face. To detect the nose in the image, we first compute the geometric features per pixel. We then augment these geometric features with two additional features: The horizontal and vertical distance to the most likely face detected by a cascade-of-boosted-ensembles face detector. We use a very simple classifier based on an axis-aligned bounding box in feature space; pixels whose feature values fall within the box are classified as nose pixels, and all other pixels are classified as “non-nose”. The extent of the bounding box is learned on a labeled training set. Despite its simiplicity, this detector already delivers satisfactory results on the geometric features alone; adding the face detector improves the equal error rate (EER) from 22.2% (without face detector) to 10.4% (with face detector). (Note when comparing with our previous results from [1] and [2] that, in contrast to this paper, the test data used there did not contain scale variations.)
{"title":"Head tracking with combined face and nose detection","authors":"M. Bohme, M. Haker, T. Martinetz, E. Barth","doi":"10.1109/ISSCS.2009.5206211","DOIUrl":"https://doi.org/10.1109/ISSCS.2009.5206211","url":null,"abstract":"We present a facial feature detector for time-of-flight (TOF) cameras that extends previous work by combining a nose detector based on geometric features with a face detector. The goal is to prevent false detections outside the area of the face. To detect the nose in the image, we first compute the geometric features per pixel. We then augment these geometric features with two additional features: The horizontal and vertical distance to the most likely face detected by a cascade-of-boosted-ensembles face detector. We use a very simple classifier based on an axis-aligned bounding box in feature space; pixels whose feature values fall within the box are classified as nose pixels, and all other pixels are classified as “non-nose”. The extent of the bounding box is learned on a labeled training set. Despite its simiplicity, this detector already delivers satisfactory results on the geometric features alone; adding the face detector improves the equal error rate (EER) from 22.2% (without face detector) to 10.4% (with face detector). (Note when comparing with our previous results from [1] and [2] that, in contrast to this paper, the test data used there did not contain scale variations.)","PeriodicalId":277587,"journal":{"name":"2009 International Symposium on Signals, Circuits and Systems","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124531003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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