Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844198
T. Iizuka, Takehisa Koga, T. Nakura, K. Asada
This paper proposes a fine-time-resolution pulse-shrinking (PS) time-to-digital converter (TDC) based on an offset pulse width detection scheme. The proposed PS TDC detects the end of the conversion utilizing a built-in offset pulse unlike the conventional PS TDCs. Thus it prevents an undesirable non-uniform shrinking rate issue in the conventional ones and contributes to fine-resolution, small-area, power-efficient and low-jitter implementation. The prototype TDC fabricated in a 0.18μm standard CMOS technology realizes 9 bit, 1.8 ps sub-gate-delay resolution with 0.07 mm2 area, and achieves 2.16 ps single-shot precision. Its power dissipation is 3.4 mW at 4.4 MS/s.
{"title":"A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse","authors":"T. Iizuka, Takehisa Koga, T. Nakura, K. Asada","doi":"10.1109/ASSCC.2016.7844198","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844198","url":null,"abstract":"This paper proposes a fine-time-resolution pulse-shrinking (PS) time-to-digital converter (TDC) based on an offset pulse width detection scheme. The proposed PS TDC detects the end of the conversion utilizing a built-in offset pulse unlike the conventional PS TDCs. Thus it prevents an undesirable non-uniform shrinking rate issue in the conventional ones and contributes to fine-resolution, small-area, power-efficient and low-jitter implementation. The prototype TDC fabricated in a 0.18μm standard CMOS technology realizes 9 bit, 1.8 ps sub-gate-delay resolution with 0.07 mm2 area, and achieves 2.16 ps single-shot precision. Its power dissipation is 3.4 mW at 4.4 MS/s.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125317830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844143
Chun-Yu Lin, Tsung-Hsien Lin
This paper proposes a fractional-N PLL with 2-dimensional quantization noise pushing technique to suppress the quantization noise and a fractional spur elimination technique to mitigate fractional spurs. With these techniques, the experimental results show that the quantization noise is reduced by around 30 dB, and the fractional spurs are considerably suppressed. This PLL was fabricated in a TSMC 90-nm CMOS process. The core area is 0.4 mm2. The chip dissipates 13.5 mW from a 1-V supply voltage.
{"title":"A 4-GHz ΔΣ fractional-N frequency synthesizer with 2-dimensional quantization noise pushing and fractional spur elimination techniques","authors":"Chun-Yu Lin, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2016.7844143","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844143","url":null,"abstract":"This paper proposes a fractional-N PLL with 2-dimensional quantization noise pushing technique to suppress the quantization noise and a fractional spur elimination technique to mitigate fractional spurs. With these techniques, the experimental results show that the quantization noise is reduced by around 30 dB, and the fractional spurs are considerably suppressed. This PLL was fabricated in a TSMC 90-nm CMOS process. The core area is 0.4 mm2. The chip dissipates 13.5 mW from a 1-V supply voltage.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125550360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844180
W. Bae, Haram Ju, Kwanseo Park, D. Jeong
A voltage-mode (VM) transmitter which offers a wide operation range of 6-to-32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the various operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48×0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s.
{"title":"A 6-to-32 Gb/s voltage-mode transmitter with scalable supply, voltage swing, and pre-emphasis in 65-nm CMOS","authors":"W. Bae, Haram Ju, Kwanseo Park, D. Jeong","doi":"10.1109/ASSCC.2016.7844180","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844180","url":null,"abstract":"A voltage-mode (VM) transmitter which offers a wide operation range of 6-to-32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the various operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48×0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121370391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844202
Chao Wang, Jianmin Zhang, Jun Zhou, Xin Liu, R. Tan, Liang Zhong, K. Chai
In this paper, an energy-efficient phonocardiogram (PCG) signal processor is proposed for wearable long-term cardiac monitoring. To achieve high energy efficiency, the proposed PCG processor employs pipelined and memory-less adaptive architecture to implement wavelet-domain statistic based real-time de-noising, heart sound peak detection, false peak filtering, S1/S2 peak identification and cardiac feature extraction. The statistic threshold based memory-less adaptive processing scheme is developed to reduce computation and storage requirement, and therefore energy consumption significantly. At circuit level, sub/near-threshold minimum-energy design technique is adopted to enable processor to operate at the minimum energy point to maximize the energy efficiency. At the optimum operating point of 0.35 V and 2.1 MHz, the fabricated 65-nm PCG processor consumes 7.1 μW and 272 nJ when performing real-time S1/S2 detection of a 20-s heart sound signals with 99.2%/89.9% accuracy.
{"title":"A 65-nm 0.35-V 7.1-μW memory-less adaptive PCG processor for wearable long-term cardiac monitoring","authors":"Chao Wang, Jianmin Zhang, Jun Zhou, Xin Liu, R. Tan, Liang Zhong, K. Chai","doi":"10.1109/ASSCC.2016.7844202","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844202","url":null,"abstract":"In this paper, an energy-efficient phonocardiogram (PCG) signal processor is proposed for wearable long-term cardiac monitoring. To achieve high energy efficiency, the proposed PCG processor employs pipelined and memory-less adaptive architecture to implement wavelet-domain statistic based real-time de-noising, heart sound peak detection, false peak filtering, S1/S2 peak identification and cardiac feature extraction. The statistic threshold based memory-less adaptive processing scheme is developed to reduce computation and storage requirement, and therefore energy consumption significantly. At circuit level, sub/near-threshold minimum-energy design technique is adopted to enable processor to operate at the minimum energy point to maximize the energy efficiency. At the optimum operating point of 0.35 V and 2.1 MHz, the fabricated 65-nm PCG processor consumes 7.1 μW and 272 nJ when performing real-time S1/S2 detection of a 20-s heart sound signals with 99.2%/89.9% accuracy.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132570254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844124
Y. Ishii, M. Yabuuchi, Yohei Sawada, M. Morimoto, Y. Tsukamoto, Y. Yoshida, Ken Shibata, T. Sano, S. Tanaka, K. Nii
We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which enables 2-read/write (2RW) operation within a clock cycle. The data sequencer for address/data latch and double output sense amplifier realize the simulations read-read or write-write operation. We designed and implemented a 512-kb pseudo DP SRAM macro based on 28-nm low-power bulk CMOS technology. Our design achieved the bit density of 5.92 Mb/mm2, which is the highest ever reported. Measured data at 1.0 V supply voltage shows 1.05 ns read-access-time for one port and 2.37 ns for another port, respectively. Area overhead of the proposed circuitry is only 3.2% compared to the original SP SRAM macro.
{"title":"A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry","authors":"Y. Ishii, M. Yabuuchi, Yohei Sawada, M. Morimoto, Y. Tsukamoto, Y. Yoshida, Ken Shibata, T. Sano, S. Tanaka, K. Nii","doi":"10.1109/ASSCC.2016.7844124","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844124","url":null,"abstract":"We propose pseudo dual-port (DP) SRAM by using 6T single-port (SP) SRAM bitcell with double pumping circuitry, which enables 2-read/write (2RW) operation within a clock cycle. The data sequencer for address/data latch and double output sense amplifier realize the simulations read-read or write-write operation. We designed and implemented a 512-kb pseudo DP SRAM macro based on 28-nm low-power bulk CMOS technology. Our design achieved the bit density of 5.92 Mb/mm2, which is the highest ever reported. Measured data at 1.0 V supply voltage shows 1.05 ns read-access-time for one port and 2.37 ns for another port, respectively. Area overhead of the proposed circuitry is only 3.2% compared to the original SP SRAM macro.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131243574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR sub-ADC low-power, but also accelerates its conversion rate. A self-trigger latch (STL) technique is also used to reduce digital power consumption. The prototype ADC in 40nm CMOS consumes 3.1mW at 1.5GS/s with a 0.9V supply. It achieves a Nyquist SNDR of 44.5dB and results in an FoM of 15fJ/c.-s.
{"title":"A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s two-step SAR ADC","authors":"Yao-Sheng Hu, Po-Chao Huang, Mi-Ti Yang, Shih-Wei Wu, Hsin-Shu Chen","doi":"10.1109/ASSCC.2016.7844140","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844140","url":null,"abstract":"An 8-bit 1.5GS/s 2-way two-step SAR ADC operating at 0.9V is presented in this paper. A low-skew demultiplexer circuit is proposed to synchronize the sampled signals of the two sub-ADCs with the edge of global clock. The sharing of the quarter clock phase generator leads to lower power consumption. A charge-sharing technique without any interstage residue amplifier not only makes the two-step SAR sub-ADC low-power, but also accelerates its conversion rate. A self-trigger latch (STL) technique is also used to reduce digital power consumption. The prototype ADC in 40nm CMOS consumes 3.1mW at 1.5GS/s with a 0.9V supply. It achieves a Nyquist SNDR of 44.5dB and results in an FoM of 15fJ/c.-s.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116677155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844150
B. Zimmer, P. Chiu, B. Nikolić, K. Asanović
The presented processor lowers SRAM-based cache Vmin by using three architectural techniques-bit bypass (BB), dynamic column redundancy (DCR), and line disable (LD)-that use low-overhead reprogrammable redundancy (RR) to avoid failing bitcells and therefore increase the maximum bitcell failure rate in processor caches. In the 28nm chip, the Vmin of the 1MB L2 cache is reduced by 25%, resulting in a 49% power reduction with a 2% area overhead and minimal timing overhead.
{"title":"Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor","authors":"B. Zimmer, P. Chiu, B. Nikolić, K. Asanović","doi":"10.1109/ASSCC.2016.7844150","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844150","url":null,"abstract":"The presented processor lowers SRAM-based cache Vmin by using three architectural techniques-bit bypass (BB), dynamic column redundancy (DCR), and line disable (LD)-that use low-overhead reprogrammable redundancy (RR) to avoid failing bitcells and therefore increase the maximum bitcell failure rate in processor caches. In the 28nm chip, the Vmin of the 1MB L2 cache is reduced by 25%, resulting in a 49% power reduction with a 2% area overhead and minimal timing overhead.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115224625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844121
Takuji Miki, T. Ozeki, Junpei Naka
This paper presents a 2 GS/s 8-bit 16× time-interleaved (TI) ADC for millimeter-wave pulsed radar baseband SoC in 40nm CMOS. An extremely-compact foreground timing calibration suppresses sampling clock skews among sub-ADCs within 400fs. Measured SFDR and SNDR at 1GHz full-Nyquist is therefore enhanced by 16dB and 11dB, respectively. Unlike conventional calibration based on redundant ADCs or DSP-assisted calculations, just a few small resistors and a capacitor are needed, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar SoC with beamforming where 8-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed-loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. Thanks to the foreground scheme, the TI-ADC including the input buffer consumes only 54.2mW and 355fJ/step.
{"title":"A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC","authors":"Takuji Miki, T. Ozeki, Junpei Naka","doi":"10.1109/ASSCC.2016.7844121","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844121","url":null,"abstract":"This paper presents a 2 GS/s 8-bit 16× time-interleaved (TI) ADC for millimeter-wave pulsed radar baseband SoC in 40nm CMOS. An extremely-compact foreground timing calibration suppresses sampling clock skews among sub-ADCs within 400fs. Measured SFDR and SNDR at 1GHz full-Nyquist is therefore enhanced by 16dB and 11dB, respectively. Unlike conventional calibration based on redundant ADCs or DSP-assisted calculations, just a few small resistors and a capacitor are needed, resulting in only 0.4% area penalty. This area saving enables the compact integration of the radar SoC with beamforming where 8-channel TI-ADCs occupy the dominant chip area otherwise. Even though this is foreground, no system performance is sacrificed because the calibration sequence is closed-loop and fast enough to be executed during an existing calibration interval in a periodic beam transmission sequence. Thanks to the foreground scheme, the TI-ADC including the input buffer consumes only 54.2mW and 355fJ/step.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128386228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844179
Taehwan Kim, Pavan Bhargava, V. Stojanović
An all-digital nonlinear transmit-side equalization technique based on Model Predictive Control (MPC) is presented. The MPC equalizer performs an online optimization subject to eye height constraints at the RX using transmit waveform as a variable. Compared to existing TX equalization schemes such as IIR or Tomlinson-Harashima Precoding, MPC has been shown to achieve the best eye performance for any type of channel, especially when the control signal resolution is low, with minimal overhead at the RX. A simplified Direct Search algorithm and architecture optimization techniques are proposed to realize the MPC equalizer for high-speed links. A 20-tap MPC transmitter has been implemented in 28nm FDSOI technology. For a multidrop channel, the equalizer achieves opening of a closed eye at 4.5Gb/s for PAM2 and 6Gb/s for PAM4 mode.
{"title":"A model predictive control equalization transmitter for asymmetric interfaces in 28nm FDSOI","authors":"Taehwan Kim, Pavan Bhargava, V. Stojanović","doi":"10.1109/ASSCC.2016.7844179","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844179","url":null,"abstract":"An all-digital nonlinear transmit-side equalization technique based on Model Predictive Control (MPC) is presented. The MPC equalizer performs an online optimization subject to eye height constraints at the RX using transmit waveform as a variable. Compared to existing TX equalization schemes such as IIR or Tomlinson-Harashima Precoding, MPC has been shown to achieve the best eye performance for any type of channel, especially when the control signal resolution is low, with minimal overhead at the RX. A simplified Direct Search algorithm and architecture optimization techniques are proposed to realize the MPC equalizer for high-speed links. A 20-tap MPC transmitter has been implemented in 28nm FDSOI technology. For a multidrop channel, the equalizer achieves opening of a closed eye at 4.5Gb/s for PAM2 and 6Gb/s for PAM4 mode.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121018821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844135
Daniel DeDorigo, Y. Manoli
This paper presents a field-programmable analog array (FPAA) with on-chip automatic filter tuning in a 130nm CMOS technology. Parasitic capacitances in the signal nodes are compensated to eliminate the constraints on the regularity of the array and to enable the implementation of 12 capacitance arrays, 2 mixers and 62 OTAs on a die area of 0.8 mm2. The tuning technique is independent on the frequency of the target filter and operates in the full configurable GBW range of a gm-C unit from 42kHz to 305MHz. The implementation is scalable to larger array sizes and enables the configuration of arbitrary filter functions with a deviation (sigma) smaller than 2.175%.
{"title":"An OTA-C signal processing FPAA with 305 MHz GBW and integrated frequency-independent filter tuning","authors":"Daniel DeDorigo, Y. Manoli","doi":"10.1109/ASSCC.2016.7844135","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844135","url":null,"abstract":"This paper presents a field-programmable analog array (FPAA) with on-chip automatic filter tuning in a 130nm CMOS technology. Parasitic capacitances in the signal nodes are compensated to eliminate the constraints on the regularity of the array and to enable the implementation of 12 capacitance arrays, 2 mixers and 62 OTAs on a die area of 0.8 mm2. The tuning technique is independent on the frequency of the target filter and operates in the full configurable GBW range of a gm-C unit from 42kHz to 305MHz. The implementation is scalable to larger array sizes and enables the configuration of arbitrary filter functions with a deviation (sigma) smaller than 2.175%.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128062814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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