Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844130
J. Kadomoto, T. Miyata, H. Amano, T. Kuroda
A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10−12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.
提出了一种三维片上网络(NoC)无线垂直总线碰撞检测方案。利用线圈之间的感应耦合，在所有堆叠芯片之间建立无线连接。通过感应磁场变化来检测数据碰撞。采用65nm SOI CMOS工艺制作了测试芯片。数据速率为0.8 Gb/s，误码率< 10−12。能效优于1.4 pJ/b。实现了碰撞检测电路，并对其工作进行了验证。
{"title":"An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips","authors":"J. Kadomoto, T. Miyata, H. Amano, T. Kuroda","doi":"10.1109/ASSCC.2016.7844130","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844130","url":null,"abstract":"A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10−12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121092842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844167
J. Tillak, S. Akhbari, Nimesh Shah, Ljubomir Radakovic, Liwei Lin, Jerald Yoo
A 1- to 8-ch scalable pMUT interface system with on-chip aberration compensation is presented for portable ultrasonic imaging applications. The system overcomes the necessity of area and power reduction for large ultrasonic arrays and presents the first hardware implementation on-chip calibration to improve the signal quality. The Charge Redistribution Transmitter (CR-TX) saves power by 32.8% while driving pMUT array at a wide range from 100 kHz to 5MHz. The CR-TX drives up to 500pF/channel load, which is 33× of the state-of-the-art ultrasonic driver reported to date. The on-chip adaptive beamformer supports five different media scans, has channel scalability and features the first demonstration of on-chip aberration compensation. The 8-ch system fabricated in 65nm CMOS occupies the core area of 700×1490μm, TX drives up to 6V while consuming 2.34μJ/scan.
{"title":"A 2.34μJ/scan acoustic power scalable charge-redistribution pMUT interface system with on-chip aberration compensation for portable ultrasonic applications","authors":"J. Tillak, S. Akhbari, Nimesh Shah, Ljubomir Radakovic, Liwei Lin, Jerald Yoo","doi":"10.1109/ASSCC.2016.7844167","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844167","url":null,"abstract":"A 1- to 8-ch scalable pMUT interface system with on-chip aberration compensation is presented for portable ultrasonic imaging applications. The system overcomes the necessity of area and power reduction for large ultrasonic arrays and presents the first hardware implementation on-chip calibration to improve the signal quality. The Charge Redistribution Transmitter (CR-TX) saves power by 32.8% while driving pMUT array at a wide range from 100 kHz to 5MHz. The CR-TX drives up to 500pF/channel load, which is 33× of the state-of-the-art ultrasonic driver reported to date. The on-chip adaptive beamformer supports five different media scans, has channel scalability and features the first demonstration of on-chip aberration compensation. The 8-ch system fabricated in 65nm CMOS occupies the core area of 700×1490μm, TX drives up to 6V while consuming 2.34μJ/scan.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121346027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844188
Chun-Ping Wang, Tai-Cheng Lee
A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 800-MHz fractional-N PLL fabricated in a 0.18-μm CMOS process. The experimental results demonstrate that the integrated rms jitter (10 kHz to 10 MHz) in the fractional-N PLL can be greatly improved from 26.45 ps to 3.91 ps. This fully-integrated PLL dissipates 23.5 mA from a 1.8-V supply.
{"title":"A technique for in-band phase noise reduction in fractional-N frequency synthesizers","authors":"Chun-Ping Wang, Tai-Cheng Lee","doi":"10.1109/ASSCC.2016.7844188","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844188","url":null,"abstract":"A fractional-N PLL employing a dual-frequency clock generator is proposed to achieve lowering the in-band phase noise. The architecture enables the PFD/CP to operate in the linear region to avoid noise-folding effect. An optimum operating condition can be tuned to achieve the best in-band phase noise. The proposed techniques are employed in a 800-MHz fractional-N PLL fabricated in a 0.18-μm CMOS process. The experimental results demonstrate that the integrated rms jitter (10 kHz to 10 MHz) in the fractional-N PLL can be greatly improved from 26.45 ps to 3.91 ps. This fully-integrated PLL dissipates 23.5 mA from a 1.8-V supply.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116921068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844149
G. Pini, D. Manstretta, R. Castello
A highly linear trans-impedance amplifier TIA is proposed to meet stringent linearity requirements of SAW-less frequency-division duplexing (FDD) LTE receivers with 20MHz channel bandwidth. In the proposed solution the operational amplifier is compensated exploiting the passive feedback network in order to achieve wide bandwidth and low power dissipation. The prototype in 28nm CMOS achieves 14dB of gain with 20MHz bandwidth and features 46 dBm IIP3 and 12μV in-band noise, with 5.4mW power dissipation and a filter FOM of 183 dB.
{"title":"Highly linear TIA for SAW-less FDD receivers","authors":"G. Pini, D. Manstretta, R. Castello","doi":"10.1109/ASSCC.2016.7844149","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844149","url":null,"abstract":"A highly linear trans-impedance amplifier TIA is proposed to meet stringent linearity requirements of SAW-less frequency-division duplexing (FDD) LTE receivers with 20MHz channel bandwidth. In the proposed solution the operational amplifier is compensated exploiting the passive feedback network in order to achieve wide bandwidth and low power dissipation. The prototype in 28nm CMOS achieves 14dB of gain with 20MHz bandwidth and features 46 dBm IIP3 and 12μV in-band noise, with 5.4mW power dissipation and a filter FOM of 183 dB.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132547666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844123
Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-ha Park, Hojin Park, Yoonmyung Lee
A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with < 500 μA load is as critical as active mode efficiency with > 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.
针对固态硬盘(SSD)应用，提出了一种高集成度高压双模升压转换器，在这种情况下，< 500 μA负载的待机模式效率与> 100 mA负载的主动模式效率同样重要。为了提高轻载工况下的效率，实现更宽的运行负载范围，采用平衡导通和开关损耗的最小化方法，并采用动态功率门控方案进行PFM模式运行。此外，采用基于时间的控制方案实现鲁棒双模式运行，使其能够在较低的峰值电流下运行，以达到最佳的损耗平衡。该转换器采用130 nm CMOS工艺制作，面积为1.7 mm2。在5.5 V输入提供12v输出的峰值效率为91%，在200 μA的极轻负载下效率为85%。它还实现了宽负载范围34.6 dB > 85%的效率和18.8 dB > 90%的效率。
{"title":"A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications","authors":"Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-ha Park, Hojin Park, Yoonmyung Lee","doi":"10.1109/ASSCC.2016.7844123","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844123","url":null,"abstract":"A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with < 500 μA load is as critical as active mode efficiency with > 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844192
Jiangyi Li, Jae-sun Seo, I. Kymissis, Mingoo Seok
We present a triple-mode energy-harvesting power management unit (PMU) that interfaces a photovoltaic (PV) cell and delivers a regulated supply (VLoad) of 0.45V while storing remaining energy in a 3V rechargeable battery. The objective is to maximize the end-to-end conversion efficiency of the PMU against the variabilities of harvested energy and load power dissipation. Specifically, it uses an intermediate energy-storage capacitor to minimize the involvement (charging or discharging) of a battery in the conversion process over time. The experiments show that the proposed PMU can achieve 2.2× higher end-to-end conversion efficiency than the conventional dual-mode architectures when faced with typical variabilities in harvested energy and load power dissipation.
{"title":"Triple-mode photovoltaic power management: Achieving high efficiency against harvesting and load variability","authors":"Jiangyi Li, Jae-sun Seo, I. Kymissis, Mingoo Seok","doi":"10.1109/ASSCC.2016.7844192","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844192","url":null,"abstract":"We present a triple-mode energy-harvesting power management unit (PMU) that interfaces a photovoltaic (PV) cell and delivers a regulated supply (VLoad) of 0.45V while storing remaining energy in a 3V rechargeable battery. The objective is to maximize the end-to-end conversion efficiency of the PMU against the variabilities of harvested energy and load power dissipation. Specifically, it uses an intermediate energy-storage capacitor to minimize the involvement (charging or discharging) of a battery in the conversion process over time. The experiments show that the proposed PMU can achieve 2.2× higher end-to-end conversion efficiency than the conventional dual-mode architectures when faced with typical variabilities in harvested energy and load power dissipation.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122583546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844146
D. Guermandi, Qixian Shi, A. Dewilde, V. Derudder, U. Ahmad, A. Spagnolo, A. Bourdoux, P. Wambacq, W. V. Thillo
This paper describes a 28nm fully integrated 79 GHz Phase Modulated radar SoC including 2TX, 2RX and the mm-wave frequency generation. A custom digital core generates the pseudo random sequence and performs correlation and accumulation of the digitized received data. With 1W power consumption, 7.5 cm range resolution is achieved while antennas arrangement allows for 5° resolution over ±60° elevation and azimuth scan in 2×2 code domain MIMO operation.
{"title":"A 79GHz 2×2 MIMO PMCW radar SoC in 28nm CMOS","authors":"D. Guermandi, Qixian Shi, A. Dewilde, V. Derudder, U. Ahmad, A. Spagnolo, A. Bourdoux, P. Wambacq, W. V. Thillo","doi":"10.1109/ASSCC.2016.7844146","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844146","url":null,"abstract":"This paper describes a 28nm fully integrated 79 GHz Phase Modulated radar SoC including 2TX, 2RX and the mm-wave frequency generation. A custom digital core generates the pseudo random sequence and performs correlation and accumulation of the digitized received data. With 1W power consumption, 7.5 cm range resolution is achieved while antennas arrangement allows for 5° resolution over ±60° elevation and azimuth scan in 2×2 code domain MIMO operation.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124267856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844201
H. Sun, J. Muhlestein, Spencer Leuenberger, Kazuki Sobue, K. Hamashita, U. Moon
A reference-free stochastic ADC is proposed by utilizing both spatial averaging and oversampling noise-shaping schemes. By implementing multiple VCO-based quantizers in parallel, stochastic spatial averaging for quantization errors is inherently obtained. In addition, 1st-order noise shaping of a VCO-based quantizer is achieved in an open-loop oversampling configuration. By resolving a faster conversion rate, this open-loop structure eliminates biasing, loop filter, sample-and-hold, and external reference, and it consists of only delay cells and digital logic. The proof-of-concept prototype which includes eight VCO-based quantizers and spatial averaging estimator is implemented in a 0.18 μm CMOS process, demonstrating 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, with 116 mW power consumption. Measurement results reveal that the eight channel stochastic ADC provides an average 9 dB SQNR improvement due to the spatial averaging.
{"title":"A 50 MHz bandwidth 54.2 dB SNDR reference-free stochastic ADC using VCO-based quantizers","authors":"H. Sun, J. Muhlestein, Spencer Leuenberger, Kazuki Sobue, K. Hamashita, U. Moon","doi":"10.1109/ASSCC.2016.7844201","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844201","url":null,"abstract":"A reference-free stochastic ADC is proposed by utilizing both spatial averaging and oversampling noise-shaping schemes. By implementing multiple VCO-based quantizers in parallel, stochastic spatial averaging for quantization errors is inherently obtained. In addition, 1st-order noise shaping of a VCO-based quantizer is achieved in an open-loop oversampling configuration. By resolving a faster conversion rate, this open-loop structure eliminates biasing, loop filter, sample-and-hold, and external reference, and it consists of only delay cells and digital logic. The proof-of-concept prototype which includes eight VCO-based quantizers and spatial averaging estimator is implemented in a 0.18 μm CMOS process, demonstrating 54.2 dB and 45.4 dB SNDR for 50 MHz and 100 MHz bandwidths, with 116 mW power consumption. Measurement results reveal that the eight channel stochastic ADC provides an average 9 dB SQNR improvement due to the spatial averaging.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121831027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844120
Masayoshi Oshiro, T. Maruyama, T. Tokairin, Yuki Tuda, Tong Wang, N. Koide, Y. Ogasawara, T. Ta, H. Yoshida, K. Sami
A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2 mA RX and 3.5 mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture that avoids out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of −93 dBm and maximum output power of 0 dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the world's lowest current consumption for both RX and TX modes in the published product-level SoCs.
{"title":"A 3.2 mA-RX 3.5 mA-TX fully integrated SoC for Bluetooth Low Energy","authors":"Masayoshi Oshiro, T. Maruyama, T. Tokairin, Yuki Tuda, Tong Wang, N. Koide, Y. Ogasawara, T. Ta, H. Yoshida, K. Sami","doi":"10.1109/ASSCC.2016.7844120","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844120","url":null,"abstract":"A fully-integrated system-on-chip (SoC) for Bluetooth Low Energy (BLE) with 3.2 mA RX and 3.5 mA TX current consumption is presented. To achieve both low current consumption and high performance, the SoC employs a sliding-IF architecture that avoids out-of-band-blocking signals, a power management unit with improved efficiency, and techniques to reduce current in core circuits. The SoC achieves RX sensitivity of −93 dBm and maximum output power of 0 dBm. The SoC is in compliance with version 4.2 of the Bluetooth specifications and with the radio regulations of the FCC, ETSI, and ARIB. The SoC achieves the world's lowest current consumption for both RX and TX modes in the published product-level SoCs.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133939594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844187
Fan Yang, Hangyan Guo, Runhua Wang, Zherui Zhang, Junhua Liu, H. Liao
This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from pre- and background-calibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for fractional operation is proposed to lower architecture complexity and minimal design effort. A high frequency resolution digitally-controlled oscillator with an equivalent variable inductor is also utilized. A 2.2-GHz digital PLL has been implemented in a 55-nm CMOS technology. The frequency resolution of DCO is 1.58 kHz, and in-band phase noise of PLL is −104.4 dBc/Hz. The PLL consumes 2.43 mA from a 1.2-V supply voltage and occupies an active area of 0.216 mm2.
{"title":"A low-power calibration-free fractional-N digital PLL with high linear phase interpolator","authors":"Fan Yang, Hangyan Guo, Runhua Wang, Zherui Zhang, Junhua Liu, H. Liao","doi":"10.1109/ASSCC.2016.7844187","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844187","url":null,"abstract":"This paper presents a low-complexity calibration-free digital PLL architecture. The PLL adopts a fractional frequency divider with a harmonic rejection current steering phase interpolator which is free from pre- and background-calibration. The harmonic rejection technology could improve linearity of interpolator. A simplified glitch-free control logic for fractional operation is proposed to lower architecture complexity and minimal design effort. A high frequency resolution digitally-controlled oscillator with an equivalent variable inductor is also utilized. A 2.2-GHz digital PLL has been implemented in a 55-nm CMOS technology. The frequency resolution of DCO is 1.58 kHz, and in-band phase noise of PLL is −104.4 dBc/Hz. The PLL consumes 2.43 mA from a 1.2-V supply voltage and occupies an active area of 0.216 mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115118939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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