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2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)最新文献

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Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique 利用泵送电容和线电感技术实现DC-DC升压变换器的超低电压纹波
Pub Date : 1900-01-01 DOI: 10.1109/ASSCC.2016.7844195
Chen-Fan Tang, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai
Overall consideration including bonding wire effects is needed because conventional DC-DC boost converter used in energy harvesting systems suffers from large output voltage ripple in steady state and transient response. Thus, this paper proposed the pumping capacitor and wire inductance (PCWI) technique to suppress output voltage ripple to an ultra-low value. Small steady state voltage across the wire inductance (WI) and continuous WI current can be ensured by an additional pumping capacitor (PC). Moreover, even in case of an ultra-low output voltage ripple, the proposed pseudo-inductor current (PIC) technique regenerates the inductor current information to eliminate the instability problem in conventional ripple-based control techniques. Transient recovery time and output voltage variation can be reduced simultaneously. Test chip was fabricated in 0.18-μm 5V/24V CMOS process when input voltage of 1.8–5.5V is converted to 12.8V. Experimental results show the ratio of output voltage ripple and output voltage is reduced to 0.04%. Measured power conversion efficiency is around 92% at 100mA and 96% at 0.1mA.
由于用于能量收集系统的传统DC-DC升压变换器在稳态和瞬态响应中存在较大的输出电压纹波,因此需要全面考虑包括键合线效应在内的因素。为此,本文提出了泵浦电容加线电感(PCWI)技术,将输出电压纹波抑制到超低值。通过一个额外的泵送电容(PC),可以确保小的稳态电压通过导线电感(WI)和连续WI电流。此外,即使在超低输出电压纹波的情况下,伪电感电流(PIC)技术也能重新生成电感电流信息,从而消除传统基于纹波控制技术的不稳定性问题。可同时减少暂态恢复时间和输出电压变化。将输入电压1.8 ~ 5.5 v转换为12.8V,采用0.18-μm 5V/24V CMOS工艺制备测试芯片。实验结果表明,输出电压纹波与输出电压的比值降至0.04%。测量的功率转换效率在100mA时约为92%,在0.1mA时为96%。
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引用次数: 2
A 41.3pJ/26.7pJ per neuron weight RBM processor for on-chip learning/inference applications 用于片上学习/推理应用的41.3pJ/26.7pJ /神经元权重RBM处理器
Pub Date : 1900-01-01 DOI: 10.1109/ASSCC.2016.7844186
Chang-Hung Tsai, Wan-Ju Yu, W. Wong, Chen-Yi Lee
A restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning applications in this paper. Featuring neural network (NN) model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism in learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2M gates and 128kB SRAM with 8.8mm2 area. Operated at 1.2V and 210MHz, this chip respectively achieves 114.3x and 3.9x faster processing time than CPU and GPGPU. And the proposed RBM-P chip consumes 41.3pJ and 26.7pJ per neuron weight (NW) for learning and inference, respectively.
本文提出了一种支持片上学习和推理的受限玻尔兹曼机(RBM)处理器(RBM- p)。该系统采用神经网络(NN)模型简化来节省外部内存带宽,低功耗神经元二值化器(LPNB)具有动态时钟门控和面积高效的类神经网络激活函数计算器,用户自定义连接映射(UDCM)用于节省计算时间和带宽,以及学习过程中的早期停止(ES)机制,该系统集成了32个RBM内核,每层最大4k神经元,每个样本128个候选样本用于机器学习应用。RBM-P芯片采用65nm CMOS技术,成本为220万个栅极和128kB SRAM,面积为8.8mm2。该芯片工作在1.2V和210MHz下,处理速度分别比CPU和GPGPU快114.3倍和3.9倍。RBM-P芯片每个神经元权重(NW)分别消耗41.3pJ和26.7pJ进行学习和推理。
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引用次数: 1
期刊
2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)
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