Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844166
H. Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, D. Sun, Shin-Rung Wu, H. Liao, Jonathan Chang
In low voltage SRAM for IoT application, although static noise margin (SNM) and write margin (WM) decide VMIN, Icell / Ioff ratio and Icell are also important in order to keep performance and achieve better operating efficiency. We propose a new mixed Vth RP design which can achieve better Icell and Icell / Ioff ratio. Furthermore, combination of the proposed mixed Vth and boosted read wordline (RWL) scheme improves the worst case bitline delay time by 72.3% at 0.45V. In the measurement results, we confirmed a minimum operating voltage (VMIN) for the 64 Kb SRAM of 0.370 V with 99% yield at room temperature.
{"title":"A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications","authors":"H. Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, D. Sun, Shin-Rung Wu, H. Liao, Jonathan Chang","doi":"10.1109/ASSCC.2016.7844166","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844166","url":null,"abstract":"In low voltage SRAM for IoT application, although static noise margin (SNM) and write margin (WM) decide VMIN, Icell / Ioff ratio and Icell are also important in order to keep performance and achieve better operating efficiency. We propose a new mixed Vth RP design which can achieve better Icell and Icell / Ioff ratio. Furthermore, combination of the proposed mixed Vth and boosted read wordline (RWL) scheme improves the worst case bitline delay time by 72.3% at 0.45V. In the measurement results, we confirmed a minimum operating voltage (VMIN) for the 64 Kb SRAM of 0.370 V with 99% yield at room temperature.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116485588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844153
Shengshuo Lu, Zhengya Zhang, M. Papaefthymiou
This paper presents an ultra-high-performance neural network engine fabricated in a 65nm CMOS technology. The 0.9mm2 core relies on an energy-efficient resonant clock mesh running at 5.5GHz to achieve 0.76 8-bit TOPS, improving throughput by over 4x, area efficiency by over 8×, and energy-delay-area product by over 1.8× compared to previous state-of-the-art neural network designs. Achieving a charge recovery rate of 63%, the resonant clock mesh enables the deployment of a deeply-pipelined stream architecture and high-speed stream buffers with a sub-5W power consumption.
{"title":"A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh","authors":"Shengshuo Lu, Zhengya Zhang, M. Papaefthymiou","doi":"10.1109/ASSCC.2016.7844153","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844153","url":null,"abstract":"This paper presents an ultra-high-performance neural network engine fabricated in a 65nm CMOS technology. The 0.9mm2 core relies on an energy-efficient resonant clock mesh running at 5.5GHz to achieve 0.76 8-bit TOPS, improving throughput by over 4x, area efficiency by over 8×, and energy-delay-area product by over 1.8× compared to previous state-of-the-art neural network designs. Achieving a charge recovery rate of 63%, the resonant clock mesh enables the deployment of a deeply-pipelined stream architecture and high-speed stream buffers with a sub-5W power consumption.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"532 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123449130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844136
Lilan Yu, M. Miyahara, A. Matsuzawa
This paper presents a dynamic pipelined analog-to-digital converter (ADC). A time-domain linearization technique is proposed to enhance the linearity of dynamic amplifiers. Also, an inverter threshold voltage based method is proposed to calibrate the common mode voltage of the dynamic amplifier. Furthermore, a capacitor digital-to-analog converter (CDAC) based method is used to calibrate the stage-gain of pipelined ADC. The prototype designed in a 65-nm CMOS technology realizes a 50.5-dB SNDR at a 500-MS/s sampling rate with a Nyquist input. It consumes 6.0-mW at a 1.2-V power supply and achieves 44 fJ per conversion step.
本文提出了一种动态流水线模数转换器(ADC)。提出了一种时域线性化技术来提高动态放大器的线性度。同时，提出了一种基于逆变器阈值电压的动态放大器共模电压标定方法。此外，采用基于电容数模转换器(CDAC)的方法对流水线ADC的级增益进行了标定。采用65纳米CMOS技术设计的原型在500 ms /s采样率下实现了50.5 db的SNDR，并使用奈奎斯特输入。它在1.2 v电源下消耗6.0 mw，每个转换步骤达到44 fJ。
{"title":"A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers","authors":"Lilan Yu, M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2016.7844136","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844136","url":null,"abstract":"This paper presents a dynamic pipelined analog-to-digital converter (ADC). A time-domain linearization technique is proposed to enhance the linearity of dynamic amplifiers. Also, an inverter threshold voltage based method is proposed to calibrate the common mode voltage of the dynamic amplifier. Furthermore, a capacitor digital-to-analog converter (CDAC) based method is used to calibrate the stage-gain of pipelined ADC. The prototype designed in a 65-nm CMOS technology realizes a 50.5-dB SNDR at a 500-MS/s sampling rate with a Nyquist input. It consumes 6.0-mW at a 1.2-V power supply and achieves 44 fJ per conversion step.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126617689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844128
Chih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin
This paper presents an area-efficient and fast-response CMOS Hall sensor system for a camera autofocus system. The prototype comprises of a Hall sensor and a capacitively-coupled instrumentation amplifier (CCIA). The Hall sensor adopts the spinning current technique to mitigate the Hall element offset. In the CCIA, the T-capacitor network is employed considering the capacitor matching requirement and the chip area. The amplifier offset is further suppressed by a ripple-reduction loop. This chip is measured with Helmholtz coil, Solenoid, and NMR system. Implemented in a 0.18-μm CMOS process, it achieves 564 μTrms in 180-kHz BW. The linearity error is < 0.5% over ±100-mT range. The power consumption is 1.19 mW, and the area is 0.12 mm2.
{"title":"An area-efficient wideband CMOS hall sensor system for camera autofocus systems","authors":"Chih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2016.7844128","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844128","url":null,"abstract":"This paper presents an area-efficient and fast-response CMOS Hall sensor system for a camera autofocus system. The prototype comprises of a Hall sensor and a capacitively-coupled instrumentation amplifier (CCIA). The Hall sensor adopts the spinning current technique to mitigate the Hall element offset. In the CCIA, the T-capacitor network is employed considering the capacitor matching requirement and the chip area. The amplifier offset is further suppressed by a ripple-reduction loop. This chip is measured with Helmholtz coil, Solenoid, and NMR system. Implemented in a 0.18-μm CMOS process, it achieves 564 μTrms in 180-kHz BW. The linearity error is < 0.5% over ±100-mT range. The power consumption is 1.19 mW, and the area is 0.12 mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125322722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844156
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, U. Seng-Pan, R. Martins
This paper presents a calibration scheme for reference error caused by signal dependent switching transient in a high speed SAR ADC. The scheme has a little hardware overhead, which is not dependent on the type of the input signal and is able to run in the background without interrupting the ADC's normal operation. The calibration along with the SAR ADC are implemented in a 65 nm CMOS and the measurement results show that the proposed scheme effectively improves the SNDR of an 11b SAR ADC by ∼9 dB. The calibration allows the placement of only 3 pF decoupling capacitance in the reference voltages. The prototype achieves 100 MS/s sampling rate with a total power consumption of 1.6 mW at a 1.2 V supply. Plus, it exhibits a 59.03 dB and 60.4 dB SNDR at Nyquist and low input frequency, respectively, yielding a Walden FoM@Nyquist of 21.9 fJ/conv.-step. The total core area is 0.011 mm2 which includes the decoupling capacitor.
{"title":"A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages","authors":"Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2016.7844156","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844156","url":null,"abstract":"This paper presents a calibration scheme for reference error caused by signal dependent switching transient in a high speed SAR ADC. The scheme has a little hardware overhead, which is not dependent on the type of the input signal and is able to run in the background without interrupting the ADC's normal operation. The calibration along with the SAR ADC are implemented in a 65 nm CMOS and the measurement results show that the proposed scheme effectively improves the SNDR of an 11b SAR ADC by ∼9 dB. The calibration allows the placement of only 3 pF decoupling capacitance in the reference voltages. The prototype achieves 100 MS/s sampling rate with a total power consumption of 1.6 mW at a 1.2 V supply. Plus, it exhibits a 59.03 dB and 60.4 dB SNDR at Nyquist and low input frequency, respectively, yielding a Walden FoM@Nyquist of 21.9 fJ/conv.-step. The total core area is 0.011 mm2 which includes the decoupling capacitor.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134131774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844199
Beichen Zhang, Runjiang Dou, Liyuan Liu, N. Wu
A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the chip area. The prototype modulator has 91.2 dB peak SNDR in 24 kHz and consumes only 94μW from a 1-V supply, achieving a FOM of 66.2fJ/conv. The active core area is only 0.11mm2.
{"title":"A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator","authors":"Beichen Zhang, Runjiang Dou, Liyuan Liu, N. Wu","doi":"10.1109/ASSCC.2016.7844199","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844199","url":null,"abstract":"A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the chip area. The prototype modulator has 91.2 dB peak SNDR in 24 kHz and consumes only 94μW from a 1-V supply, achieving a FOM of 66.2fJ/conv. The active core area is only 0.11mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844182
Sung-Geun Kim, Tongsung Kim, D. Kwon, W. Choi
We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, the same data transition information can be directly used for implementing 2-tap pre-emphasize and, consequently, the need for the additional serializer required in the conventional pre-emphasis circuits can be eliminated, resulting in further reduced power consumption. A prototype transmitter realized in 65nm CMOS technology achieves energy efficiencies of 0.202 pJ/bit at 5 Gb/s and 0.3 pJ/bit at 8 Gb/s for 150 mVpp,d output voltage swing without pre-emphasis, and 0.252 pJ/bit at 5 Gb/s and 0.333 pJ/bit at 8 Gb/s with 2-tap pre-emphasis providing 6-dB equalization gain. To the best of our knowledge, these are the lowest energy efficiencies achieved for wireline transmitters realized in 65nm CMOS technology.
{"title":"A 5–8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization","authors":"Sung-Geun Kim, Tongsung Kim, D. Kwon, W. Choi","doi":"10.1109/ASSCC.2016.7844182","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844182","url":null,"abstract":"We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, the same data transition information can be directly used for implementing 2-tap pre-emphasize and, consequently, the need for the additional serializer required in the conventional pre-emphasis circuits can be eliminated, resulting in further reduced power consumption. A prototype transmitter realized in 65nm CMOS technology achieves energy efficiencies of 0.202 pJ/bit at 5 Gb/s and 0.3 pJ/bit at 8 Gb/s for 150 mVpp,d output voltage swing without pre-emphasis, and 0.252 pJ/bit at 5 Gb/s and 0.333 pJ/bit at 8 Gb/s with 2-tap pre-emphasis providing 6-dB equalization gain. To the best of our knowledge, these are the lowest energy efficiencies achieved for wireline transmitters realized in 65nm CMOS technology.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844149
G. Pini, D. Manstretta, R. Castello
A highly linear trans-impedance amplifier TIA is proposed to meet stringent linearity requirements of SAW-less frequency-division duplexing (FDD) LTE receivers with 20MHz channel bandwidth. In the proposed solution the operational amplifier is compensated exploiting the passive feedback network in order to achieve wide bandwidth and low power dissipation. The prototype in 28nm CMOS achieves 14dB of gain with 20MHz bandwidth and features 46 dBm IIP3 and 12μV in-band noise, with 5.4mW power dissipation and a filter FOM of 183 dB.
{"title":"Highly linear TIA for SAW-less FDD receivers","authors":"G. Pini, D. Manstretta, R. Castello","doi":"10.1109/ASSCC.2016.7844149","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844149","url":null,"abstract":"A highly linear trans-impedance amplifier TIA is proposed to meet stringent linearity requirements of SAW-less frequency-division duplexing (FDD) LTE receivers with 20MHz channel bandwidth. In the proposed solution the operational amplifier is compensated exploiting the passive feedback network in order to achieve wide bandwidth and low power dissipation. The prototype in 28nm CMOS achieves 14dB of gain with 20MHz bandwidth and features 46 dBm IIP3 and 12μV in-band noise, with 5.4mW power dissipation and a filter FOM of 183 dB.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132547666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844123
Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-ha Park, Hojin Park, Yoonmyung Lee
A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with < 500 μA load is as critical as active mode efficiency with > 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.
针对固态硬盘(SSD)应用，提出了一种高集成度高压双模升压转换器，在这种情况下，< 500 μA负载的待机模式效率与> 100 mA负载的主动模式效率同样重要。为了提高轻载工况下的效率，实现更宽的运行负载范围，采用平衡导通和开关损耗的最小化方法，并采用动态功率门控方案进行PFM模式运行。此外，采用基于时间的控制方案实现鲁棒双模式运行，使其能够在较低的峰值电流下运行，以达到最佳的损耗平衡。该转换器采用130 nm CMOS工艺制作，面积为1.7 mm2。在5.5 V输入提供12v输出的峰值效率为91%，在200 μA的极轻负载下效率为85%。它还实现了宽负载范围34.6 dB > 85%的效率和18.8 dB > 90%的效率。
{"title":"A high efficiency wide-load-range asynchronous boost converter with time-based dual-mode control for SSD applications","authors":"Kyoungjin Lee, Haneul Kim, Jehyung Yoon, Hyoung-Seok Oh, Byeong-ha Park, Hojin Park, Yoonmyung Lee","doi":"10.1109/ASSCC.2016.7844123","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844123","url":null,"abstract":"A highly integrated, high-voltage dual-mode boost converter is presented for solid-state drive (SSD) applications, where standby mode efficiency with < 500 μA load is as critical as active mode efficiency with > 100 mA load. To enhance efficiency in light load condition and to achieve wide operation load range, loss minimization by balancing conduction and switching loss is adopted and dynamic power gating scheme is applied for PFM mode operation. Moreover, robust dual mode operation is implemented with time-based control scheme, which enables operation with lower peak current for optimal loss balancing. The proposed converter is fabricated in 130 nm CMOS process with an area of 1.7 mm2. The measured efficiency for supplying 12 V output from 5.5 V input is 91% at its peak and 85% with extremely light load of 200 μA. It also achieves wide load range of 34.6 dB for > 85% efficiency and 18.8 dB for > 90% efficiency.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133924610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844130
J. Kadomoto, T. Miyata, H. Amano, T. Kuroda
A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10−12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.
提出了一种三维片上网络(NoC)无线垂直总线碰撞检测方案。利用线圈之间的感应耦合，在所有堆叠芯片之间建立无线连接。通过感应磁场变化来检测数据碰撞。采用65nm SOI CMOS工艺制作了测试芯片。数据速率为0.8 Gb/s，误码率< 10−12。能效优于1.4 pJ/b。实现了碰撞检测电路，并对其工作进行了验证。
{"title":"An inductive-coupling bus with collision detection scheme using magnetic field variation for 3-D network-on-chips","authors":"J. Kadomoto, T. Miyata, H. Amano, T. Kuroda","doi":"10.1109/ASSCC.2016.7844130","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844130","url":null,"abstract":"A wireless vertical bus with collision detection scheme for 3-D network-on-chips (NoC) is presented. Utilizing inductive-coupling between coils, wireless connection between all stacked chips is established. Data collision is detected by sensing magnetic field variation. A test chip is fabricated in 65 nm SOI CMOS technology. A data rate of 0.8 Gb/s with a BER < 10−12 is achieved. The energy efficiency is better than 1.4 pJ/b. A collision detection circuit is implemented and its operation is confirmed.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121092842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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