Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844166
H. Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, D. Sun, Shin-Rung Wu, H. Liao, Jonathan Chang
In low voltage SRAM for IoT application, although static noise margin (SNM) and write margin (WM) decide VMIN, Icell / Ioff ratio and Icell are also important in order to keep performance and achieve better operating efficiency. We propose a new mixed Vth RP design which can achieve better Icell and Icell / Ioff ratio. Furthermore, combination of the proposed mixed Vth and boosted read wordline (RWL) scheme improves the worst case bitline delay time by 72.3% at 0.45V. In the measurement results, we confirmed a minimum operating voltage (VMIN) for the 64 Kb SRAM of 0.370 V with 99% yield at room temperature.
{"title":"A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted WL scheme for IoT applications","authors":"H. Fujiwara, Yen-Huei Chen, Chih-Yu Lin, Wei-Cheng Wu, D. Sun, Shin-Rung Wu, H. Liao, Jonathan Chang","doi":"10.1109/ASSCC.2016.7844166","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844166","url":null,"abstract":"In low voltage SRAM for IoT application, although static noise margin (SNM) and write margin (WM) decide VMIN, Icell / Ioff ratio and Icell are also important in order to keep performance and achieve better operating efficiency. We propose a new mixed Vth RP design which can achieve better Icell and Icell / Ioff ratio. Furthermore, combination of the proposed mixed Vth and boosted read wordline (RWL) scheme improves the worst case bitline delay time by 72.3% at 0.45V. In the measurement results, we confirmed a minimum operating voltage (VMIN) for the 64 Kb SRAM of 0.370 V with 99% yield at room temperature.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116485588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844153
Shengshuo Lu, Zhengya Zhang, M. Papaefthymiou
This paper presents an ultra-high-performance neural network engine fabricated in a 65nm CMOS technology. The 0.9mm2 core relies on an energy-efficient resonant clock mesh running at 5.5GHz to achieve 0.76 8-bit TOPS, improving throughput by over 4x, area efficiency by over 8×, and energy-delay-area product by over 1.8× compared to previous state-of-the-art neural network designs. Achieving a charge recovery rate of 63%, the resonant clock mesh enables the deployment of a deeply-pipelined stream architecture and high-speed stream buffers with a sub-5W power consumption.
{"title":"A 5.5GHz 0.84TOPS/mm2 neural network engine with stream architecture and resonant clock mesh","authors":"Shengshuo Lu, Zhengya Zhang, M. Papaefthymiou","doi":"10.1109/ASSCC.2016.7844153","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844153","url":null,"abstract":"This paper presents an ultra-high-performance neural network engine fabricated in a 65nm CMOS technology. The 0.9mm2 core relies on an energy-efficient resonant clock mesh running at 5.5GHz to achieve 0.76 8-bit TOPS, improving throughput by over 4x, area efficiency by over 8×, and energy-delay-area product by over 1.8× compared to previous state-of-the-art neural network designs. Achieving a charge recovery rate of 63%, the resonant clock mesh enables the deployment of a deeply-pipelined stream architecture and high-speed stream buffers with a sub-5W power consumption.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"532 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123449130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844136
Lilan Yu, M. Miyahara, A. Matsuzawa
This paper presents a dynamic pipelined analog-to-digital converter (ADC). A time-domain linearization technique is proposed to enhance the linearity of dynamic amplifiers. Also, an inverter threshold voltage based method is proposed to calibrate the common mode voltage of the dynamic amplifier. Furthermore, a capacitor digital-to-analog converter (CDAC) based method is used to calibrate the stage-gain of pipelined ADC. The prototype designed in a 65-nm CMOS technology realizes a 50.5-dB SNDR at a 500-MS/s sampling rate with a Nyquist input. It consumes 6.0-mW at a 1.2-V power supply and achieves 44 fJ per conversion step.
本文提出了一种动态流水线模数转换器(ADC)。提出了一种时域线性化技术来提高动态放大器的线性度。同时，提出了一种基于逆变器阈值电压的动态放大器共模电压标定方法。此外，采用基于电容数模转换器(CDAC)的方法对流水线ADC的级增益进行了标定。采用65纳米CMOS技术设计的原型在500 ms /s采样率下实现了50.5 db的SNDR，并使用奈奎斯特输入。它在1.2 v电源下消耗6.0 mw，每个转换步骤达到44 fJ。
{"title":"A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers","authors":"Lilan Yu, M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2016.7844136","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844136","url":null,"abstract":"This paper presents a dynamic pipelined analog-to-digital converter (ADC). A time-domain linearization technique is proposed to enhance the linearity of dynamic amplifiers. Also, an inverter threshold voltage based method is proposed to calibrate the common mode voltage of the dynamic amplifier. Furthermore, a capacitor digital-to-analog converter (CDAC) based method is used to calibrate the stage-gain of pipelined ADC. The prototype designed in a 65-nm CMOS technology realizes a 50.5-dB SNDR at a 500-MS/s sampling rate with a Nyquist input. It consumes 6.0-mW at a 1.2-V power supply and achieves 44 fJ per conversion step.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126617689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844128
Chih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin
This paper presents an area-efficient and fast-response CMOS Hall sensor system for a camera autofocus system. The prototype comprises of a Hall sensor and a capacitively-coupled instrumentation amplifier (CCIA). The Hall sensor adopts the spinning current technique to mitigate the Hall element offset. In the CCIA, the T-capacitor network is employed considering the capacitor matching requirement and the chip area. The amplifier offset is further suppressed by a ripple-reduction loop. This chip is measured with Helmholtz coil, Solenoid, and NMR system. Implemented in a 0.18-μm CMOS process, it achieves 564 μTrms in 180-kHz BW. The linearity error is < 0.5% over ±100-mT range. The power consumption is 1.19 mW, and the area is 0.12 mm2.
{"title":"An area-efficient wideband CMOS hall sensor system for camera autofocus systems","authors":"Chih-Chan Tu, Kuan-Chung Chen, Tsung-Yu Wu, Tsung-Hsien Lin","doi":"10.1109/ASSCC.2016.7844128","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844128","url":null,"abstract":"This paper presents an area-efficient and fast-response CMOS Hall sensor system for a camera autofocus system. The prototype comprises of a Hall sensor and a capacitively-coupled instrumentation amplifier (CCIA). The Hall sensor adopts the spinning current technique to mitigate the Hall element offset. In the CCIA, the T-capacitor network is employed considering the capacitor matching requirement and the chip area. The amplifier offset is further suppressed by a ripple-reduction loop. This chip is measured with Helmholtz coil, Solenoid, and NMR system. Implemented in a 0.18-μm CMOS process, it achieves 564 μTrms in 180-kHz BW. The linearity error is < 0.5% over ±100-mT range. The power consumption is 1.19 mW, and the area is 0.12 mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125322722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844156
Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, U. Seng-Pan, R. Martins
This paper presents a calibration scheme for reference error caused by signal dependent switching transient in a high speed SAR ADC. The scheme has a little hardware overhead, which is not dependent on the type of the input signal and is able to run in the background without interrupting the ADC's normal operation. The calibration along with the SAR ADC are implemented in a 65 nm CMOS and the measurement results show that the proposed scheme effectively improves the SNDR of an 11b SAR ADC by ∼9 dB. The calibration allows the placement of only 3 pF decoupling capacitance in the reference voltages. The prototype achieves 100 MS/s sampling rate with a total power consumption of 1.6 mW at a 1.2 V supply. Plus, it exhibits a 59.03 dB and 60.4 dB SNDR at Nyquist and low input frequency, respectively, yielding a Walden FoM@Nyquist of 21.9 fJ/conv.-step. The total core area is 0.011 mm2 which includes the decoupling capacitor.
{"title":"A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages","authors":"Chi-Hang Chan, Yan Zhu, Iok-Meng Ho, Wai-Hong Zhang, Chon-Lam Lio, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2016.7844156","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844156","url":null,"abstract":"This paper presents a calibration scheme for reference error caused by signal dependent switching transient in a high speed SAR ADC. The scheme has a little hardware overhead, which is not dependent on the type of the input signal and is able to run in the background without interrupting the ADC's normal operation. The calibration along with the SAR ADC are implemented in a 65 nm CMOS and the measurement results show that the proposed scheme effectively improves the SNDR of an 11b SAR ADC by ∼9 dB. The calibration allows the placement of only 3 pF decoupling capacitance in the reference voltages. The prototype achieves 100 MS/s sampling rate with a total power consumption of 1.6 mW at a 1.2 V supply. Plus, it exhibits a 59.03 dB and 60.4 dB SNDR at Nyquist and low input frequency, respectively, yielding a Walden FoM@Nyquist of 21.9 fJ/conv.-step. The total core area is 0.011 mm2 which includes the decoupling capacitor.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"11 14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134131774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844199
Beichen Zhang, Runjiang Dou, Liyuan Liu, N. Wu
A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the chip area. The prototype modulator has 91.2 dB peak SNDR in 24 kHz and consumes only 94μW from a 1-V supply, achieving a FOM of 66.2fJ/conv. The active core area is only 0.11mm2.
{"title":"A 91.2dB SNDR 66.2fJ/conv. dynamic amplifier based 24kHz ΔΣ modulator","authors":"Beichen Zhang, Runjiang Dou, Liyuan Liu, N. Wu","doi":"10.1109/ASSCC.2016.7844199","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844199","url":null,"abstract":"A discrete time single loop 2nd order 5-bit ΔΣ modulator is implemented in 65nm CMOS for digital audio and sensor applications. We propose a power efficient integrator based on periodical-reset dynamic amplifier without static current consumption. A passive inter-stage sampling method is proposed which prevents active buffer. A 3-D capacitance layout implementation method is employed to saving the chip area. The prototype modulator has 91.2 dB peak SNDR in 24 kHz and consumes only 94μW from a 1-V supply, achieving a FOM of 66.2fJ/conv. The active core area is only 0.11mm2.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133101234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844182
Sung-Geun Kim, Tongsung Kim, D. Kwon, W. Choi
We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, the same data transition information can be directly used for implementing 2-tap pre-emphasize and, consequently, the need for the additional serializer required in the conventional pre-emphasis circuits can be eliminated, resulting in further reduced power consumption. A prototype transmitter realized in 65nm CMOS technology achieves energy efficiencies of 0.202 pJ/bit at 5 Gb/s and 0.3 pJ/bit at 8 Gb/s for 150 mVpp,d output voltage swing without pre-emphasis, and 0.252 pJ/bit at 5 Gb/s and 0.333 pJ/bit at 8 Gb/s with 2-tap pre-emphasis providing 6-dB equalization gain. To the best of our knowledge, these are the lowest energy efficiencies achieved for wireline transmitters realized in 65nm CMOS technology.
{"title":"A 5–8 Gb/s low-power transmitter with 2-tap pre-emphasis based on toggling serialization","authors":"Sung-Geun Kim, Tongsung Kim, D. Kwon, W. Choi","doi":"10.1109/ASSCC.2016.7844182","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844182","url":null,"abstract":"We demonstrate a low-power wireline transmitter with 2-tap pre-emphasis in which serialization is achieved by toggling serializer with data transition information extracted from parallel input data. This novel technique of serialization provides significantly reduced power consumption since it does not need the short pulse generation block required in the conventional serializer. In addition, the same data transition information can be directly used for implementing 2-tap pre-emphasize and, consequently, the need for the additional serializer required in the conventional pre-emphasis circuits can be eliminated, resulting in further reduced power consumption. A prototype transmitter realized in 65nm CMOS technology achieves energy efficiencies of 0.202 pJ/bit at 5 Gb/s and 0.3 pJ/bit at 8 Gb/s for 150 mVpp,d output voltage swing without pre-emphasis, and 0.252 pJ/bit at 5 Gb/s and 0.333 pJ/bit at 8 Gb/s with 2-tap pre-emphasis providing 6-dB equalization gain. To the best of our knowledge, these are the lowest energy efficiencies achieved for wireline transmitters realized in 65nm CMOS technology.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130348167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844144
M. Jalalifar, Gyung-Su Byun
A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.
{"title":"A 14.4Gb/s/pin 230fJ/b/pin/mm multi-level RF-interconnect for global network-on-chip communication","authors":"M. Jalalifar, Gyung-Su Byun","doi":"10.1109/ASSCC.2016.7844144","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844144","url":null,"abstract":"A simultaneous and reconfigurable multi-level RF-interconnect (MRI) for global network-on-chip (NoC) communication is demonstrated. The proposed MRI interface consists of baseband (BB) and RF band transceivers. The BB transceiver uses multi-level signaling (MLS) to enhance communication bandwidth. The RF-band transceiver utilizes amplitude-shift keying (ASK) modulation to support simultaneous communication on a shared single-ended on-chip global interconnect. A phase-locked loop (PLL) is also designed to support the fully-synchronous NoC architecture. The MLS-based BB and ASK-based RF band carry 10Gb/s/pin and 4.4Gb/s/pin, respectively. The proposed system is fabricated in a 65nm CMOS process and achieves an energy/b/pin/mm of 230fJ/b/pin/mm.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122998468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844189
Yining Zhang, Ranran Zhou, W. Rhee, Zhihua Wang
This paper proposes a frequency-domain OOK (F-OOK) modulation method which utilizes power detection of both a carrier and a sideband by modulating the carrier frequency with a pre-selected modulation template. Unlike the conventional OOK modulation, the carrier waveform in the time domain can be always present regardless of data pattern, thus offering a packet-level duty cycle operation without affecting overall spectrum occupation. Compared to the BFSK modulation, more efficient bandwidth control can be achieved for the same data rate with a symmetric FM template. The F-OOK signal is generated by a PLL based modulator in which only high-pass modulation is performed, which is different from the conventional two-point modulation, thus significantly relaxing design complexity. A prototype transmitter implemented in 65nm CMOS consumes 1.9mW from a 0.8V supply with a data rate of 750kb/s, achieving an energy efficiency of 2.5nJ/bit.
{"title":"A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL","authors":"Yining Zhang, Ranran Zhou, W. Rhee, Zhihua Wang","doi":"10.1109/ASSCC.2016.7844189","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844189","url":null,"abstract":"This paper proposes a frequency-domain OOK (F-OOK) modulation method which utilizes power detection of both a carrier and a sideband by modulating the carrier frequency with a pre-selected modulation template. Unlike the conventional OOK modulation, the carrier waveform in the time domain can be always present regardless of data pattern, thus offering a packet-level duty cycle operation without affecting overall spectrum occupation. Compared to the BFSK modulation, more efficient bandwidth control can be achieved for the same data rate with a symmetric FM template. The F-OOK signal is generated by a PLL based modulator in which only high-pass modulation is performed, which is different from the conventional two-point modulation, thus significantly relaxing design complexity. A prototype transmitter implemented in 65nm CMOS consumes 1.9mW from a 0.8V supply with a data rate of 750kb/s, achieving an energy efficiency of 2.5nJ/bit.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126185310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-01DOI: 10.1109/ASSCC.2016.7844208
Bingwei Jiang, Chixiao Chen, Junyan Ren, H. Luong
This paper presents a noise-shifting coupling network to minimize the phase noise contribution from the coupling devices of quadrature voltage-controlled oscillators (QVCOs). Through capacitive feedback, the noisy currents of the coupling devices are shifted to be orthogonal to their impulse sensitivity function (ISF). Fabricated in 65nm CMOS technology, a 7.9-GHz QVCO prototype measures phase noise of −143dBc/Hz at 10-MHz frequency offset and a minimum IQ phase error of 0.23o. The QVCO consumes 27.2mW with a 0.8-V supply voltage, corresponding to figure-of-merit (FOM) of 186.6 dB.
{"title":"A 7.9-GHz transformer-feedback quadrature VCO with a noise-shifting coupling network","authors":"Bingwei Jiang, Chixiao Chen, Junyan Ren, H. Luong","doi":"10.1109/ASSCC.2016.7844208","DOIUrl":"https://doi.org/10.1109/ASSCC.2016.7844208","url":null,"abstract":"This paper presents a noise-shifting coupling network to minimize the phase noise contribution from the coupling devices of quadrature voltage-controlled oscillators (QVCOs). Through capacitive feedback, the noisy currents of the coupling devices are shifted to be orthogonal to their impulse sensitivity function (ISF). Fabricated in 65nm CMOS technology, a 7.9-GHz QVCO prototype measures phase noise of −143dBc/Hz at 10-MHz frequency offset and a minimum IQ phase error of 0.23o. The QVCO consumes 27.2mW with a 0.8-V supply voltage, corresponding to figure-of-merit (FOM) of 186.6 dB.","PeriodicalId":278002,"journal":{"name":"2016 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131326202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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