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2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)最新文献

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Timing analysis for wide IO memory interface applications with silicon interposer 基于硅中间层的宽IO存储器接口时序分析
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6898941
K. Chandrasekar, D. Oh, Arif Rahman
Memory bandwidth requirements for future high-end applications such as graphics, 200G/400G networking and high performance computing is driving the need for more “on-chip memory”. Silicon Interposer based 2.5D integration provides an intermediate path to achieving high memory bandwidth by integrating memory in package. This paper discusses timing budget analysis for realizing wide IO memory interfaces in silicon interposer technology. Traditional signal and power integrity (SI/PI) analysis for closing system timing in DDR interfaces cannot be applied directly to “chip-to-chip scenarios” as it tends to be time consuming because of need for extensive electromagnetic (EM) simulations. In addition, the assumptions on bus activity and IO bandwidth/density/speed are unique to 2.5D memory customer applications. Applying traditional assumptions from off-chip double data rate (DDR) memory interfaces to “in-package” memory interfaces can lead to additional cost overhead at chip/package and board level. The key contributions of this paper are in providing an accurate time efficient SPICE based modeling methodology to design and optimize 2.5D memory applications cost effectively to meet desired timing specifications. This paper notes simultaneous switching noise (SSN) to be a major impairment leading to eye closure in wide memory interfaces with worst case timing jitter numbers of the order of 130ps in FPGA applications. Achieving 500MHz to 1GHz DDR operating speeds primarily require a more rigorous application - based tuning of on-die decoupling capacitance, PDN inductive parasitics, interconnect length and IO drive strength. But the power, bandwidth and latency benefits of wide IO system-in-package (SIP) memory make the additional development effort worthwhile.
未来高端应用(如图形、200G/400G网络和高性能计算)对内存带宽的需求正在推动对更多“片上存储器”的需求。基于硅Interposer的2.5D集成提供了一种中间途径,通过在封装中集成存储器来实现高内存带宽。本文讨论了在硅中间层技术中实现宽IO存储接口的时序预算分析。传统的用于DDR接口中关闭系统时序的信号和功率完整性(SI/PI)分析不能直接应用于“片对片场景”,因为它往往需要大量的电磁(EM)模拟,因此往往很耗时。此外,对总线活动和IO带宽/密度/速度的假设是2.5D内存客户应用程序所独有的。将片外双数据速率(DDR)内存接口的传统假设应用到“封装内”内存接口可能会导致芯片/封装和板级的额外成本开销。本文的主要贡献在于提供了一种精确的时间效率高的基于SPICE的建模方法,以经济有效地设计和优化2.5D内存应用,以满足所需的时序规范。本文指出,在FPGA应用中,同步开关噪声(SSN)是导致宽内存接口闭眼的主要损害,最坏情况下时序抖动数为130ps。达到500 mhz 1 ghz DDR运营速度主要基于需要更严格的应用程序——调优on-die去耦电容,生产寄生电感,互连长度和IO驱动力量。但是,宽IO包内系统(SIP)内存的功率、带宽和延迟优势使得额外的开发工作是值得的。
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引用次数: 3
The impact of near-field scanning size on the accuracy of far-field estimation 近场扫描尺寸对远场估计精度的影响
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6899038
Xiao Ren, Pratik Maheshwari, Yaojiang Zhang, V. Khilkevich, J. Fan, Yan Zhou, Yadong Bai, Xuequan Yu
The impact of near-field scanning sizes on the accuracy of far-field estimations is studied using a U-shape trace above a large ground plane as an example. Simulation model is built in commercial software and the planar near fields above the trace are obtained. Fourier Transform of the planar near fields is used to calculate the far-field radiations. Different sizes of planar scanning area are chosen and their corresponding computed far field patterns and maximum values are compared with those obtained by the software. It demonstrates that too small scanning size may lead to large errors in far-field calculations. Relationship between scanning plane height and planar scanning size is derived for accurate far field estimation, which is guidance for the extraction of accurate IC radiated emission model by planar near-field scanning technique.
以大地平面上的u型迹线为例,研究了近场扫描尺寸对远场估计精度的影响。在商业软件中建立仿真模型,得到轨迹上方的平面近场。利用平面近场的傅里叶变换计算远场辐射。选择了不同尺寸的平面扫描区域,并与软件计算得到的远场图和最大值进行了比较。结果表明,过小的扫描尺寸可能导致远场计算误差较大。推导了扫描平面高度与平面扫描尺寸之间的关系,为平面近场扫描技术精确提取集成电路辐射发射模型提供了指导。
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引用次数: 11
Over-the-air performance testing of a real 4G LTE base station in a reverberation chamber 在混响室中对真实4G LTE基站进行无线性能测试
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6899096
M. Barazzetta, D. Micheli, F. Moglie, V. M. Primiani
Fourth generation (4G) cellular systems have been nowadays rolled out already in several countries in the world. With networks open to commercial use, one of the key issues is how the quality perceived by the user is influenced by multipath propagation, like it may happen in indoor locations or in any kind of places where electromagnetic waves are partially reflected by walls and other objects. In order to verify this, the signal of a real 4G base station connected to the real radio access network of Telecom Italia has been transmitted into a reverberation chamber where a client was running FTPs using a 4G capable USB dongle as a modem. This paper describe the tests that have been performed and focus on how changes in propagation conditions affected the performances perceived by the user.
第四代(4G)蜂窝系统目前已经在世界上几个国家推出。随着网络向商业用途开放,关键问题之一是用户感知到的质量如何受到多径传播的影响,就像它可能发生在室内位置或电磁波被墙壁和其他物体部分反射的任何类型的地方一样。为了验证这一点,将连接意大利电信真实无线接入网络的真实4G基站的信号传输到一个混响室,该混响室的客户端使用支持4G的USB加密狗作为调制解调器运行FTPs。本文描述了已经执行的测试,并重点关注传播条件的变化如何影响用户感知的性能。
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引用次数: 18
Interconnect impedance optimization for high speed IO up to 12Gbps under HVM condition HVM条件下高达12Gbps的高速IO互连阻抗优化
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6899048
Xinjun Zhang, C. Ye, M. Wei, Weifeng Shu, X. Ye
Differential impedance optimization is critical for high-speed IO design and has attracted lot of interests for decades. This paper focuses on impedance optimization on a general purpose server design for 10Gbps and above and use SAS3 (Serial Attached SCSI Gen3) as example under HVM (high volume manufacturing) condition. The study starts with theoretical analysis on a two-port network of three cascaded transmission lines to prove that there is an optimal characteristic impedance value of the middle section which can bring the lowest reflection and best transmission to the entire two-port network. In the SAS3 impedance optimization study, statistical distribution for each design variable is considered to address the HVM consideration. The result clearly shows that lower the impedance of baseboard and backplane yields better eye opening at the receiver for the given impedance design range from 85Ω to 100Ω. In other words, 85Ω design on baseboard and backplane is better in performance than 100Ω even if cables, connectors and SAS3 hard disk drives (HDDs) are designed at 100Ω per SAS3 specification.
差分阻抗优化是高速IO设计的关键,几十年来引起了人们的广泛关注。本文主要研究10Gbps及以上通用服务器设计的阻抗优化,并以大批量生产条件下的SAS3(串行连接SCSI Gen3)为例。本研究首先对三根级联传输线组成的双端口网络进行理论分析,证明存在一个最优的中间段特性阻抗值,使整个双端口网络反射最小,传输最佳。在SAS3阻抗优化研究中,考虑了每个设计变量的统计分布,以解决HVM的考虑。结果清楚地表明,对于给定的阻抗设计范围从85Ω到100Ω,基板和背板的阻抗越低,接收器的眼界就越大。换句话说,即使电缆、连接器和SAS3硬盘驱动器(hdd)按照SAS3规范100Ω设计,在基板和背板上的85Ω设计在性能上优于100Ω。
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引用次数: 1
De-embedding method to accurately measure high-frequency impedance of an O-shape spring contact 用去嵌入法精确测量o型弹簧触点高频阻抗
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6899041
Qiaolei Huang, Jing Li, Joe Zhou, Wilson Wu, Y. Qi, J. Fan
In this paper, a de-embedding method is proposed to measure the impedance of an innovative O-shape spring contact, for frequency up to 30 GHz. To allow the de-embedding method to be applied in practical situations, both conductor loss and the discontinuity associated with the junction are taken into account. Results obtained from the de-embedding method are validated using full wave simulation. In the simulation model, the O-shape spring contact is cut into two pieces based on the current flow paths, providing a straightforward way to understand why a resonance exists in the impedance profile of the connector. Lastly, the advantages and drawbacks of this method are discussed.
本文提出了一种去嵌入方法,用于测量频率高达30 GHz的新型o形弹簧触点的阻抗。为了使去埋方法应用于实际情况,同时考虑了导体损耗和与结有关的不连续。用全波模拟验证了去嵌入方法的结果。在仿真模型中,o型弹簧触点根据电流流动路径被切成两部分,提供了一种直接的方法来理解为什么在连接器的阻抗剖面中存在共振。最后,对该方法的优缺点进行了讨论。
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引用次数: 17
Design criteria of automatic fixture removal (AFR) for asymmetric fixture de-embedding 非对称夹具去嵌的自动夹具移除(AFR)设计准则
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6899051
C. Yoon, M. Tsiklauri, M. Zvonkin, J. Fan, J. Drewniak, A. Razmadze, Aman Aflaki, Jingook Kim, Q. Chen
Automatic fixture removal (AFR) for asymmetric fixture de-embedding is introduced. Two design criteria for fixture design in AFR, passivity and discontinuity, are proposed. Three different 2x-fixtures are investigated for the verification of proposed two design criteria.
介绍了非对称夹具去嵌的自动夹具移除(AFR)方法。提出了AFR中夹具设计的两种设计准则:无源性和不连续性。为了验证提出的两个设计准则,研究了三种不同的2x夹具。
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引用次数: 13
An efficient hybrid boundary-integral and finite-element method for signal integrity analysis of multiple vias sharing an anti-pad in an infinitely-large plate pair 无限大板对共用一个反盘的多通孔信号完整性分析的边界积分与有限元混合方法
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6898974
Yaojiang Zhang, Xinxin Tian, Liehui Ren, Dazhao Liu, J. Fan
A domain decomposition approach, namely hybrid boundary-integral and finite-element method, is proposed for signal integrity analysis of an infinitely-large plate pair with multi-vias in a shared anti-pad. Each via structure is modeled as a multi-mode network containing top/bottom transverse electromagnetic (TEM) ports associated with vias and parallel-plate ports a little far away from the anti-pad. Coupling among parallel-plate ports of all via structures is considered by a plate-pair impedance matrix. The connection of the multi-mode networks of via structures and the impedance matrix constructs a complete noise coupling path from one via structure to another one, and the S-parameter of the entire plate pair can be steadily obtained by simply manipulating S-parameter matrices. Numerical examples are used to verify the accuracy of the approach by comparing with a full-wave solver.
提出了一种混合边界积分和有限元法的区域分解方法,用于分析共享防垫中具有多通孔的无限大板对的信号完整性。每个通孔结构都被建模为一个多模式网络,其中包含与通孔和离反垫稍远的平行板端口相关联的上下横向电磁(TEM)端口。通过板对阻抗矩阵来考虑所有通孔结构中平行板端口之间的耦合。通孔结构的多模网络与阻抗矩阵的连接构成了从一个通孔结构到另一个通孔结构的完整的噪声耦合路径,通过简单地操纵s参数矩阵可以稳定地获得整个板对的s参数。通过与全波解算器的比较,验证了该方法的准确性。
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引用次数: 2
On intermittent OFDM transmitter saturation and radar system performance 断断续续OFDM发射机饱和与雷达系统性能研究
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6898936
B. Cordill, S. A. Seguin
The effects of spectral crowding are becoming acutely problematic as new wireless systems are being deployed in adjacent bands to legacy systems. Current spectrum management practices seek to control and limit persistent out-of-band emissions, but fall short on addressing intermittent emissions. Such intermittent interference can be caused by the occasional saturation of a transmitting power amplifier, resulting in unintended emissions into adjacent bands. Such transmitter saturations are common for the high peak-to-average power waveforms commonly found in OFDM systems. This work seeks to quantify the performance degradation of a notional radar system in the face of intermittent interference falling in the radar's operating bandwidth. The results show a rise in the false alarm rate of the radar system in proportion to the saturation rate of the adjacent band system.
随着新的无线系统被部署在与传统系统相邻的频段上,频谱拥挤的影响正变得非常严重。目前的频谱管理实践旨在控制和限制持续的带外发射,但在解决间歇性发射方面做得不够。这种间歇性干扰可能是由发射功率放大器的偶尔饱和引起的,导致无意的发射到邻近的波段。这样的发射机饱和对于OFDM系统中常见的峰值平均功率波形是常见的。这项工作旨在量化一个概念雷达系统在面对雷达工作带宽中的间歇性干扰时的性能退化。结果表明,雷达系统的虚警率与邻带系统的饱和率成正比。
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引用次数: 1
New spread spectrum clocking techniques: For improved compatibility with cellular and wireless subsystems 新的扩频时钟技术:用于改进与蜂窝和无线子系统的兼容性
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6898965
Dawson Kesling, H. Skinner
Spread spectrum clocking is an established technique for reducing electromagnetic interference arising from clocking signals. Though effective for reducing interference with other devices, SSC can increase the interference with radio receivers inside the device itself. New SSC techniques have been developed to reduce this internal interference while retaining the external interference benefits. Laboratory measurements and test chip results show significant reduction in radio interference. The techniques are applicable to switching voltage regulators and high-speed digital computing and communications systems.
扩频时钟是一种成熟的减少由时钟信号引起的电磁干扰的技术。虽然可以有效地减少对其他设备的干扰,但SSC会增加对设备内部无线电接收器的干扰。新的SSC技术已经开发出来,以减少这种内部干扰,同时保留外部干扰的好处。实验室测量和测试芯片结果显示无线电干扰显著减少。该技术适用于开关电压调节器和高速数字计算和通信系统。
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引用次数: 2
Statistical performance comparison between the FSV and the FS-NMI index FSV与FS-NMI指数的统计性能比较
Pub Date : 2014-11-20 DOI: 10.1109/ISEMC.2014.6898991
M. Azpúrua, E. Paez, X. Parra, Ferran Silva, R. Jaúregui
This paper presents a performance comparison between two validation methods developed specifically for the Computational Electromagnetics purposes: the Feature Selective Validation (FSV) and the Feature Selective Normalized Mutual Information (FSNMI) index. To achieve this goal, a statistical analysis of 40 different cases of study (pairs of data sets) is carried out covering a wide range of real-life applications, such as, frequency domain, noisy and transient data, among others. The results provided an insight of the relationships between each method, showing that more effort is required to achieve generally coherent validation results between the FSV and the FSNMI.
本文介绍了专门为计算电磁学目的开发的两种验证方法:特征选择验证(FSV)和特征选择归一化互信息(FSNMI)索引之间的性能比较。为了实现这一目标,对40个不同的研究案例(数据集对)进行了统计分析,涵盖了广泛的现实应用,如频域、噪声和瞬态数据等。结果揭示了每种方法之间的关系,表明需要更多的努力才能在FSV和FSNMI之间获得普遍一致的验证结果。
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引用次数: 1
期刊
2014 IEEE International Symposium on Electromagnetic Compatibility (EMC)
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