Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875953
Frank Amiot, E. Pissaloux
This paper proposes a concept of vision application-adaptable architecture called FreeTIV (Free architecture dedicated to image processing and vision) based on an adaptable message passing router called RouTIV (Router dedicated to image processing and vision). This router adapts interconnection of the available calculation resources in order to reduce the running application data movements implementation and execution costs. The adaptable router concept allows to obtain application dedicated fast and reliable parallel machine at low cost.
{"title":"FreeTIV parallel computer: architecture and environment","authors":"Frank Amiot, E. Pissaloux","doi":"10.1109/CAMP.2000.875953","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875953","url":null,"abstract":"This paper proposes a concept of vision application-adaptable architecture called FreeTIV (Free architecture dedicated to image processing and vision) based on an adaptable message passing router called RouTIV (Router dedicated to image processing and vision). This router adapts interconnection of the available calculation resources in order to reduce the running application data movements implementation and execution costs. The adaptable router concept allows to obtain application dedicated fast and reliable parallel machine at low cost.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116408677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875959
J. Kim, Tom Chen
We propose a segmentation scheme and its VLSI edge fusion architecture for image sequences which provides initial region information for the semantic object representation of image sequences. The proposed scheme incorporates static and dynamic features simultaneously in one scheme. The segmentation results of both gray level image sequences and color image sequences are evaluated using a evaluation metric. Also, based on complexity analysis of the segmentation scheme, the edge fusion is the bottleneck of fast image sequence segmentation. The proposed VLSI architecture makes it possible to the image sequence segmentation in real-time.
{"title":"A VLSI architecture for image sequence segmentation using edge fusion","authors":"J. Kim, Tom Chen","doi":"10.1109/CAMP.2000.875959","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875959","url":null,"abstract":"We propose a segmentation scheme and its VLSI edge fusion architecture for image sequences which provides initial region information for the semantic object representation of image sequences. The proposed scheme incorporates static and dynamic features simultaneously in one scheme. The segmentation results of both gray level image sequences and color image sequences are evaluated using a evaluation metric. Also, based on complexity analysis of the segmentation scheme, the edge fusion is the bottleneck of fast image sequence segmentation. The proposed VLSI architecture makes it possible to the image sequence segmentation in real-time.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875993
L. Cinque, S. Levialdi, L. Lombardi, S. Tanimoto
The analysis of scanned documents is important in the construction of digital libraries and paperless offices. One significant challenge is coping with artifacts of photocopying and scanning. We present a series of simple techniques for handling these difficulties. Using 125 images of the University of Washington scanned documents database, we demonstrate the effectiveness of these methods in preparing the images for segmentation by a multiresolution algorithm.
{"title":"Handling artifacts in digitally reproduced documents","authors":"L. Cinque, S. Levialdi, L. Lombardi, S. Tanimoto","doi":"10.1109/CAMP.2000.875993","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875993","url":null,"abstract":"The analysis of scanned documents is important in the construction of digital libraries and paperless offices. One significant challenge is coping with artifacts of photocopying and scanning. We present a series of simple techniques for handling these difficulties. Using 125 images of the University of Washington scanned documents database, we demonstrate the effectiveness of these methods in preparing the images for segmentation by a multiresolution algorithm.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131564769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875985
N. Zingirian, M. Maresca
This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of image and video processing programs running on instruction level parallel (ILP) processors. LR is specifically, devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today's low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique.
{"title":"Loop regularization for image and video processing on instruction level parallel architectures","authors":"N. Zingirian, M. Maresca","doi":"10.1109/CAMP.2000.875985","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875985","url":null,"abstract":"This paper presents a novel loop transformation (Loop Regularization, LR) that increases the execution efficiency of image and video processing programs running on instruction level parallel (ILP) processors. LR is specifically, devised for those ILP processors that do not include hardware mechanisms for instruction reordering and register renaming such as today's low cost processors for embedded systems and digital signal processors. This paper shows the effects of LR and reports on a set of system-level experiments that validate the technique.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132735358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875988
M. Herbordt, J. Cravy, Honghai Zhang, Calvin Lin, H. Rao
Although arrays of SIMD PEs can be built with very high operating frequencies, problems exist in keeping the array busy. The inherent mismatch between host and array makes it difficult to maintain high array utilization: either the rate of instruction issue is very low or PE data locality is compromised, having the same effect. Our solution is based on an array control unit (ACU) design that expands macro instructions in two stages, first by data tile and then into microinstructions. The expansion itself solves the issue problem; decoupling the expansion modalities maintains data locality. Several issues involving host/ACU interaction need to be resolved to effect this solution.
{"title":"An array control unit for high performance SIMD arrays","authors":"M. Herbordt, J. Cravy, Honghai Zhang, Calvin Lin, H. Rao","doi":"10.1109/CAMP.2000.875988","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875988","url":null,"abstract":"Although arrays of SIMD PEs can be built with very high operating frequencies, problems exist in keeping the array busy. The inherent mismatch between host and array makes it difficult to maintain high array utilization: either the rate of instruction issue is very low or PE data locality is compromised, having the same effect. Our solution is based on an array control unit (ACU) design that expands macro instructions in two stages, first by data tile and then into microinstructions. The expansion itself solves the issue problem; decoupling the expansion modalities maintains data locality. Several issues involving host/ACU interaction need to be resolved to effect this solution.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115353808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875952
A. Chihoub, Y. Bai, Visvanathan Ramesh
In this paper we describe the design and implementation of an efficient and compact image processing library for a digital still camera based on Siemens TriCore microcontroller-DSP processor. The library is designed for use in both off-line (e.g. NT based Pentium platforms) as well as on-line (TriCore implementation). To satisfy the constraints of embedded systems the library was designed to operate on an input image using the concept of band processing. In such a method, the input image is divided into an appropriate number of data bands (strips). The image bands are then processed separately using a pipeline of band based operators. The processed bands are then collected into a single output image. Most of the operators incorporated in the library take advantage of the band processing mechanism and operate on a stream of such image bands. This scheme not only alleviates the memory space requirements but also lends itself to multithreading and parallel processing implementations with potential for even faster performance. The library was optimized in terms of code size (31 kilobytes) and processing speed (1.98 sec. on an 1008/spl times/800 input image in the acquisition mode of operation) to meet the current requirements of a size less than 250 kilobytes and a processing speed of less than 2 seconds/image.
{"title":"An imaging library for a TriCore based digital camera","authors":"A. Chihoub, Y. Bai, Visvanathan Ramesh","doi":"10.1109/CAMP.2000.875952","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875952","url":null,"abstract":"In this paper we describe the design and implementation of an efficient and compact image processing library for a digital still camera based on Siemens TriCore microcontroller-DSP processor. The library is designed for use in both off-line (e.g. NT based Pentium platforms) as well as on-line (TriCore implementation). To satisfy the constraints of embedded systems the library was designed to operate on an input image using the concept of band processing. In such a method, the input image is divided into an appropriate number of data bands (strips). The image bands are then processed separately using a pipeline of band based operators. The processed bands are then collected into a single output image. Most of the operators incorporated in the library take advantage of the band processing mechanism and operate on a stream of such image bands. This scheme not only alleviates the memory space requirements but also lends itself to multithreading and parallel processing implementations with potential for even faster performance. The library was optimized in terms of code size (31 kilobytes) and processing speed (1.98 sec. on an 1008/spl times/800 input image in the acquisition mode of operation) to meet the current requirements of a size less than 250 kilobytes and a processing speed of less than 2 seconds/image.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875989
G. Conte, Stefano Tommesani, F. Zanichelli
Recently introduced "SIMD on registers" extensions to commodity microprocessors instruction sets promise (according to the makers) high potential speed-ups for multimedia processing tasks. This paper introduces the complex programming model of MMX/SSE extensions and discusses how the achievement of an effective performance increase over sequential code is no easy task also due to a poor software support. Experiences gained on two real-time image processing projects helped defining a programming methodology and evaluating the tradeoffs to obtain substantial speed-ups with MMX/SSE code.
{"title":"The long and winding road to high-performance image processing with MMX/SSE","authors":"G. Conte, Stefano Tommesani, F. Zanichelli","doi":"10.1109/CAMP.2000.875989","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875989","url":null,"abstract":"Recently introduced \"SIMD on registers\" extensions to commodity microprocessors instruction sets promise (according to the makers) high potential speed-ups for multimedia processing tasks. This paper introduces the complex programming model of MMX/SSE extensions and discusses how the achievement of an effective performance increase over sequential code is no easy task also due to a poor software support. Experiences gained on two real-time image processing projects helped defining a programming methodology and evaluating the tradeoffs to obtain substantial speed-ups with MMX/SSE code.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129735184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875974
G. Coldani, L. Cotrino, G. Danese, F. Leporati, M. Maneri
Automatic control applications are real time systems which pose stringent requirements on precisely time-triggered synchronised actions and constant end to end delays in feedback loops which often constitute multi-rate systems. The paper presents the Notacheck projects (single one or sheet inspections), a typical specimen of real-time control application requiring interaction between several technical disciplines. Mechanical control and computer engineering. An overview of the bank-note inspection problem is given. The state of technology for visual inspection and distributed architecture system is investigated.
{"title":"Notacheck: a parallel DSP-based architecture for real time high resolution inspection of bank-notes","authors":"G. Coldani, L. Cotrino, G. Danese, F. Leporati, M. Maneri","doi":"10.1109/CAMP.2000.875974","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875974","url":null,"abstract":"Automatic control applications are real time systems which pose stringent requirements on precisely time-triggered synchronised actions and constant end to end delays in feedback loops which often constitute multi-rate systems. The paper presents the Notacheck projects (single one or sheet inspections), a typical specimen of real-time control application requiring interaction between several technical disciplines. Mechanical control and computer engineering. An overview of the bank-note inspection problem is given. The state of technology for visual inspection and distributed architecture system is investigated.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116490537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875971
Wael Badawy, M. Bayoumi
This paper presents a scalable affine core (SAC) that can be used for video object motion-compensation. MPEG standardization committee recommends affine transformation for 2D mesh-based video object motion tracking, where the object is modeled as 2D mesh with triangular patches. The motion tracking is a texture warping for the deformed patches from frame-to-frame. A mesh-based video motion compensation architecture is presented. The motion compensation architecture uses the proposed SAC to track the deformation of a 2D mesh-based video object. A performance study is conducted and it shows that the proposed SAC can be used in online MPEG-4 mobile applications.
{"title":"A scalable affine core for video object motion compensation","authors":"Wael Badawy, M. Bayoumi","doi":"10.1109/CAMP.2000.875971","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875971","url":null,"abstract":"This paper presents a scalable affine core (SAC) that can be used for video object motion-compensation. MPEG standardization committee recommends affine transformation for 2D mesh-based video object motion tracking, where the object is modeled as 2D mesh with triangular patches. The motion tracking is a texture warping for the deformed patches from frame-to-frame. A mesh-based video motion compensation architecture is presented. The motion compensation architecture uses the proposed SAC to track the deformation of a 2D mesh-based video object. A performance study is conducted and it shows that the proposed SAC can be used in online MPEG-4 mobile applications.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122210963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875956
G. V. D. Wal, M. W. Hansen, M. Piacentino
Presented is a new 80 GOPS video-processing chip capable of performing video rate vision applications. These applications include real-time video stabilization, mosaicking, video fusion, motion-stereo and video enhancement. The new vision chip, code-named Acadia, is the result of over 15 years of research and development by Sarnoff in the areas of multi-resolution pyramid-based vision processing and efficient computational architectures. The Acadia chip represents the third generation of ASIC technology developed by Sarnoff, and incorporates the processing functions found in Sarnoff's earlier PYR-1 and PYR-2 pyramid processing chips as well as numerous other functions found in Sarnoff-developed video processing systems, including the PVT200. A demonstration board is being implemented and includes two video decoders, a video encoder and a PCI interface.
{"title":"The Acadia vision processor","authors":"G. V. D. Wal, M. W. Hansen, M. Piacentino","doi":"10.1109/CAMP.2000.875956","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875956","url":null,"abstract":"Presented is a new 80 GOPS video-processing chip capable of performing video rate vision applications. These applications include real-time video stabilization, mosaicking, video fusion, motion-stereo and video enhancement. The new vision chip, code-named Acadia, is the result of over 15 years of research and development by Sarnoff in the areas of multi-resolution pyramid-based vision processing and efficient computational architectures. The Acadia chip represents the third generation of ASIC technology developed by Sarnoff, and incorporates the processing functions found in Sarnoff's earlier PYR-1 and PYR-2 pyramid processing chips as well as numerous other functions found in Sarnoff-developed video processing systems, including the PVT200. A demonstration board is being implemented and includes two video decoders, a video encoder and a PCI interface.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115118555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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