Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875995
L. D. Stefano, S. Mattoccia
The ever-increasing speed of current general purpose processors, together with architectural enhancements such as multimedia-oriented instruction set extensions, allow for deploying standard PC-based systems in a number of com-putationally intensive computer vision tasks. This paper de-scribes the PC-based real-time stereo vision system devel-oped within the VIDET project, which is a research project aimed at the development of a mobility aid for the visu-ally impaired. VIDET's approach consists in the conversion of depth data gathered through a stereo vision system into a 3D model perceivable by the user by means of a wire-actuated haptic interface. The developed stereo matching algorithm makes massive use of recursion and multime-dia instructions to achieve the performance figures needed to sustain user's real-time interaction with the 3D model through the haptic interface.
{"title":"Fast stereo matching for the VIDET system using a general purpose processor with multimedia extensions","authors":"L. D. Stefano, S. Mattoccia","doi":"10.1109/CAMP.2000.875995","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875995","url":null,"abstract":"The ever-increasing speed of current general purpose processors, together with architectural enhancements such as multimedia-oriented instruction set extensions, allow for deploying standard PC-based systems in a number of com-putationally intensive computer vision tasks. This paper de-scribes the PC-based real-time stereo vision system devel-oped within the VIDET project, which is a research project aimed at the development of a mobility aid for the visu-ally impaired. VIDET's approach consists in the conversion of depth data gathered through a stereo vision system into a 3D model perceivable by the user by means of a wire-actuated haptic interface. The developed stereo matching algorithm makes massive use of recursion and multime-dia instructions to achieve the performance figures needed to sustain user's real-time interaction with the 3D model through the haptic interface.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116970755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875994
B. Wilson, M. Bayoumi
Traditional decompress-process methods for texture feature extraction consume valuable time and memory resources. This paper proposes a method for calculating wavelet energy texture features directly from a wavelet-compressed symbol stream. The proposed method requires little decompression and results in a technique that is efficient and requires less memory than traditional approaches. This reduction is accomplished through the elimination of both multiplication operations and the storage of zero-valued coefficients, which have no effect on these features. The developed algorithm has been implemented at various compression ratios, and in each case, the classification results are nearly identical to those obtained with the traditional method.
{"title":"Compressed-domain classification of texture images","authors":"B. Wilson, M. Bayoumi","doi":"10.1109/CAMP.2000.875994","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875994","url":null,"abstract":"Traditional decompress-process methods for texture feature extraction consume valuable time and memory resources. This paper proposes a method for calculating wavelet energy texture features directly from a wavelet-compressed symbol stream. The proposed method requires little decompression and results in a technique that is efficient and requires less memory than traditional approaches. This reduction is accomplished through the elimination of both multiplication operations and the storage of zero-valued coefficients, which have no effect on these features. The developed algorithm has been implemented at various compression ratios, and in each case, the classification results are nearly identical to those obtained with the traditional method.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131932313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875968
S. Bouaziz, M. Fan, R. Reynaud, T. Maurin
The "PICAR" project is based on "Prometheus Prochip" experience and results. The goal is to design an embedded multi sensors collision avoidance system for automotive application. The system includes sensors like video camera, ultrasonic sensors, a PC hardware computer, a CAN/sup 2/ network and a dedicated software for signal and image processing, data fusion and AI expert system. The design of such a system is difficult under real time constraints. Therefore, a simulator is a good solution to test different parts of the system and then to help to choose the overall architecture. However simulating all the embedded architecture in real-time becomes a very complex work. It is necessary to have an environment simulator where sensors can be virtually implemented. The data are then processed leading to results without hardware costs. The designed environment software allows the simulation of physical sensors, and also the emulation of these sensors. The simulator is interfaced to the physical embedded hardware by a network bridge. So, we can emulate some sensors to experiment data processing on the physical embedded PICAR computer. This paper presents the physical smart car PICAR and its embedded system, the virtual world simulator. We explain how we can mix the virtual world (produced by virtual sensors) and real world (physical embedded system) to implement some scenarios (like automatic parking) and to validate the physical architecture. An alternate goal can be to design customized sensors.
{"title":"Multi-sensors and environment simulator for collision avoidance applications","authors":"S. Bouaziz, M. Fan, R. Reynaud, T. Maurin","doi":"10.1109/CAMP.2000.875968","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875968","url":null,"abstract":"The \"PICAR\" project is based on \"Prometheus Prochip\" experience and results. The goal is to design an embedded multi sensors collision avoidance system for automotive application. The system includes sensors like video camera, ultrasonic sensors, a PC hardware computer, a CAN/sup 2/ network and a dedicated software for signal and image processing, data fusion and AI expert system. The design of such a system is difficult under real time constraints. Therefore, a simulator is a good solution to test different parts of the system and then to help to choose the overall architecture. However simulating all the embedded architecture in real-time becomes a very complex work. It is necessary to have an environment simulator where sensors can be virtually implemented. The data are then processed leading to results without hardware costs. The designed environment software allows the simulation of physical sensors, and also the emulation of these sensors. The simulator is interfaced to the physical embedded hardware by a network bridge. So, we can emulate some sensors to experiment data processing on the physical embedded PICAR computer. This paper presents the physical smart car PICAR and its embedded system, the virtual world simulator. We explain how we can mix the virtual world (produced by virtual sensors) and real world (physical embedded system) to implement some scenarios (like automatic parking) and to validate the physical architecture. An alternate goal can be to design customized sensors.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130477174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875990
R. Cucchiara, M. Piccardi, A. Prati
The workload of multimedia applications has a strong impact on cache memory performance, since the locality of memory references embedded in multimedia programs differs from that of traditional programs. In many cases, standard cache memory organization achieves poorer performance when used for multimedia. A widely explored approach to improve cache performance is hardware prefetching that allows the pre-loading of data in the cache before they are referenced. However, existing hardware prefetching approaches partially miss the potential performance improvement, since they are not tailored to multimedia locality. In this paper we propose novel effective approaches to hardware prefetching to be used in image processing programs for multimedia. Experimental results are reported for a suite of multimedia image processing programs including convolutions with kernels, MPEG-2 decoding, and edge chain coding.
{"title":"Hardware prefetching techniques for cache memories in multimedia applications","authors":"R. Cucchiara, M. Piccardi, A. Prati","doi":"10.1109/CAMP.2000.875990","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875990","url":null,"abstract":"The workload of multimedia applications has a strong impact on cache memory performance, since the locality of memory references embedded in multimedia programs differs from that of traditional programs. In many cases, standard cache memory organization achieves poorer performance when used for multimedia. A widely explored approach to improve cache performance is hardware prefetching that allows the pre-loading of data in the cache before they are referenced. However, existing hardware prefetching approaches partially miss the potential performance improvement, since they are not tailored to multimedia locality. In this paper we propose novel effective approaches to hardware prefetching to be used in image processing programs for multimedia. Experimental results are reported for a suite of multimedia image processing programs including convolutions with kernels, MPEG-2 decoding, and edge chain coding.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129803418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875966
S. Sabatini, P. Cavalleri, F. Solari, G. Bisio
A computational architecture for direct estimation of heading direction from optic flow is proposed. By representing optic flow information as undulatory spatiotemporal patterns, global first-order differential analysis of the optic flow is reconducted to spatiotemporal filtering operations with local kernels characterized with respect to the fixation point(gaze). These operations can be mapped with high efficiency on analog architectures based on structured arrays of cells reacting collectively to spatiotemporal input stimuli. By observing the overall distribution of cells' activity, it is possible to gain information on the orientation of the heading in the retinal reference frame and on the angle between the heading and the gaze directions.
{"title":"Recovering 3-D egomotion parameters from optic flow: from structural principles to analog architectures","authors":"S. Sabatini, P. Cavalleri, F. Solari, G. Bisio","doi":"10.1109/CAMP.2000.875966","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875966","url":null,"abstract":"A computational architecture for direct estimation of heading direction from optic flow is proposed. By representing optic flow information as undulatory spatiotemporal patterns, global first-order differential analysis of the optic flow is reconducted to spatiotemporal filtering operations with local kernels characterized with respect to the fixation point(gaze). These operations can be mapped with high efficiency on analog architectures based on structured arrays of cells reacting collectively to spatiotemporal input stimuli. By observing the overall distribution of cells' activity, it is possible to gain information on the orientation of the heading in the retinal reference frame and on the angle between the heading and the gaze directions.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133164969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875965
C. Torres-Huitzil, M. Arias-Estrada
This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.
{"title":"An FPGA architecture for high speed edge and corner detection","authors":"C. Torres-Huitzil, M. Arias-Estrada","doi":"10.1109/CAMP.2000.875965","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875965","url":null,"abstract":"This paper presents an FPGA based architecture for high speed edge and corner detection. Applications targeted are in high speed computer vision (i.e. more than 100 images per second). The architecture design was centred on the minimization on the number of accesses to the image memory. The design is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture design, FPGA resources utilization, results, and real time performance are discussed.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121933380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875978
J. L. Bosque, O. D. Robles, Angel Rodríguez, L. Pastor
This paper presents a parallel implementation of a content based information retrieval (CBIR) system which deals with an image database composed of data from over 29 million bidimensional RGB images, which would be equivalent to 1.45 TB of graphical data. The application has been designed for a distributed memory multiprocessor environment, and has been implemented in a cluster of twenty five PCs using MPI. The paradigm that best fits the problem's needs is a farm based solution: a master process distributes the work load between the slave processes, and when these have finished, the master recollects the partial results computed on each slave process. In order to evaluate this solution, the experimental results have been compared with those achieved using a Silicon Graphics Origin 2000, a shared memory machine with eight processors. This paper analyzes the performances offered by both approaches from the viewpoints of speed, price and scalability, presenting the conclusions that can be extracted from the results' comparison.
{"title":"Study of a parallel CBIR implementation using MPI","authors":"J. L. Bosque, O. D. Robles, Angel Rodríguez, L. Pastor","doi":"10.1109/CAMP.2000.875978","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875978","url":null,"abstract":"This paper presents a parallel implementation of a content based information retrieval (CBIR) system which deals with an image database composed of data from over 29 million bidimensional RGB images, which would be equivalent to 1.45 TB of graphical data. The application has been designed for a distributed memory multiprocessor environment, and has been implemented in a cluster of twenty five PCs using MPI. The paradigm that best fits the problem's needs is a farm based solution: a master process distributes the work load between the slave processes, and when these have finished, the master recollects the partial results computed on each slave process. In order to evaluate this solution, the experimental results have been compared with those achieved using a Silicon Graphics Origin 2000, a shared memory machine with eight processors. This paper analyzes the performances offered by both approaches from the viewpoints of speed, price and scalability, presenting the conclusions that can be extracted from the results' comparison.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117052084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875962
Bimal Gisutham, T. Srikanthan, V. Asari
Implementing Neural Networks in hardware has been a major problem due to the complexity involved in generating non-linear functions. The high hardware costs incurred in real time applications can be substantially reduced by adopting a suitable reuse methodology of the neurons. In addition, neurons with high speed of operation are necessitated to realise hardware efficient real time pattern recognition for images with higher resolution. In this regard, the response time and area of a neuron becomes critical in realising VLSI efficient neural networks. In this paper, the digital architecture of a multiple valued logic neuron has been proposed to realise a neural network implementation for real-time pattern recognition purposes. The proposed neuron uses a multilevel sigmoidal function as the activation function. Flat CORDIC, a new variation of the CORDIC algorithm, has been employed to generate the complex multi-level activation function in a VLSI efficient manner. The proposed neuron operates with a 200 MHz clock and has significant hardware and latency savings when compared to conventional CORDIC based neurons.
{"title":"A high speed flat CORDIC based neuron with multi-level activation function for robust pattern recognition","authors":"Bimal Gisutham, T. Srikanthan, V. Asari","doi":"10.1109/CAMP.2000.875962","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875962","url":null,"abstract":"Implementing Neural Networks in hardware has been a major problem due to the complexity involved in generating non-linear functions. The high hardware costs incurred in real time applications can be substantially reduced by adopting a suitable reuse methodology of the neurons. In addition, neurons with high speed of operation are necessitated to realise hardware efficient real time pattern recognition for images with higher resolution. In this regard, the response time and area of a neuron becomes critical in realising VLSI efficient neural networks. In this paper, the digital architecture of a multiple valued logic neuron has been proposed to realise a neural network implementation for real-time pattern recognition purposes. The proposed neuron uses a multilevel sigmoidal function as the activation function. Flat CORDIC, a new variation of the CORDIC algorithm, has been employed to generate the complex multi-level activation function in a VLSI efficient manner. The proposed neuron operates with a 200 MHz clock and has significant hardware and latency savings when compared to conventional CORDIC based neurons.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115702180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875986
E. Senn, B. Zavidovique
This paper describes how asynchronous techniques make easier timing in an image processing computer. It outlines an original machine architecture, and explains why it is asynchronous: the router circuit supports the asynchronism by itself. Its structure and behavior are sketched. Our method for self-timed design, its salient features and contributions to the typical asynchronous circuit design flow are introduced. The VLSI implementation and the cell set design, including full-custom self-timed asynchronous cells, are detailed. Measured circuit's performances are presented, as well as global processing and communication performances for different image processing algorithms. The gain from asynchronism is exhibited.
{"title":"Examples of image processing to benefit from an asynchronous implementation","authors":"E. Senn, B. Zavidovique","doi":"10.1109/CAMP.2000.875986","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875986","url":null,"abstract":"This paper describes how asynchronous techniques make easier timing in an image processing computer. It outlines an original machine architecture, and explains why it is asynchronous: the router circuit supports the asynchronism by itself. Its structure and behavior are sketched. Our method for self-timed design, its salient features and contributions to the typical asynchronous circuit design flow are introduced. The VLSI implementation and the cell set design, including full-custom self-timed asynchronous cells, are detailed. Measured circuit's performances are presented, as well as global processing and communication performances for different image processing algorithms. The gain from asynchronism is exhibited.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125272409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2000-09-11DOI: 10.1109/CAMP.2000.875963
D. Dulac, Gilles Bertrand, S. Guezguez
This paper presents an implementation of a topological segmentation on a SIMD massively parallel computer based on reconfigurability and asynchronism: Associative Mesh. This architecture provides powerful computational primitives that can apply an associative operator over the connex sets of a graph. So, basic primitives combine communications and computations. These primitives can be easily and efficiently realised in hardware by means of asynchronous operations and are adapted to a large number of image analysis primitives. We try to show the adequacy of Associative Mesh computing model with the different data movements that are generated by the several approaches of the image analysis. We are interested here with a new approach: image topology. We indicate how to get an homotopic kernel and a leveling kernel with parallel algorithms. Such kernels may be seen as "ultimate" topological simplifications of an image. This kind of image is similar to a very good split because it is based on topological information of image. We show one example of merge: we implement a method segmenting without the need of defining and tuning parameters.
{"title":"Parallel segmentation based on topology with the associative net model","authors":"D. Dulac, Gilles Bertrand, S. Guezguez","doi":"10.1109/CAMP.2000.875963","DOIUrl":"https://doi.org/10.1109/CAMP.2000.875963","url":null,"abstract":"This paper presents an implementation of a topological segmentation on a SIMD massively parallel computer based on reconfigurability and asynchronism: Associative Mesh. This architecture provides powerful computational primitives that can apply an associative operator over the connex sets of a graph. So, basic primitives combine communications and computations. These primitives can be easily and efficiently realised in hardware by means of asynchronous operations and are adapted to a large number of image analysis primitives. We try to show the adequacy of Associative Mesh computing model with the different data movements that are generated by the several approaches of the image analysis. We are interested here with a new approach: image topology. We indicate how to get an homotopic kernel and a leveling kernel with parallel algorithms. Such kernels may be seen as \"ultimate\" topological simplifications of an image. This kind of image is similar to a very good split because it is based on topological information of image. We show one example of merge: we implement a method segmenting without the need of defining and tuning parameters.","PeriodicalId":282003,"journal":{"name":"Proceedings Fifth IEEE International Workshop on Computer Architectures for Machine Perception","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114691387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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