The performance of a method for robustly writing conductive states into resistive switches is analyzed. The focus is set on the variability of the conductance distribution which has a strong impact on the signal margin and the robustness of the circuit performance. In order to be able to capture cycle-to-cycle as well as device-to-device variability an existing device model for ECM cells was extended and prepared to be executable on standard circuit simulation platforms. The ECM devices were embedded into a passive crossbar whereby electrical worst case conditions were identified by Monte Carlo simulations. Under the constraint of specified signal margins to be maintained for the read operation the underlying write circuit was optimized.
{"title":"A Monte Carlo analysis of a write method used in passive nanoelectronic crossbars","authors":"A. Heittmann, T. Noll","doi":"10.1145/2765491.2765509","DOIUrl":"https://doi.org/10.1145/2765491.2765509","url":null,"abstract":"The performance of a method for robustly writing conductive states into resistive switches is analyzed. The focus is set on the variability of the conductance distribution which has a strong impact on the signal margin and the robustness of the circuit performance. In order to be able to capture cycle-to-cycle as well as device-to-device variability an existing device model for ECM cells was extended and prepared to be executable on standard circuit simulation platforms. The ECM devices were embedded into a passive crossbar whereby electrical worst case conditions were identified by Monte Carlo simulations. Under the constraint of specified signal margins to be maintained for the read operation the underlying write circuit was optimized.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114954773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Khasanvis, K. Habib, Mostafizur Rahman, P. Narayanan, R. Lake, C. A. Moritz
Graphene is an emerging nano-material that has garnered immense research interest due to its exotic electrical properties. It is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper, we present an approach to realize multistate memories, enabled by these graphene crossbar devices. We propose a ternary graphene nanoribbon tunneling volatile random access memory (GNTRAM) and implement it using a heterogeneous integration with CMOS transistors and routing. Benchmarking is presented with respect to state-of-the-art CMOS SRAM and 3T DRAM designs. Ternary GNTRAM shows up to 1.77x density-per-bit benefit over CMOS SRAMs and 1.42x benefit over 3T DRAM in 16nm technology node. Ternary GNTRAM is also up to 9x more power-efficient per bit against low-power CMOS SRAMs during stand-by, while maintaining comparable performance to high-performance designs. Thus GNTRAM has the potential to realize ultra-dense nanoscale memories exceeding those achievable by mere physical scaling. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future.
{"title":"Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric","authors":"S. Khasanvis, K. Habib, Mostafizur Rahman, P. Narayanan, R. Lake, C. A. Moritz","doi":"10.1145/2765491.2765505","DOIUrl":"https://doi.org/10.1145/2765491.2765505","url":null,"abstract":"Graphene is an emerging nano-material that has garnered immense research interest due to its exotic electrical properties. It is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper, we present an approach to realize multistate memories, enabled by these graphene crossbar devices. We propose a ternary graphene nanoribbon tunneling volatile random access memory (GNTRAM) and implement it using a heterogeneous integration with CMOS transistors and routing. Benchmarking is presented with respect to state-of-the-art CMOS SRAM and 3T DRAM designs. Ternary GNTRAM shows up to 1.77x density-per-bit benefit over CMOS SRAMs and 1.42x benefit over 3T DRAM in 16nm technology node. Ternary GNTRAM is also up to 9x more power-efficient per bit against low-power CMOS SRAMs during stand-by, while maintaining comparable performance to high-performance designs. Thus GNTRAM has the potential to realize ultra-dense nanoscale memories exceeding those achievable by mere physical scaling. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. G. Alzate, P. Upadhyaya, Mark Lewis, J. Nath, Yen-Ting Lin, Kin L. Wong, S. Cherepov, P. Amiri, K. Wang, J. L. Hockel, A. Bur, G. Carman, S. Bender, Y. Tserkovnyak, Jian Zhu, Y. Chen, I. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, S. Khasanvis, S. Narayanan, C. A. Moritz, A. Khitun
We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing. This provides a fundamental advantage over the conventional transistor-based logic circuitry allowing for functional throughput enhancement and power consumption minimization at the same time. We present recent accomplishments in the magneto-electric element development and integration with spin wave buses. In particular, we show the excitation and detection of the spin waves via multiferroic elements. In addition, we present different approaches to magnonic logic circuit engineering and provide the comparison with CMOS by mapping the designs to 45nm NANGATE standard cell libraries. The estimates show more than 40X power reduction and 53X area reduction for magnonic circuits. These results illustrate the potential advantages over conventional charge based electronics that could be a route to beyond CMOS logic circuitry.
{"title":"Spin wave nanofabric update","authors":"J. G. Alzate, P. Upadhyaya, Mark Lewis, J. Nath, Yen-Ting Lin, Kin L. Wong, S. Cherepov, P. Amiri, K. Wang, J. L. Hockel, A. Bur, G. Carman, S. Bender, Y. Tserkovnyak, Jian Zhu, Y. Chen, I. Krivorotov, J. Katine, J. Langer, Prasad Shabadi, S. Khasanvis, S. Narayanan, C. A. Moritz, A. Khitun","doi":"10.1145/2765491.2765526","DOIUrl":"https://doi.org/10.1145/2765491.2765526","url":null,"abstract":"We provide a progress update on the spin wave nanofabric. The nanofabric comprises magneto-electric cells and spin wave buses serving for spin wave propagation. The magneto-electric cells are used as the input/output ports for information transfer between the charge and the spin domains, while information processing inside the nanofabric is via spin waves only. Information is encoded into the phase of the propagating spin wave, which makes it possible to utilize waveguides as passive logic elements and take the advantage of using wave superposition for data processing. This provides a fundamental advantage over the conventional transistor-based logic circuitry allowing for functional throughput enhancement and power consumption minimization at the same time. We present recent accomplishments in the magneto-electric element development and integration with spin wave buses. In particular, we show the excitation and detection of the spin waves via multiferroic elements. In addition, we present different approaches to magnonic logic circuit engineering and provide the comparison with CMOS by mapping the designs to 45nm NANGATE standard cell libraries. The estimates show more than 40X power reduction and 53X area reduction for magnonic circuits. These results illustrate the potential advantages over conventional charge based electronics that could be a route to beyond CMOS logic circuitry.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132627706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Topological quantum computing has recently proven itself to be a very powerful model when considering large-scale, fully error corrected quantum architectures. In addition to its robust nature under hardware errors, it is a software driven method of error corrected computation, with the hardware responsible for only creating a generic quantum resource (the topological lattice). Computation in this scheme is achieved by the geometric manipulation of holes (defects) within the lattice. Interactions between logical qubits (quantum gate operations) are implemented by using particular arrangements of the defects, such as braids and junctions.We demonstrate that junction-based topological quantum gates allow highly regular and structured implementation of large CNOT (controlled-not) gate networks, which ultimately form the basis of the error corrected primitives that must be used for an error corrected algorithm. We present a number of heuristics to optimise the area of the resulting structures and therefore the number of the required hardware resources.
{"title":"Synthesis of topological quantum circuits","authors":"A. Paler, S. Devitt, K. Nemoto, I. Polian","doi":"10.1145/2765491.2765524","DOIUrl":"https://doi.org/10.1145/2765491.2765524","url":null,"abstract":"Topological quantum computing has recently proven itself to be a very powerful model when considering large-scale, fully error corrected quantum architectures. In addition to its robust nature under hardware errors, it is a software driven method of error corrected computation, with the hardware responsible for only creating a generic quantum resource (the topological lattice). Computation in this scheme is achieved by the geometric manipulation of holes (defects) within the lattice. Interactions between logical qubits (quantum gate operations) are implemented by using particular arrangements of the defects, such as braids and junctions.We demonstrate that junction-based topological quantum gates allow highly regular and structured implementation of large CNOT (controlled-not) gate networks, which ultimately form the basis of the error corrected primitives that must be used for an error corrected algorithm. We present a number of heuristics to optimise the area of the resulting structures and therefore the number of the required hardware resources.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, D. Querlioz, Djaafar Chabi, D. Ravelosona, C. Chappert, J. Portal, M. Bocquet, H. Aziza, D. Deleruyelle, C. Muller
Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.
{"title":"Crossbar architecture based on 2R complementary resistive switching memory cell","authors":"Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, D. Querlioz, Djaafar Chabi, D. Ravelosona, C. Chappert, J. Portal, M. Bocquet, H. Aziza, D. Deleruyelle, C. Muller","doi":"10.1145/2765491.2765508","DOIUrl":"https://doi.org/10.1145/2765491.2765508","url":null,"abstract":"Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense R&D investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >1012) beyond Flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper describes a design of crossbar architecture based on 2R complementary resistive switching memory cell. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture. We performed transient simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 65 nm design kit and memory compact models.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131492380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in integrated circuits (ICs) design for advanced process technology nodes. This paper proposes a Markovian framework to asses and predict the IC lifetime by taking into account the joint effects of process, environmental, and temporal variations. By allowing the performance boundary to vary in time such that both remnant and non remnant variations are encompassed, and imposing a Markovian evolution, we propose a model that can be better fitted to various real conditions, thus enabling at design-time appropriate guardbands selection and effective aging mitigation/compensation techniques. The proposed framework has been validated for different stress conditions, under process variations and aging effects. Experimental results indicate an approximation error with mean value smaller than 10% and a standard deviation smaller than 15% for the considered circuit predicted end-of-life (EOL).
{"title":"A Markovian, variation-aware circuit-level aging model","authors":"N. C. Laurenciu, S. Cotofana","doi":"10.1145/2765491.2765513","DOIUrl":"https://doi.org/10.1145/2765491.2765513","url":null,"abstract":"Accurate age modeling, and fast, yet robust reliability sign-off emerged as mandatory constraints in integrated circuits (ICs) design for advanced process technology nodes. This paper proposes a Markovian framework to asses and predict the IC lifetime by taking into account the joint effects of process, environmental, and temporal variations. By allowing the performance boundary to vary in time such that both remnant and non remnant variations are encompassed, and imposing a Markovian evolution, we propose a model that can be better fitted to various real conditions, thus enabling at design-time appropriate guardbands selection and effective aging mitigation/compensation techniques. The proposed framework has been validated for different stress conditions, under process variations and aging effects. Experimental results indicate an approximation error with mean value smaller than 10% and a standard deviation smaller than 15% for the considered circuit predicted end-of-life (EOL).","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fluctuations have recently been recognized as powerful resources that can be exploited to drive computations, but their use has mostly been limited to logic circuits. This paper goes further and explores a more general framework, in which computation is modeled as a process with a multitude of fluctuating tokens that interact with each other directly or via stigmergy. For the implementation of these concepts Single Electron Tunneling (SET) technology is a strong candidate, since it combines a key element of fluctuation-driven systems, i.e., fluctuating tokens, with the potential for manufacturing in traditional materials (silicon) as well as alternatives, such as molecules. We propose computational elements, i.e., Memory Enhanced Hubs (MEHs), that contain functionality to pass fluctuating signals through them, as well as stigmergic functionality to store a state temporarily and reset it. We introduce a SET based design of such a memory enhance hub instance and demonstrate by means of simulations that it function correctly and that MEHs networks operating according to the stigmergic paradigm can be constructed.
{"title":"Stigmergic search with Single Electron Tunneling technology based Memory Enhanced Hubs","authors":"S. Safiruddin, S. Cotofana, F. Peper","doi":"10.1145/2765491.2765523","DOIUrl":"https://doi.org/10.1145/2765491.2765523","url":null,"abstract":"Fluctuations have recently been recognized as powerful resources that can be exploited to drive computations, but their use has mostly been limited to logic circuits. This paper goes further and explores a more general framework, in which computation is modeled as a process with a multitude of fluctuating tokens that interact with each other directly or via stigmergy. For the implementation of these concepts Single Electron Tunneling (SET) technology is a strong candidate, since it combines a key element of fluctuation-driven systems, i.e., fluctuating tokens, with the potential for manufacturing in traditional materials (silicon) as well as alternatives, such as molecules. We propose computational elements, i.e., Memory Enhanced Hubs (MEHs), that contain functionality to pass fluctuating signals through them, as well as stigmergic functionality to store a state temporarily and reset it. We introduce a SET based design of such a memory enhance hub instance and demonstrate by means of simulations that it function correctly and that MEHs networks operating according to the stigmergic paradigm can be constructed.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117193285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents 2-input cells designed to perform reconfigurable operations in nanometric systems exploiting the ambipolar property of double-gate (DG) carbon nanotube (CNT) FETs. Previous work [12] described a dynamic logic cell generating only 14 functions instead of 16 normally performed by the multiplexer-based logic part of a CLB (Configurable Logic Block) of an FPGA for 2-inputs. In this work, a reconfigurable 2-input dynamic logic cell designed using DG-CNTFET devices is able to achieve a more complete set of functions by exploiting sum of products (SOP) and product of sums (POS) to express logic functions. We also demonstrated that a static logic version can be derived from this dynamic cell. Simulations reveal improvement factor of 3X in terms of delay and 23% of decrease in power consumption compared with the previous work [12]. When compared with 16nm-CMOS Technology, DG-CNTFET cells (dynamic logic and static logic style) showed a comparable PDP with a slight increase in area.
{"title":"Ambipolar double gate CNTFETs based reconfigurable Logic cells","authors":"K. Jabeur, I. O’Connor, S. L. Beux, D. Navarro","doi":"10.1145/2765491.2765494","DOIUrl":"https://doi.org/10.1145/2765491.2765494","url":null,"abstract":"This paper presents 2-input cells designed to perform reconfigurable operations in nanometric systems exploiting the ambipolar property of double-gate (DG) carbon nanotube (CNT) FETs. Previous work [12] described a dynamic logic cell generating only 14 functions instead of 16 normally performed by the multiplexer-based logic part of a CLB (Configurable Logic Block) of an FPGA for 2-inputs. In this work, a reconfigurable 2-input dynamic logic cell designed using DG-CNTFET devices is able to achieve a more complete set of functions by exploiting sum of products (SOP) and product of sums (POS) to express logic functions. We also demonstrated that a static logic version can be derived from this dynamic cell. Simulations reveal improvement factor of 3X in terms of delay and 23% of decrease in power consumption compared with the previous work [12]. When compared with 16nm-CMOS Technology, DG-CNTFET cells (dynamic logic and static logic style) showed a comparable PDP with a slight increase in area.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As feature-size scaling and “Moore's Law” in integrated CMOS circuits further slows down, attention is shifting to computing by non-von Neumann and non-Boolean computing models. Reservoir computing (RC) is a new computing paradigm that allows to harness the intrinsic dynamics of a “reservoir” to perform useful computations. The reservoir, or compute core, must only provide sufficiently rich dynamics that are then mapped onto a low-dimensional space by an readout layer. One of the key advantages of this approach is that only the readout layer needs to be adapted to perform the desired computation. The reservoir itself remains unchanged. In this paper we use for the first time memristive components as reservoir building blocks that are assembled into device networks. Memristive components are particularly interesting for this purpose because of their non-linear and memory characteristics. In addition, they can be integrated very densely and provide rich dynamics with a few components only. We use pattern recognition and associative memory tasks to illustrate the memristive reservoir computing approach. For that purpose, we have built a software framework that allows to create valid memristor networks, to simulate and evaluate them in Ngspice, and to train the readout layer by means of a Genetic Algorithm (GA). Our results show that we can efficiently and robustly classify temporal patterns. The approach presents a promising new computing paradigm that harnesses the non-linear, time-dependent, and highly-variable properties of current memristive components for solving computational tasks.
{"title":"Memristor-based reservoir computing","authors":"M. S. Kulkarni, C. Teuscher","doi":"10.1145/2765491.2765531","DOIUrl":"https://doi.org/10.1145/2765491.2765531","url":null,"abstract":"As feature-size scaling and “Moore's Law” in integrated CMOS circuits further slows down, attention is shifting to computing by non-von Neumann and non-Boolean computing models. Reservoir computing (RC) is a new computing paradigm that allows to harness the intrinsic dynamics of a “reservoir” to perform useful computations. The reservoir, or compute core, must only provide sufficiently rich dynamics that are then mapped onto a low-dimensional space by an readout layer. One of the key advantages of this approach is that only the readout layer needs to be adapted to perform the desired computation. The reservoir itself remains unchanged. In this paper we use for the first time memristive components as reservoir building blocks that are assembled into device networks. Memristive components are particularly interesting for this purpose because of their non-linear and memory characteristics. In addition, they can be integrated very densely and provide rich dynamics with a few components only. We use pattern recognition and associative memory tasks to illustrate the memristive reservoir computing approach. For that purpose, we have built a software framework that allows to create valid memristor networks, to simulate and evaluate them in Ngspice, and to train the readout layer by means of a Genetic Algorithm (GA). Our results show that we can efficiently and robustly classify temporal patterns. The approach presents a promising new computing paradigm that harnesses the non-linear, time-dependent, and highly-variable properties of current memristive components for solving computational tasks.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116687243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the high complexity of current digital circuits, the use of gate-level models during the design process is mandatory. For standard CMOS technologies, designers assemble standard cells for which the gate-level model is provided by the founderies. For a given technology, the temporal parameters (such as propagation delays) are constants that can be extracted from experimental measurements. For FinFET-based circuits, such standard cells do not exist. As a consequence, to get predictive simulations of a circuit, the use of low-level model is required. To overcome this problem, we develop a predictive gate-level model for such circuits. To feed the timing parameters of the models, an automated procedure is established. It is based on a new compact model for ultimate FinFET mostly based on physical equations we recently develop. The results obtained with both approaches (compact model and gate-level model) are compared in the last part of the paper. For a digital circuit with about 80 transistors, the results are in accordance. The slight inaccuracy of the gate-level model is largely compensated by a very short simulation time.
{"title":"Gate-level modeling for CMOS circuit simulation with ultimate FinFETs","authors":"N. Chevillon, M. Madec, C. Lallement","doi":"10.1145/2765491.2765497","DOIUrl":"https://doi.org/10.1145/2765491.2765497","url":null,"abstract":"With the high complexity of current digital circuits, the use of gate-level models during the design process is mandatory. For standard CMOS technologies, designers assemble standard cells for which the gate-level model is provided by the founderies. For a given technology, the temporal parameters (such as propagation delays) are constants that can be extracted from experimental measurements. For FinFET-based circuits, such standard cells do not exist. As a consequence, to get predictive simulations of a circuit, the use of low-level model is required. To overcome this problem, we develop a predictive gate-level model for such circuits. To feed the timing parameters of the models, an automated procedure is established. It is based on a new compact model for ultimate FinFET mostly based on physical equations we recently develop. The results obtained with both approaches (compact model and gate-level model) are compared in the last part of the paper. For a digital circuit with about 80 transistors, the results are in accordance. The slight inaccuracy of the gate-level model is largely compensated by a very short simulation time.","PeriodicalId":287602,"journal":{"name":"2012 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)","volume":"52 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114001038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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