Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284379
F. Howell, R. Williams, R. Ibbett
The Hierarchical Architecture Design and Simulation Environment (HASE) is a tool for modelling and simulating computer architectures. Using HASE, designers can create and explore architectural designs at different levels of abstraction through a graphical interface based on X-Windows/Motif and can view the results of the simulation through animation of the design drawings.<>
{"title":"Hierarchical Architecture Design and Simulation Environment","authors":"F. Howell, R. Williams, R. Ibbett","doi":"10.1109/MASCOT.1994.284379","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284379","url":null,"abstract":"The Hierarchical Architecture Design and Simulation Environment (HASE) is a tool for modelling and simulating computer architectures. Using HASE, designers can create and explore architectural designs at different levels of abstraction through a graphical interface based on X-Windows/Motif and can view the results of the simulation through animation of the design drawings.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127328043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284439
Barbara K. Pasquale, George C. Polyzos
Characterizing the I/O demands of scientific applications is an integral part of the solution to the I/O bottleneck problem in high performance systems. Knowledge of the type, volume, and frequency of events that occur in common patterns of I/O activity can provide insight into the policies and mechanisms needed at all levels of the memory hierarchy. This paper is a detailed case study of one scientific application's dynamic I/O behavior. Results from this study show that with appropriate measurement tools, dynamic I/O behavior can be characterized and regular, recurring patterns of I/O activity can be isolated.<>
{"title":"A case study of scientific application I/O behavior","authors":"Barbara K. Pasquale, George C. Polyzos","doi":"10.1109/MASCOT.1994.284439","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284439","url":null,"abstract":"Characterizing the I/O demands of scientific applications is an integral part of the solution to the I/O bottleneck problem in high performance systems. Knowledge of the type, volume, and frequency of events that occur in common patterns of I/O activity can provide insight into the policies and mechanisms needed at all levels of the memory hierarchy. This paper is a detailed case study of one scientific application's dynamic I/O behavior. Results from this study show that with appropriate measurement tools, dynamic I/O behavior can be characterized and regular, recurring patterns of I/O activity can be isolated.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126741045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284389
H. Kari, Heikki Saikkonen, F. Lombardi
The authors present new improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material. In case of media deterioration on the rarely accessed sectors, a latent disk fault may remain undetected for a long time. An adaptive algorithm is proposed to utilize the idle time of the disk for scanning commonly used SCSI disks.<>
{"title":"Detecting latent sector faults in modern SCSI disks","authors":"H. Kari, Heikki Saikkonen, F. Lombardi","doi":"10.1109/MASCOT.1994.284389","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284389","url":null,"abstract":"The authors present new improved methods for detecting latent sector faults in a disk subsystem as caused by media deterioration of the disk magnetic storage material. In case of media deterioration on the rarely accessed sectors, a latent disk fault may remain undetected for a long time. An adaptive algorithm is proposed to utilize the idle time of the disk for scanning commonly used SCSI disks.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"4 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284403
G. Manduchi, M. Moro
The paper describes a programming environment based on the timed Petri net paradigm with generally distributed transition firing times and with several execution policies. The user interaction is supported by a X Window-based graphical interface. The graphical editor, which allows both bottom-up and top-down modeling, is based on a hierarchy (toolkit) of graphical objects (widgets). A discrete-event simulator is provided: it is composed by a set of basic simulation objects assembled from the model description. A simulator prototype has been developed using the C++ programming language.<>
{"title":"An object oriented approach in building an environment for simulation and analysis based on timed Petri nets with multiple execution policies","authors":"G. Manduchi, M. Moro","doi":"10.1109/MASCOT.1994.284403","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284403","url":null,"abstract":"The paper describes a programming environment based on the timed Petri net paradigm with generally distributed transition firing times and with several execution policies. The user interaction is supported by a X Window-based graphical interface. The graphical editor, which allows both bottom-up and top-down modeling, is based on a hierarchy (toolkit) of graphical objects (widgets). A discrete-event simulator is provided: it is composed by a set of basic simulation objects assembled from the model description. A simulator prototype has been developed using the C++ programming language.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123773430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284420
J. E. Butler, V. Wallentine
We present the latest implementation of our Remote Process Execution (RPE) mechanism for parallel discrete-event simulation (PDES), along with results of an empirical study of its performance. RPE is an optimistic time warp based mechanism, which allows logical processes on one processor to execute remotely on another when the former is lagging behind in the computation. The advantage is that processors running too far ahead need neither wait, nor run excessively optimistically: they can instead do some useful work for processors which are falling behind. The disadvantage of course, is the cost associated with running processes remotely. The experiments we have run so far show that performance can be significantly enhanced through RPE under the right conditions. In particular, as expected, the site of computation grains was found to be of primary importance. Though our tests were ran with relatively few processors, we suggest a few simple modifications which should allow the scheme to work well for large numbers of computing elements.<>
{"title":"A performance study of the RPE mechanism for PDES","authors":"J. E. Butler, V. Wallentine","doi":"10.1109/MASCOT.1994.284420","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284420","url":null,"abstract":"We present the latest implementation of our Remote Process Execution (RPE) mechanism for parallel discrete-event simulation (PDES), along with results of an empirical study of its performance. RPE is an optimistic time warp based mechanism, which allows logical processes on one processor to execute remotely on another when the former is lagging behind in the computation. The advantage is that processors running too far ahead need neither wait, nor run excessively optimistically: they can instead do some useful work for processors which are falling behind. The disadvantage of course, is the cost associated with running processes remotely. The experiments we have run so far show that performance can be significantly enhanced through RPE under the right conditions. In particular, as expected, the site of computation grains was found to be of primary importance. Though our tests were ran with relatively few processors, we suggest a few simple modifications which should allow the scheme to work well for large numbers of computing elements.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122110850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284382
P. Bond, Bruce C. Kim, Christopher A. Lee, D. Schimmel
The authors describe a trace collection system that provides complete, accurate, and long traces. A methodology for generating multiprocessor traces from uniprocessor traces is presented, and the implementation of a multiprocesser simulator is discussed. Some programs that contain multiple processes with synchronization information have been run on a uniprocessor system to collect traces utilizing a hardware trace collection system. These traces are used to simulate a multiprocessor system.<>
{"title":"A methodology for generation and collection of multiprocessor traces","authors":"P. Bond, Bruce C. Kim, Christopher A. Lee, D. Schimmel","doi":"10.1109/MASCOT.1994.284382","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284382","url":null,"abstract":"The authors describe a trace collection system that provides complete, accurate, and long traces. A methodology for generating multiprocessor traces from uniprocessor traces is presented, and the implementation of a multiprocesser simulator is discussed. Some programs that contain multiple processes with synchronization information have been run on a uniprocessor system to collect traces utilizing a hardware trace collection system. These traces are used to simulate a multiprocessor system.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131195116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284387
Russell O. Cleaver, S. Midkiff
The authors describe a case study that demonstrates the integration of network monitoring with visualization. The AVS visualization package is used to graphically display the output of the tcpdump network monitor. The visualization system allows the user to simultaneously view multiple parameters and to discern relationships that may not be readily observable from numerical data or standard plots of data.<>
{"title":"Visualization of network performance using the AVS visualization system","authors":"Russell O. Cleaver, S. Midkiff","doi":"10.1109/MASCOT.1994.284387","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284387","url":null,"abstract":"The authors describe a case study that demonstrates the integration of network monitoring with visualization. The AVS visualization package is used to graphically display the output of the tcpdump network monitor. The visualization system allows the user to simultaneously view multiple parameters and to discern relationships that may not be readily observable from numerical data or standard plots of data.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132135599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284425
S. Sarukkai
Tools to study the scalability of parallel programs, as number of processors (p) executing the program and problem size (n) being solved are increased, are a critical component of performance debugging environments for parallel programs. Simulations and scalability metrics have been used to address this issue. Simulation can accurately predict the execution time of a program for a specific (n,p) pair. However, it suffers from the drawback that one needs to simulate the program for each (n,p) pair of interest. On the other hand, while scalability metrics express the program performance as functions of n and p, they have been targeted to specific applications and there are no tools to automatically obtain simple first order scalability trends for generic parallel programs. We address the issue of automatically obtaining scalability trends for a class of data-independent message passing SPMD parallel programs. We validate our approach by considering example parallel programs executed on the Intel iPSC/860 hypercube. We show that insight into the scalability of the program can be obtained, using this approach.<>
{"title":"Scalability analysis tools for SPMD message-passing parallel programs","authors":"S. Sarukkai","doi":"10.1109/MASCOT.1994.284425","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284425","url":null,"abstract":"Tools to study the scalability of parallel programs, as number of processors (p) executing the program and problem size (n) being solved are increased, are a critical component of performance debugging environments for parallel programs. Simulations and scalability metrics have been used to address this issue. Simulation can accurately predict the execution time of a program for a specific (n,p) pair. However, it suffers from the drawback that one needs to simulate the program for each (n,p) pair of interest. On the other hand, while scalability metrics express the program performance as functions of n and p, they have been targeted to specific applications and there are no tools to automatically obtain simple first order scalability trends for generic parallel programs. We address the issue of automatically obtaining scalability trends for a class of data-independent message passing SPMD parallel programs. We validate our approach by considering example parallel programs executed on the Intel iPSC/860 hypercube. We show that insight into the scalability of the program can be obtained, using this approach.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133223979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284405
G. Kesidis
Describes and compares two classes of approaches to estimating the effective bandwidth of a traffic source of fixed-length packets (cells) in a high-speed network. In one class of approaches, the arrival times of the source are monitored and modeled by, e.g., a Markov-modulated Poisson process; the effective bandwidth of the model is then used to estimate that of the source. In the other class of approaches, points on the effective bandwidth curve of the source are estimated by monitoring the occupancy of buffers; an estimate of the effective bandwidth curve of the source is then found by interpolation and extrapolation using these points.<>
{"title":"Modeling to obtain the effective bandwidth of a traffic source in an ATM network","authors":"G. Kesidis","doi":"10.1109/MASCOT.1994.284405","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284405","url":null,"abstract":"Describes and compares two classes of approaches to estimating the effective bandwidth of a traffic source of fixed-length packets (cells) in a high-speed network. In one class of approaches, the arrival times of the source are monitored and modeled by, e.g., a Markov-modulated Poisson process; the effective bandwidth of the model is then used to estimate that of the source. In the other class of approaches, points on the effective bandwidth curve of the source are estimated by monitoring the occupancy of buffers; an estimate of the effective bandwidth curve of the source is then found by interpolation and extrapolation using these points.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125549214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-01-31DOI: 10.1109/MASCOT.1994.284401
Hatem Sellami, James D. Allen, D. Schimmel, S. Yalamanchili
This paper describes and evaluates the performance of an implementation of a parallel discrete event simulation of a class of Petri nets known as marked graphs on a single instruction stream multiple data stream (SIMD) architecture. The implementation uses an efficient, novel memory management technique for supporting abstract data types, where memory can be dynamically allocated/deallocated on an individual PE basis. Performance evaluations are reported for a number of "real world" applications.<>
{"title":"Simulation of marked graphs on SIMD architectures using efficient memory management","authors":"Hatem Sellami, James D. Allen, D. Schimmel, S. Yalamanchili","doi":"10.1109/MASCOT.1994.284401","DOIUrl":"https://doi.org/10.1109/MASCOT.1994.284401","url":null,"abstract":"This paper describes and evaluates the performance of an implementation of a parallel discrete event simulation of a class of Petri nets known as marked graphs on a single instruction stream multiple data stream (SIMD) architecture. The implementation uses an efficient, novel memory management technique for supporting abstract data types, where memory can be dynamically allocated/deallocated on an individual PE basis. Performance evaluations are reported for a number of \"real world\" applications.<<ETX>>","PeriodicalId":288344,"journal":{"name":"Proceedings of International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunication Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129169797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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