Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809868
R. R. Shafiq, B. M. Elhalawany, M. M. Elsherbini
Energy harvesting (EH) circuits are expected to be key modules for future battery-constrained electronic devices such as mobile phones and wearable devices. Radio-frequency (RF) harvesting is one of the promising EH technologies, which converts RF signals into direct-current (DC) voltage. This paper proposed an efficient design for the voltage doubler subsystem for an RF-EH module using different types of Schottky diodes, namely HSMS-2822, HSMS-2850, and HSMS-286B. Greinacher voltage doubler circuits for multi-bands including 915 MHz (GSM), (2.4, and 5.2) GHz (WI-FI) bands are scrutinized. Up to 10 stages of Schottky diode voltage doubler circuits are investigated, where the performance is evaluated using Agilent ADS software. The results showed that the HSMS-286B Schottky diode reveals a better performance with GSM band sources, while HSMS-2850 is the Optimum choice for the WI-FI band.
{"title":"Radio-Frequency Energy Harvesting Systems for GSM and WiFi Bands","authors":"R. R. Shafiq, B. M. Elhalawany, M. M. Elsherbini","doi":"10.1109/DTS55284.2022.9809868","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809868","url":null,"abstract":"Energy harvesting (EH) circuits are expected to be key modules for future battery-constrained electronic devices such as mobile phones and wearable devices. Radio-frequency (RF) harvesting is one of the promising EH technologies, which converts RF signals into direct-current (DC) voltage. This paper proposed an efficient design for the voltage doubler subsystem for an RF-EH module using different types of Schottky diodes, namely HSMS-2822, HSMS-2850, and HSMS-286B. Greinacher voltage doubler circuits for multi-bands including 915 MHz (GSM), (2.4, and 5.2) GHz (WI-FI) bands are scrutinized. Up to 10 stages of Schottky diode voltage doubler circuits are investigated, where the performance is evaluated using Agilent ADS software. The results showed that the HSMS-286B Schottky diode reveals a better performance with GSM band sources, while HSMS-2850 is the Optimum choice for the WI-FI band.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130016337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809861
N. Prokopenko, A. Titov, A. Bugakova, V. Chumakov
Circuit solutions CJFET three-stage OpAmp, in which non-ideal current mirrors (CMs) with a current transfer coefficient different from unity can be used in the intermediate stage, are considered. An OpAmp architecture in which the CM and all static-setting transistor references are replaced with identical JFET uncontrolled dynamic loads is proposed. Computer modeling in the CAD LTSpice (Analog Device, USA) and mathematical analysis of the proposed OpAmps made it possible to establish that OpAmp circuits are operable at negative temperatures (up to −197°C) and when exposed to a neutron flux up to 1014 n/cm2, have high values of open-loop gain (up to 100dB) and a small systematic component of the zero bias voltage due to the OpAmp circuitry.
{"title":"Circuitry Approaches for Reducing of the Zero Level in Three-Stage CJFET Operational Amplifier","authors":"N. Prokopenko, A. Titov, A. Bugakova, V. Chumakov","doi":"10.1109/DTS55284.2022.9809861","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809861","url":null,"abstract":"Circuit solutions CJFET three-stage OpAmp, in which non-ideal current mirrors (CMs) with a current transfer coefficient different from unity can be used in the intermediate stage, are considered. An OpAmp architecture in which the CM and all static-setting transistor references are replaced with identical JFET uncontrolled dynamic loads is proposed. Computer modeling in the CAD LTSpice (Analog Device, USA) and mathematical analysis of the proposed OpAmps made it possible to establish that OpAmp circuits are operable at negative temperatures (up to −197°C) and when exposed to a neutron flux up to 1014 n/cm2, have high values of open-loop gain (up to 100dB) and a small systematic component of the zero bias voltage due to the OpAmp circuitry.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126556668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809885
Basel Halak, Christian Hall, Syed Fathir, Nelson Kit, Ruwaydah Raymonde, Hugo Vincent
Existing anti-tamper designs protect against limited forms of attacks and have deterministic tamper responses, which can undermine the availability of systems. Advancements in physical inspection techniques have enabled stealthier attacks. Therefore, there is a pressing need for more intelligent defenses that ensure a longer operational time while keeping up with the expected increase in the capabilities of adversaries. This study proposes to enhance existing physical protection methods by developing an intelligent anti-tamper using machine learning algorithms. It uses an analytic system capable of detecting and classifying multiple types of behaviors (e.g., normal operation conditions, known attack vectors, and anomalous behavior). A prototype of the proposed system has been implemented and its functionality has been successfully verified for two types of normal operating conditions and further four forms of physical attacks. In addition, a systematic threat modelling analysis and security validation was carried out, which indicated the proposed solution provides better protection against including information leakage, loss of data, and disruption of operation.
{"title":"Intelligent Tamper Detection Systems using Machine Learning","authors":"Basel Halak, Christian Hall, Syed Fathir, Nelson Kit, Ruwaydah Raymonde, Hugo Vincent","doi":"10.1109/DTS55284.2022.9809885","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809885","url":null,"abstract":"Existing anti-tamper designs protect against limited forms of attacks and have deterministic tamper responses, which can undermine the availability of systems. Advancements in physical inspection techniques have enabled stealthier attacks. Therefore, there is a pressing need for more intelligent defenses that ensure a longer operational time while keeping up with the expected increase in the capabilities of adversaries. This study proposes to enhance existing physical protection methods by developing an intelligent anti-tamper using machine learning algorithms. It uses an analytic system capable of detecting and classifying multiple types of behaviors (e.g., normal operation conditions, known attack vectors, and anomalous behavior). A prototype of the proposed system has been implemented and its functionality has been successfully verified for two types of normal operating conditions and further four forms of physical attacks. In addition, a systematic threat modelling analysis and security validation was carried out, which indicated the proposed solution provides better protection against including information leakage, loss of data, and disruption of operation.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"312 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131675195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809888
Bouthaina Abdallah, Sonda Ben Jdidia, Fatma Belghith, Mohamed Ali Ben Ayed, N. Masmoudi
The Versatile Video Coding (VVC) standard enhances the coding performance in terms of bitrate and quality compared to its predecessor High Efficiency Video Coding (HEVC) at the expense of an additional coding complexity. This complexity is due to the new partitioning improvement named quadtree with nested multi-type tree (QTMT) which includes more partition shapes increasing the rate-distortion optimization (RDO) complexity. In this paper, a fast QTMT partition approach based on the Convolutional Neural Network (CNN) is proposed for the purpose of reducing the computational complexity. In fact, an intra QTMT decision tree method using a Convolutional Neural Network-binary tree horizontal (CNN-BTH) model is elaborated to determine the BTH decision depths at the 32×32 block size. The suggested fast partitioning algorithm achieves an important gain in the encoding time up to 64.26% compared to the original VVC software reference VTM-3.0. It allows a significant computational complexity reduction of 58.28% on average and an acceptable loss in the encoding performance.
{"title":"A CNN-based QTMT partitioning decision for the VVC standard","authors":"Bouthaina Abdallah, Sonda Ben Jdidia, Fatma Belghith, Mohamed Ali Ben Ayed, N. Masmoudi","doi":"10.1109/DTS55284.2022.9809888","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809888","url":null,"abstract":"The Versatile Video Coding (VVC) standard enhances the coding performance in terms of bitrate and quality compared to its predecessor High Efficiency Video Coding (HEVC) at the expense of an additional coding complexity. This complexity is due to the new partitioning improvement named quadtree with nested multi-type tree (QTMT) which includes more partition shapes increasing the rate-distortion optimization (RDO) complexity. In this paper, a fast QTMT partition approach based on the Convolutional Neural Network (CNN) is proposed for the purpose of reducing the computational complexity. In fact, an intra QTMT decision tree method using a Convolutional Neural Network-binary tree horizontal (CNN-BTH) model is elaborated to determine the BTH decision depths at the 32×32 block size. The suggested fast partitioning algorithm achieves an important gain in the encoding time up to 64.26% compared to the original VVC software reference VTM-3.0. It allows a significant computational complexity reduction of 58.28% on average and an acceptable loss in the encoding performance.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132795120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809846
N. B. Messaoud, C. Dridi, M. N. Abbas
An optical sensor for perchlorate anions (CIO4-) comprising a structure of Cobalt phthalocyanine derivative (Co(II)Pc-PAA) modified glass electrode has been developed. The immobilization of Co(II)Pc-PAA membrane was confirmed by contact angle measurements. The response was determined by the increase in the absorbance signal as a function of exposure to buffer solutions containing different concentrations of CIO4- anions. The optical sensor showed a linear response to CI04- from 10–10M to 10–2 M, with a limit of detection of 4.81 Χ10−10M, one of the lowest achieved up until now. The proposed sensor has demonstrated a good specificity to CIO4- when compared to common interferents anions such as CI−and NO3-. To the best of our knowledge, this is the first optode system for the detection of CIO4-, which provides a promising sensor for the specific and sensitive determination of CIO4- in environmental water samples.
{"title":"Development of optical sensor for determination of perchlorate ions","authors":"N. B. Messaoud, C. Dridi, M. N. Abbas","doi":"10.1109/DTS55284.2022.9809846","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809846","url":null,"abstract":"An optical sensor for perchlorate anions (CIO<inf>4</inf>-) comprising a structure of Cobalt phthalocyanine derivative (Co(II)Pc-PAA) modified glass electrode has been developed. The immobilization of Co(II)Pc-PAA membrane was confirmed by contact angle measurements. The response was determined by the increase in the absorbance signal as a function of exposure to buffer solutions containing different concentrations of CIO<inf>4</inf>- anions. The optical sensor showed a linear response to CI04- from 10<sup>–10</sup>M to 10<sup>–2</sup> M, with a limit of detection of 4.81 Χ10<sup>−10</sup>M, one of the lowest achieved up until now. The proposed sensor has demonstrated a good specificity to CIO<inf>4</inf>- when compared to common interferents anions such as CI<sup>−</sup>and NO<inf>3</inf>-. To the best of our knowledge, this is the first optode system for the detection of CIO<inf>4</inf>-, which provides a promising sensor for the specific and sensitive determination of CIO<inf>4</inf>- in environmental water samples.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809905
Ali H. Al-timemy, Y. Serrestou, R. Khushaba, S. Yacoub, K. Raoof
Upper limb prosthesis control with pattern recognition (PR)- based on surface Electromyogram (EMG) signals has been heavily investigated in the literature. However, challenges related to signal non-stationarity and its impact by changing force levels, limb positions and many other factors all lead to poor system stability, prevent the widespread adoption of this technology. In this study, we propose an alternative modality based on Acoustic Myography (AMG), a recording of muscle vibrations at low frequencies, as a control signal to decipher the intended hand movements. A custom-built AMG armband, consisting of 4 microphones, has been developed in this study and evaluated on intact-limbed subjects performing six classes of hand and finger movements. Time domain and auto-regression (TD-AR) features, in addition to Bi long-short term memory (BiLSTM) deep learning classifier were utilized to perform the classification. An average classification accuracy of 85% was obtained, which shows the potential of using the developed AMG armband, with PR system for prostheses control.
{"title":"Hand Movement Recognition with Long Short-Term Memory based Pattern Recognition of Acoustic Myography signals","authors":"Ali H. Al-timemy, Y. Serrestou, R. Khushaba, S. Yacoub, K. Raoof","doi":"10.1109/DTS55284.2022.9809905","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809905","url":null,"abstract":"Upper limb prosthesis control with pattern recognition (PR)- based on surface Electromyogram (EMG) signals has been heavily investigated in the literature. However, challenges related to signal non-stationarity and its impact by changing force levels, limb positions and many other factors all lead to poor system stability, prevent the widespread adoption of this technology. In this study, we propose an alternative modality based on Acoustic Myography (AMG), a recording of muscle vibrations at low frequencies, as a control signal to decipher the intended hand movements. A custom-built AMG armband, consisting of 4 microphones, has been developed in this study and evaluated on intact-limbed subjects performing six classes of hand and finger movements. Time domain and auto-regression (TD-AR) features, in addition to Bi long-short term memory (BiLSTM) deep learning classifier were utilized to perform the classification. An average classification accuracy of 85% was obtained, which shows the potential of using the developed AMG armband, with PR system for prostheses control.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"518 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124481117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809852
Sehmi Saad, F. Haddad, Aymen Ben Hammadi
Design of a CMOS compact tunable differential active inductor (DAI) suitable to low-cost and multi-standard systems is presented. The structure uses only active components, based on the Gyrator-C topology approach with two cross-coupled pairs and an additive feedback resistance to enhance the quality factor (Q). The proposed DAI, implemented in 130 nm CMOS process, achieves a Self-Resonance Frequency (SRF) from few Megahertz to 3.3 GHz. As well, it demonstrates a Q ≈ 388 at 2.31GHz, while the achieved inductance tuning range varies from 33 nH to 98 nH. The circuit consumes 7.28 mW from 1.2 V supply and occupies a small area of only (19×45) um2, Noise, linearity and sensitivity of the proposed DAI to process and mismatch variations are also studied in the paper.
{"title":"High-Performance CMOS Tunable Differential Active Inductor for RF applications","authors":"Sehmi Saad, F. Haddad, Aymen Ben Hammadi","doi":"10.1109/DTS55284.2022.9809852","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809852","url":null,"abstract":"Design of a CMOS compact tunable differential active inductor (DAI) suitable to low-cost and multi-standard systems is presented. The structure uses only active components, based on the Gyrator-C topology approach with two cross-coupled pairs and an additive feedback resistance to enhance the quality factor (Q). The proposed DAI, implemented in 130 nm CMOS process, achieves a Self-Resonance Frequency (SRF) from few Megahertz to 3.3 GHz. As well, it demonstrates a Q ≈ 388 at 2.31GHz, while the achieved inductance tuning range varies from 33 nH to 98 nH. The circuit consumes 7.28 mW from 1.2 V supply and occupies a small area of only (19×45) um2, Noise, linearity and sensitivity of the proposed DAI to process and mismatch variations are also studied in the paper.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122208135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809864
Avinash Yadhav, M. Rizkalla, T. Ytterdal, J. J. Lee, L. Balasubramanian, A. Gopinath
The data path and memory elements are integral hardware components to evaluate the performance of a complex ASIC low power architecture. In this study, a FinFET model was evaluated via 7 nm FinFET process using ASAP PDK and applied to 6T SRAM cells and 32-bit ALU architecture. Devices of 0.207 V threshold were biased at 0.7V supply voltage. The clock router was properly modeled with accurate values of resistances and capacitances for the metal layers. The noise glitch and cross talk within the parallel running interconnects and the driving loads were incorporated in the model. A command set clock uncertainty is also integrated into the model to incorporate the clock jitter and clock skew effects. The architecture was optimized for worst case scenario with typical RC corners. The Non-Linear Delay Model (NLDM) was incorporated for the cell synthesis where a delay that is based on the input transition and output load capacitance was incorporated for better quality of results (QoR). The low power architecture was evaluated for worst case scenario considering typical-typical (TT) corners. A maximum effective device current of 18.26µA with subthreshold slope of 60mV/decade were estimated and considered in the system evaluation. The output ports were loaded with a typical 2fF capacitance. At 1 GHz operation, the internal power, switching power, and leakage power are reported to be 0.2705 mW, 0.7599 mW, and 0.00743 mW, respectively.
{"title":"Evaluation of FinFET in Ultra Low Power ALU","authors":"Avinash Yadhav, M. Rizkalla, T. Ytterdal, J. J. Lee, L. Balasubramanian, A. Gopinath","doi":"10.1109/DTS55284.2022.9809864","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809864","url":null,"abstract":"The data path and memory elements are integral hardware components to evaluate the performance of a complex ASIC low power architecture. In this study, a FinFET model was evaluated via 7 nm FinFET process using ASAP PDK and applied to 6T SRAM cells and 32-bit ALU architecture. Devices of 0.207 V threshold were biased at 0.7V supply voltage. The clock router was properly modeled with accurate values of resistances and capacitances for the metal layers. The noise glitch and cross talk within the parallel running interconnects and the driving loads were incorporated in the model. A command set clock uncertainty is also integrated into the model to incorporate the clock jitter and clock skew effects. The architecture was optimized for worst case scenario with typical RC corners. The Non-Linear Delay Model (NLDM) was incorporated for the cell synthesis where a delay that is based on the input transition and output load capacitance was incorporated for better quality of results (QoR). The low power architecture was evaluated for worst case scenario considering typical-typical (TT) corners. A maximum effective device current of 18.26µA with subthreshold slope of 60mV/decade were estimated and considered in the system evaluation. The output ports were loaded with a typical 2fF capacitance. At 1 GHz operation, the internal power, switching power, and leakage power are reported to be 0.2705 mW, 0.7599 mW, and 0.00743 mW, respectively.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128032778","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809874
M. Kelany, Shaimaa Ib. Aref, M. Kana, Y. Sabry, Hasnaa M. Fahmy, D. Khalil
Colloidal quantum dots (CQDs) have various uses in photodetectors, solar cell devices and spectroscopic signal enhancement. In this paper, we synthesize mercury telluride (HgTe) CQDs and study the effect of the QDs size distribution on their infrared absorbance spectrum. The resulting dots are characterized using x-ray diffraction analysis and the size was found to be about 8.6 nm with a standard deviation of about 2 nm using high-resolution transmission electron microscope. The produced CQDs are optically characterized using Fourier transform infrared spectrometer in diffuse reflectance mode in the wavelength range from 3 to 11 μm. The absorption shows a wide absorption edge rather than a sharp feature. The measured data are fitted with a sum of a polynomial and five gaussian functions to extract the absorption lines of the QDs.
{"title":"Infrared Absorbance of Distributed-Size HgTe Quantum Dots Under Diffuse Reflectance","authors":"M. Kelany, Shaimaa Ib. Aref, M. Kana, Y. Sabry, Hasnaa M. Fahmy, D. Khalil","doi":"10.1109/DTS55284.2022.9809874","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809874","url":null,"abstract":"Colloidal quantum dots (CQDs) have various uses in photodetectors, solar cell devices and spectroscopic signal enhancement. In this paper, we synthesize mercury telluride (HgTe) CQDs and study the effect of the QDs size distribution on their infrared absorbance spectrum. The resulting dots are characterized using x-ray diffraction analysis and the size was found to be about 8.6 nm with a standard deviation of about 2 nm using high-resolution transmission electron microscope. The produced CQDs are optically characterized using Fourier transform infrared spectrometer in diffuse reflectance mode in the wavelength range from 3 to 11 μm. The absorption shows a wide absorption edge rather than a sharp feature. The measured data are fitted with a sum of a polynomial and five gaussian functions to extract the absorption lines of the QDs.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124011998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-06DOI: 10.1109/DTS55284.2022.9809845
Mariem Bouraoui, I. Barraj, Amel Neifar, M. Masmoudi
The design of an ultra-wideband low-noise amplifier for wake-up receiver applications is discussed in this article. The LNA circuit is developed for the 3–9 GHz frequency ranges using RF-TSMC CMOS 0.18µm. To lower the noise figure, substrate resistance is added. The improved LNA achieves a low noise figure of 1.66 dB, which is 47% better than the original circuit, and a maximum power gain of 21.02 dB over the operating frequency range. The designed LNA dissipates 12.3mW at 1V.
{"title":"An Ultra-Wideband noise-reduction LNA With Variable Gain for Wireless Wake-up Receivers","authors":"Mariem Bouraoui, I. Barraj, Amel Neifar, M. Masmoudi","doi":"10.1109/DTS55284.2022.9809845","DOIUrl":"https://doi.org/10.1109/DTS55284.2022.9809845","url":null,"abstract":"The design of an ultra-wideband low-noise amplifier for wake-up receiver applications is discussed in this article. The LNA circuit is developed for the 3–9 GHz frequency ranges using RF-TSMC CMOS 0.18µm. To lower the noise figure, substrate resistance is added. The improved LNA achieves a low noise figure of 1.66 dB, which is 47% better than the original circuit, and a maximum power gain of 21.02 dB over the operating frequency range. The designed LNA dissipates 12.3mW at 1V.","PeriodicalId":290904,"journal":{"name":"2022 IEEE International Conference on Design & Test of Integrated Micro & Nano-Systems (DTS)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125920187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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