Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356716
J. Techer, S. Bernard, Y. Bertrand, G. Cathébras, D. Guiraud
We propose a new implantable circuit for the internal functional electrical stimulation (FES) of motor nerves for paraplegic people. The circuit is designed to deliver precise calibrated stimulation pulses to specific multipolar electrodes. Several original design features have been developed to respond to the particular specifications imposed by safety constraints. In particular, the DAC has been thought to be fully monotonic and the output stage to ensure a passive and secure discharge of the safety capacitor. Also some features have been added in order to improve the classical charge pump that generates on-chip high voltage.
{"title":"New implantable stimulator for the FES of paralyzed muscles","authors":"J. Techer, S. Bernard, Y. Bertrand, G. Cathébras, D. Guiraud","doi":"10.1109/ESSCIR.2004.1356716","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356716","url":null,"abstract":"We propose a new implantable circuit for the internal functional electrical stimulation (FES) of motor nerves for paraplegic people. The circuit is designed to deliver precise calibrated stimulation pulses to specific multipolar electrodes. Several original design features have been developed to respond to the particular specifications imposed by safety constraints. In particular, the DAC has been thought to be fully monotonic and the output stage to ensure a passive and secure discharge of the safety capacitor. Also some features have been added in order to improve the classical charge pump that generates on-chip high voltage.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123157312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356696
Tsung-Te Liu, Chorng-Kuang Wang
This paper presents an implementation of a low-jitter wide-range multi-phase clock generator using a delay-locked loop (DLL) for ultra-wideband (UWB) application. The analog-digital dual-loop adaptive-bandwidth structure, in conjunction with a complementary phase detector (PD), ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. The 0.18-/spl mu/m CMOS prototype exhibits a maximum clock jitter of 3.9 ps (rms) and 28.7 ps (pk-pk) at an output clock rate of 1.6 to 8 GHz (50-250 MHz input reference frequency) and consumes 9.7 mW from a 1.8-V supply at 8 GHz.
{"title":"A 0.8-8 GHz 9.7 mW analog-digital dual-loop adaptive-bandwidth DLL based multi-phase clock generator","authors":"Tsung-Te Liu, Chorng-Kuang Wang","doi":"10.1109/ESSCIR.2004.1356696","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356696","url":null,"abstract":"This paper presents an implementation of a low-jitter wide-range multi-phase clock generator using a delay-locked loop (DLL) for ultra-wideband (UWB) application. The analog-digital dual-loop adaptive-bandwidth structure, in conjunction with a complementary phase detector (PD), ensures low-jitter clock generation over a wide frequency range. The self-feedback technique reduces the power consumption of the level-shifter circuit 50% at least. The 0.18-/spl mu/m CMOS prototype exhibits a maximum clock jitter of 3.9 ps (rms) and 28.7 ps (pk-pk) at an output clock rate of 1.6 to 8 GHz (50-250 MHz input reference frequency) and consumes 9.7 mW from a 1.8-V supply at 8 GHz.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"21 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123543019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356706
F. Lustenberger, M. Lehmann, L. Cavalier, N. Blanc, W. Heppner, J. Ernst, S. Gick, H. Bloß
A high-speed, high-sensitivity sensor was developed in a standard 0.5 /spl mu/m CMOS mixed-signal technology for the use in endoscopes. The full frame rate in excess of 3200 frames per second enables the imaging of transient events in biomedical samples. The sensor is organized as a 512/spl times/192 pixel array with additional RGB dye filters. Data are transferred from the sensor on either 4 or 8 analogue signal taps. The imager reaches a sensitivity of 130 V//spl mu/J.cm/sup -2/ at a wavelength of 470 nm with a dynamic range of 62 dB and 50.2 dB in linear mode and charge-skimming mode, respectively. The FPN, PRNU and temporal noise were measured to be at 0.7%, 1.1% and 0.08% of the full-scale output range of the sensor. This excellent performance is exploited in the analysis of high-speed transient phenomena of human vocal cords.
{"title":"A colour 3200fps high-speed CMOS imager for endoscopy in bio-medical applications","authors":"F. Lustenberger, M. Lehmann, L. Cavalier, N. Blanc, W. Heppner, J. Ernst, S. Gick, H. Bloß","doi":"10.1109/ESSCIR.2004.1356706","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356706","url":null,"abstract":"A high-speed, high-sensitivity sensor was developed in a standard 0.5 /spl mu/m CMOS mixed-signal technology for the use in endoscopes. The full frame rate in excess of 3200 frames per second enables the imaging of transient events in biomedical samples. The sensor is organized as a 512/spl times/192 pixel array with additional RGB dye filters. Data are transferred from the sensor on either 4 or 8 analogue signal taps. The imager reaches a sensitivity of 130 V//spl mu/J.cm/sup -2/ at a wavelength of 470 nm with a dynamic range of 62 dB and 50.2 dB in linear mode and charge-skimming mode, respectively. The FPN, PRNU and temporal noise were measured to be at 0.7%, 1.1% and 0.08% of the full-scale output range of the sensor. This excellent performance is exploited in the analysis of high-speed transient phenomena of human vocal cords.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124311947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356704
G. D. Graaf, L. Mol, L. Rocha, E. Cretu, R. Wolffenbuttel
An AC-operated capacitive accelerometer with electrostatic force feedback is employed for direct mechanical spectrum analysis. A suitable electrostatic AC field is used to make the accelerometer selectively sensitive to only the coherent mechanical frequency component. By sweeping the frequency of the drive voltage over a selected range, the mechanical (vibration) spectrum is analysed in the mechanical domain. Operation requires the simultaneous generation of predistorted sine- and cosine-like waveforms. A DDFS with DAC, based on a specially scaled resistive string, is designed, fabricated in CMOS and tested. Spurious free dynamic range is 22 dB over a frequency range of DC up to 1 kHz. The spectral performance is comparable to FFT-based systems for spectral analysis on a time series supplied by a conventional accelerometer, while the overall system features a reduced complexity, simple spectral in-zooming and potential for low power consumption.
{"title":"Quadrature oscillator with pre-distorted waveforms for application in MEMS-based mechanical spectrum analyser","authors":"G. D. Graaf, L. Mol, L. Rocha, E. Cretu, R. Wolffenbuttel","doi":"10.1109/ESSCIR.2004.1356704","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356704","url":null,"abstract":"An AC-operated capacitive accelerometer with electrostatic force feedback is employed for direct mechanical spectrum analysis. A suitable electrostatic AC field is used to make the accelerometer selectively sensitive to only the coherent mechanical frequency component. By sweeping the frequency of the drive voltage over a selected range, the mechanical (vibration) spectrum is analysed in the mechanical domain. Operation requires the simultaneous generation of predistorted sine- and cosine-like waveforms. A DDFS with DAC, based on a specially scaled resistive string, is designed, fabricated in CMOS and tested. Spurious free dynamic range is 22 dB over a frequency range of DC up to 1 kHz. The spectral performance is comparable to FFT-based systems for spectral analysis on a time series supplied by a conventional accelerometer, while the overall system features a reduced complexity, simple spectral in-zooming and potential for low power consumption.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125577350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356617
G. Frantz
This paper gives a broad overview of the evolution of DSP chips. It started with the desire of humans to communicate with computers. It has revolutionized the way we work, live, learn and play. Technology was the first driver. It was replaced by the products we call DSPs as the drivers. We are seeing another transition to the expectations of the end user as the next driver of this amazing revolution.
{"title":"DSP: a technology, a product, a revolution","authors":"G. Frantz","doi":"10.1109/ESSCIR.2004.1356617","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356617","url":null,"abstract":"This paper gives a broad overview of the evolution of DSP chips. It started with the desire of humans to communicate with computers. It has revolutionized the way we work, live, learn and play. Technology was the first driver. It was replaced by the products we call DSPs as the drivers. We are seeing another transition to the expectations of the end user as the next driver of this amazing revolution.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121097482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356607
R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, P. Schindler-Bauer, M. Augustyniak, M. Atzesberger, B. Holzapfl, M. Jenkner, B. Eversmann, G. Beer, M. Fritz, T. Haneder, H. Hanke
An overview is given of CMOS-based sensor- and actuator chips for in-vitro applications in the biotechnology area. We address the challenges and the potential of the combination of solid-state circuits with the wet world of bio molecules and living cells. Basic biological operating principles, market considerations, extended CMOS processing issues and concrete circuit examples are discussed.
{"title":"Integrated circuits for the biology-to-silicon interface [biotechnology]","authors":"R. Thewes, C. Paulus, M. Schienle, F. Hofmann, A. Frey, R. Brederlow, P. Schindler-Bauer, M. Augustyniak, M. Atzesberger, B. Holzapfl, M. Jenkner, B. Eversmann, G. Beer, M. Fritz, T. Haneder, H. Hanke","doi":"10.1109/ESSCIR.2004.1356607","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356607","url":null,"abstract":"An overview is given of CMOS-based sensor- and actuator chips for in-vitro applications in the biotechnology area. We address the challenges and the potential of the combination of solid-state circuits with the wet world of bio molecules and living cells. Basic biological operating principles, market considerations, extended CMOS processing issues and concrete circuit examples are discussed.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121103013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356694
N. Pavlovic, J. Gosselin, K. Mistry, D. Leenaerts
This work presents a fully integrated frequency synthesiser for 802.11 standard. The synthesiser uses a 10 GHz VCO and a 16/17 dual modulus prescaler based on phase switching. The power consumption is 77 mW from a 1.8 V supply. The die size is only 0.43 mm/sup 2/ in a 0.18 /spl mu/m digital five metal CMOS process. The in-band phase noise is below -90 dBc/Hz at 100 kHz, meeting the requirements.
{"title":"A 10 GHz frequency synthesiser for 802.11a in 0.18 /spl mu/m CMOS [transceiver applications]","authors":"N. Pavlovic, J. Gosselin, K. Mistry, D. Leenaerts","doi":"10.1109/ESSCIR.2004.1356694","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356694","url":null,"abstract":"This work presents a fully integrated frequency synthesiser for 802.11 standard. The synthesiser uses a 10 GHz VCO and a 16/17 dual modulus prescaler based on phase switching. The power consumption is 77 mW from a 1.8 V supply. The die size is only 0.43 mm/sup 2/ in a 0.18 /spl mu/m digital five metal CMOS process. The in-band phase noise is below -90 dBc/Hz at 100 kHz, meeting the requirements.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121192282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356724
Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee
This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52 Mb/s and 5.26 Mb/s data rates respectively. The memory access is reduced by the input caching scheme. And the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18 /spl mu/m six-metal standard CMOS process, and the measured power dissipation is 83 mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.
{"title":"A dual mode channel decoder for 3GPP2 mobile wireless communications","authors":"Chien-Ching Lin, Yen-Hsu Shih, Hsie-Chia Chang, Chen-Yi Lee","doi":"10.1109/ESSCIR.2004.1356724","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356724","url":null,"abstract":"This paper presents a turbo and Viterbi decoder single chip for 3GPP2 standard. The turbo decoding with a maximum block length of 20,730 and Viterbi decoding with various coding rates are implemented to provide maximum 4.52 Mb/s and 5.26 Mb/s data rates respectively. The memory access is reduced by the input caching scheme. And the system complexity is lowered by the efficient interleaver design. This chip is fabricated in a 0.18 /spl mu/m six-metal standard CMOS process, and the measured power dissipation is 83 mW while decoding a 3.1 Mb/s turbo encoded data stream with six iterations for each block.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132659827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356648
M. Schimper, Lukas Dörrer, E. Riccio, G. Panov
A continuous-time 4th-order multi-bit /spl Sigma//spl Delta/-modulator for GSM/EDGE is presented. By introduction of a direct feed-forward path from the input to the quantiser, high immunity to adjacent channel interferers is achieved. The dynamic range is 90 dB (>14-bit) over a 240 kHz signal bandwidth. Accurate modelling allows optimisation of excess loop delay, thus yielding a very low power consumption of 3 mW at 1.25 V supply voltage. The modulator is clocked at 26 MHz (oversampling ratio=54). It occupies 0.5 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology.
{"title":"A 3mW continuous-time /spl Sigma//spl Delta/-modulator for EDGE/GSM with high adjacent channel tolerance","authors":"M. Schimper, Lukas Dörrer, E. Riccio, G. Panov","doi":"10.1109/ESSCIR.2004.1356648","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356648","url":null,"abstract":"A continuous-time 4th-order multi-bit /spl Sigma//spl Delta/-modulator for GSM/EDGE is presented. By introduction of a direct feed-forward path from the input to the quantiser, high immunity to adjacent channel interferers is achieved. The dynamic range is 90 dB (>14-bit) over a 240 kHz signal bandwidth. Accurate modelling allows optimisation of excess loop delay, thus yielding a very low power consumption of 3 mW at 1.25 V supply voltage. The modulator is clocked at 26 MHz (oversampling ratio=54). It occupies 0.5 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130429262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356641
V. Colonna, M. Annovazzi, G. Boarin, G. Gandolfi, F. Stefani, A. Baschirotto
In the stereo audio DAC presented here, the trade-off between area-power consumption-SNRout-dynamic range is optimized for the case of a 96 dB audio system. Using a single-op amp switched capacitor structure for the reconstruction filter, a hybrid FIR/IIR transfer function allows it to reject out-of-band noise. This circuit solution strongly reduces area and power consumption. In a 0.13 /spl mu/m CMOS technology, the stereo DAC achieves a 97 dB-dynamic range and a 39 dB SNRout with a 0.22 mm/sup 2/ area and 7.25 mW power consumption per-channel.
{"title":"A 0.22mm/sup 2/ 7.25mW per-channel audio stereo-DAC with 97dB-DR and 39dB SNRout","authors":"V. Colonna, M. Annovazzi, G. Boarin, G. Gandolfi, F. Stefani, A. Baschirotto","doi":"10.1109/ESSCIR.2004.1356641","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356641","url":null,"abstract":"In the stereo audio DAC presented here, the trade-off between area-power consumption-SNRout-dynamic range is optimized for the case of a 96 dB audio system. Using a single-op amp switched capacitor structure for the reconstruction filter, a hybrid FIR/IIR transfer function allows it to reject out-of-band noise. This circuit solution strongly reduces area and power consumption. In a 0.13 /spl mu/m CMOS technology, the stereo DAC achieves a 97 dB-dynamic range and a 39 dB SNRout with a 0.22 mm/sup 2/ area and 7.25 mW power consumption per-channel.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130829260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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