Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356667
B. Xia, A. Valdes-Garcia, E. Sánchez-Sinencio
A time-interleaved pipeline ADC is designed for an 802.11b/Bluetooth dual-mode receiver. Its operation mode can be configured to satisfy the resolution and sampling rate required by each standard. System and circuit level techniques are applied to optimize the ADC power dissipation. An on-line digital calibration scheme is developed to cancel both non-linearity and mismatch in the ADC. The measured dynamic range of the ADC is 60 dB at 44 MS/s and 64 dB at 11 MS/s over the 802.11b and Bluetooth signal bandwidth, respectively. The ADC consumes 14.8 mW in the Bluetooth mode and 20.2 mW in the 802.11b mode.
{"title":"A configurable time-interleaved pipeline ADC for multi-standard wireless receivers","authors":"B. Xia, A. Valdes-Garcia, E. Sánchez-Sinencio","doi":"10.1109/ESSCIR.2004.1356667","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356667","url":null,"abstract":"A time-interleaved pipeline ADC is designed for an 802.11b/Bluetooth dual-mode receiver. Its operation mode can be configured to satisfy the resolution and sampling rate required by each standard. System and circuit level techniques are applied to optimize the ADC power dissipation. An on-line digital calibration scheme is developed to cancel both non-linearity and mismatch in the ADC. The measured dynamic range of the ADC is 60 dB at 44 MS/s and 64 dB at 11 MS/s over the 802.11b and Bluetooth signal bandwidth, respectively. The ADC consumes 14.8 mW in the Bluetooth mode and 20.2 mW in the 802.11b mode.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356643
Dario Giotta, P. Pessl, M. Clara, Wolfgang Klatzer, R. Gaggl
This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.
{"title":"Low-power 14-bit current steering DAC, for ADSL2+/CO applications in 0.13/spl mu/m CMOS","authors":"Dario Giotta, P. Pessl, M. Clara, Wolfgang Klatzer, R. Gaggl","doi":"10.1109/ESSCIR.2004.1356643","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356643","url":null,"abstract":"This work presents a 6-bit fully-differential current steering digital-to-analog converter (DAC), oversampled and 2/sup nd/ order noiseshaped. It is implemented in a 0.13 /spl mu/m standard CMOS process, using only regular threshold voltage devices. The circuit is targeted at ADSL2+ central-office (CO) applications. Clocked at 105 MHz from a low-jitter PLL, it yields a multi-tone power ratio (MTPR) higher than 75 dBc for DMT signals, with an output swing of 1.4 V peak-to-peak. It has an effective resolution of more than 14.5 ENOBs (effective number of bits), consuming only 9 mW from a single 1.5 V supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122668686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356630
F. Bahmani, E. Sánchez-Sinencio
This paper presents a pseudo differential, fully balanced, fully symmetric CMOS operational transconductance amplifier (OTA) with inherent common mode detection which shows a very linear behavior at frequencies around 10.7 MHz. A proposed feedback circuit helps to linearize the output while keeping the output voltage controllable. The OTA linearity behavior is measured in a unity voltage gain configuration which is the worst case for Gm-C filter realizations. Measurement results show an HD3 of -80 dB at 10.7 MHz with 1-Vp-p input signal. Two tone intermodulation measurement results show -70 dB from 1 MHz up to 10 MHz. The OTA is fabricated in the AMI 0.59 /spl mu/m CMOS process and consumes 6 mA current drawn from a /spl plusmn/1.65 V power supply and occupies a small area of 118 /spl mu/m/spl times/160 /spl mu/m.
{"title":"A highly linear pseudo-differential transconductance [CMOS OTA]","authors":"F. Bahmani, E. Sánchez-Sinencio","doi":"10.1109/ESSCIR.2004.1356630","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356630","url":null,"abstract":"This paper presents a pseudo differential, fully balanced, fully symmetric CMOS operational transconductance amplifier (OTA) with inherent common mode detection which shows a very linear behavior at frequencies around 10.7 MHz. A proposed feedback circuit helps to linearize the output while keeping the output voltage controllable. The OTA linearity behavior is measured in a unity voltage gain configuration which is the worst case for Gm-C filter realizations. Measurement results show an HD3 of -80 dB at 10.7 MHz with 1-Vp-p input signal. Two tone intermodulation measurement results show -70 dB from 1 MHz up to 10 MHz. The OTA is fabricated in the AMI 0.59 /spl mu/m CMOS process and consumes 6 mA current drawn from a /spl plusmn/1.65 V power supply and occupies a small area of 118 /spl mu/m/spl times/160 /spl mu/m.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126844686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356698
Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, Jae-Youl Lee, H. Yoo
Two schemes for a charge pump are presented, to reduce output ripple voltage, with high load current drivability. The first is an automatic pumping current control scheme which automatically adjusts the size of the pumping driver to reduce the ripple voltage. The second is an automatic pumping frequency control scheme, which changes the pumping period by controlling a VCO. The prototype chip provides 30-mA load current and delivers a regulated 4.5-V output with a flying capacitor of 330-nF and a clock frequency which automatically varies from 400-kHz to 600-kHz at a 3.3-V supply. The area is 0.25 mm/sup 2/ in a 3.3-V 0.13-/spl mu/m CMOS technology, and measured output ripple voltage is less than 33.8-mV with 2-/spl mu/F load capacitor. Power efficiency is higher than 70%.
{"title":"A small ripple regulated charge pump with automatic pumping control schemes","authors":"Sung-Eun Kim, Seong-Jun Song, Jin-Kyung Kim, Sunyoung Kim, Jae-Youl Lee, H. Yoo","doi":"10.1109/ESSCIR.2004.1356698","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356698","url":null,"abstract":"Two schemes for a charge pump are presented, to reduce output ripple voltage, with high load current drivability. The first is an automatic pumping current control scheme which automatically adjusts the size of the pumping driver to reduce the ripple voltage. The second is an automatic pumping frequency control scheme, which changes the pumping period by controlling a VCO. The prototype chip provides 30-mA load current and delivers a regulated 4.5-V output with a flying capacitor of 330-nF and a clock frequency which automatically varies from 400-kHz to 600-kHz at a 3.3-V supply. The area is 0.25 mm/sup 2/ in a 3.3-V 0.13-/spl mu/m CMOS technology, and measured output ripple voltage is less than 33.8-mV with 2-/spl mu/F load capacitor. Power efficiency is higher than 70%.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126173511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356686
R. Berenguer, E. Hernández, N. Rodriguez, I. Cendoya, Armando Munoz, H. Solar
This paper presents the design of a highly integrated tuner suitable for analog and digital terrestrial TV applications. The tuner system implements an additional up-conversion stage, which allows allocation of any TV channel at IF to the terrestrial TV frequency band (47-860 MHz). This way, applications of conventional tuner systems are expanded. Results based on standard tests have shown that the designed tuner is able to deliver the necessary performance in terms of selectivity, <-35 dB to adjacent channel protection ratio, SNR of 54 dB, in band spurious emissions lower than 60 dBc and /spl Delta/IMD/sub 3/ of 52.8 dB worst case. Finally it has been also demonstrated that with a careful design of the analog components (mixers and oscillators) the restrictive specifications of the TV tuner can be fulfilled by implementing the tuner in a low-cost standard technology (0.8 /spl mu/m SiGe). The total power consumption of the complete tuner is around 390 mA from a 5 V power supply.
{"title":"Design of a highly integrated tuner suitable for analog and digital TV systems","authors":"R. Berenguer, E. Hernández, N. Rodriguez, I. Cendoya, Armando Munoz, H. Solar","doi":"10.1109/ESSCIR.2004.1356686","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356686","url":null,"abstract":"This paper presents the design of a highly integrated tuner suitable for analog and digital terrestrial TV applications. The tuner system implements an additional up-conversion stage, which allows allocation of any TV channel at IF to the terrestrial TV frequency band (47-860 MHz). This way, applications of conventional tuner systems are expanded. Results based on standard tests have shown that the designed tuner is able to deliver the necessary performance in terms of selectivity, <-35 dB to adjacent channel protection ratio, SNR of 54 dB, in band spurious emissions lower than 60 dBc and /spl Delta/IMD/sub 3/ of 52.8 dB worst case. Finally it has been also demonstrated that with a careful design of the analog components (mixers and oscillators) the restrictive specifications of the TV tuner can be fulfilled by implementing the tuner in a low-cost standard technology (0.8 /spl mu/m SiGe). The total power consumption of the complete tuner is around 390 mA from a 5 V power supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124877846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356726
P. Muller, Y. Leblebici, M. Emsley, M. Ünlü
We present a fully differential transimpedance amplifier array with 4 parallel channels achieving an aggregate bandwidth of 10 Gb/s in 0.18 /spl mu/m digital CMOS technology. This array is intended to be bundled with an existing silicon-only photodetector to demonstrate the feasibility of monolithic silicon-based photo-detection in the GHz range. The presented transimpedance amplifier drives a load of up to 0.6 pF and handles photodiode capacitance of up to 1 pF.
{"title":"A 4-channel 2.5Gb/s/channel 66dB/spl Omega/ inductorless transimpedance amplifier [optical receiver applications]","authors":"P. Muller, Y. Leblebici, M. Emsley, M. Ünlü","doi":"10.1109/ESSCIR.2004.1356726","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356726","url":null,"abstract":"We present a fully differential transimpedance amplifier array with 4 parallel channels achieving an aggregate bandwidth of 10 Gb/s in 0.18 /spl mu/m digital CMOS technology. This array is intended to be bundled with an existing silicon-only photodetector to demonstrate the feasibility of monolithic silicon-based photo-detection in the GHz range. The presented transimpedance amplifier drives a load of up to 0.6 pF and handles photodiode capacitance of up to 1 pF.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128581246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356689
Takahide Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, Hirovuki Okada
A 4-Gb/s track and hold (T/H) circuit with a parasitic capacitance canceller is proposed. The parasitic capacitance canceller is connected in parallel with the load capacitance of the T/H circuit and acts as a negative capacitance. The proposed T/H circuit can reduce by 26 % its chip area and by 37 % its power dissipation compared with those of a conventional one, since the cancellation circuit equivalently reduces the load capacitance of the T/H circuit. The proposed T/H circuit is applied to a 4-Gb/s 5-bit flash ADC, fabricated in a 90 nm CMOS process. Thanks to the cancellation circuit, there is not only a reduction of its power consumption but also an extension of its bandwidth. In particular, the bandwidth is extended up to 2 GHz. The measurement results show that the signal to noise and distortion ratio (SINAD) of the ADC, at 2 GHz, is improved to about 27 dB.
{"title":"4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]","authors":"Takahide Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, Hirovuki Okada","doi":"10.1109/ESSCIR.2004.1356689","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356689","url":null,"abstract":"A 4-Gb/s track and hold (T/H) circuit with a parasitic capacitance canceller is proposed. The parasitic capacitance canceller is connected in parallel with the load capacitance of the T/H circuit and acts as a negative capacitance. The proposed T/H circuit can reduce by 26 % its chip area and by 37 % its power dissipation compared with those of a conventional one, since the cancellation circuit equivalently reduces the load capacitance of the T/H circuit. The proposed T/H circuit is applied to a 4-Gb/s 5-bit flash ADC, fabricated in a 90 nm CMOS process. Thanks to the cancellation circuit, there is not only a reduction of its power consumption but also an extension of its bandwidth. In particular, the bandwidth is extended up to 2 GHz. The measurement results show that the signal to noise and distortion ratio (SINAD) of the ADC, at 2 GHz, is improved to about 27 dB.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356656
Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour
This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV
{"title":"A high density, low leakage, 5T SRAM for embedded caches","authors":"Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour","doi":"10.1109/ESSCIR.2004.1356656","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356656","url":null,"abstract":"This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV<Vcc=1.8 V. A 128 Kb memory, based on the 5T SRAM cell, has 23% smaller area, 75% lower bitline leakage, and a read/write performance comparable to a conventional 6T SRAM. The robustness of the design has been validated at worst-case process variations.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356702
Jan F. J. Wouters, J. Sevenhans, S. V. Hoogenbemt, T. Fernandez, Jeff Biggs, C. Das, S. Dupont
This paper presents an inductive load driver. The circuit is realised in a standard low-voltage CMOS process. As the coil free-wheels when the driver is switched off, the circuit clamps the output voltage at 100 mV above the power supply. Hence no high-voltage technology or high-voltage tolerant circuit is required. 73 drivers are integrated in an ASIC, controlling 73 relays for a test access function on a POTS/ADSL splitter filter board. The driver also performs output voltage slope control and has an elegant, effective short-circuit protection.
{"title":"A novel active feedback flyback [inductive load driver]","authors":"Jan F. J. Wouters, J. Sevenhans, S. V. Hoogenbemt, T. Fernandez, Jeff Biggs, C. Das, S. Dupont","doi":"10.1109/ESSCIR.2004.1356702","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356702","url":null,"abstract":"This paper presents an inductive load driver. The circuit is realised in a standard low-voltage CMOS process. As the coil free-wheels when the driver is switched off, the circuit clamps the output voltage at 100 mV above the power supply. Hence no high-voltage technology or high-voltage tolerant circuit is required. 73 drivers are integrated in an ASIC, controlling 73 relays for a test access function on a POTS/ADSL splitter filter board. The driver also performs output voltage slope control and has an elegant, effective short-circuit protection.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"82 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133827740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356649
M. Pertijs, J. Huijsing
When dynamic element matching (DEM) techniques are applied to generate a precision reference for a (single-bit) sigma-delta modulator, intermodulation occurs between the DEM residuals and the bitstream, which increases the in-band quantization noise. This can be prevented by deriving the sequence of DEM steps from the bitstream. This technique has been implemented in a second-order sigma-delta modulator with a dynamic bandgap voltage reference, which was realized in a 0.7 /spl mu/m CMOS process. Measurements show complete elimination of intermodulation products in the signal band, corresponding to an 8 dB reduction in quantization noise compared to conventional cyclic DEM.
{"title":"A sigma-delta modulator with bitstream-controlled dynamic element matching","authors":"M. Pertijs, J. Huijsing","doi":"10.1109/ESSCIR.2004.1356649","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356649","url":null,"abstract":"When dynamic element matching (DEM) techniques are applied to generate a precision reference for a (single-bit) sigma-delta modulator, intermodulation occurs between the DEM residuals and the bitstream, which increases the in-band quantization noise. This can be prevented by deriving the sequence of DEM steps from the bitstream. This technique has been implemented in a second-order sigma-delta modulator with a dynamic bandgap voltage reference, which was realized in a 0.7 /spl mu/m CMOS process. Measurements show complete elimination of intermodulation products in the signal band, corresponding to an 8 dB reduction in quantization noise compared to conventional cyclic DEM.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"7 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128866521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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