Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356667
B. Xia, A. Valdes-Garcia, E. Sánchez-Sinencio
A time-interleaved pipeline ADC is designed for an 802.11b/Bluetooth dual-mode receiver. Its operation mode can be configured to satisfy the resolution and sampling rate required by each standard. System and circuit level techniques are applied to optimize the ADC power dissipation. An on-line digital calibration scheme is developed to cancel both non-linearity and mismatch in the ADC. The measured dynamic range of the ADC is 60 dB at 44 MS/s and 64 dB at 11 MS/s over the 802.11b and Bluetooth signal bandwidth, respectively. The ADC consumes 14.8 mW in the Bluetooth mode and 20.2 mW in the 802.11b mode.
{"title":"A configurable time-interleaved pipeline ADC for multi-standard wireless receivers","authors":"B. Xia, A. Valdes-Garcia, E. Sánchez-Sinencio","doi":"10.1109/ESSCIR.2004.1356667","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356667","url":null,"abstract":"A time-interleaved pipeline ADC is designed for an 802.11b/Bluetooth dual-mode receiver. Its operation mode can be configured to satisfy the resolution and sampling rate required by each standard. System and circuit level techniques are applied to optimize the ADC power dissipation. An on-line digital calibration scheme is developed to cancel both non-linearity and mismatch in the ADC. The measured dynamic range of the ADC is 60 dB at 44 MS/s and 64 dB at 11 MS/s over the 802.11b and Bluetooth signal bandwidth, respectively. The ADC consumes 14.8 mW in the Bluetooth mode and 20.2 mW in the 802.11b mode.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127236925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356656
Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour
This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV
{"title":"A high density, low leakage, 5T SRAM for embedded caches","authors":"Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour","doi":"10.1109/ESSCIR.2004.1356656","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356656","url":null,"abstract":"This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV<Vcc=1.8 V. A 128 Kb memory, based on the 5T SRAM cell, has 23% smaller area, 75% lower bitline leakage, and a read/write performance comparable to a conventional 6T SRAM. The robustness of the design has been validated at worst-case process variations.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356726
P. Muller, Y. Leblebici, M. Emsley, M. Ünlü
We present a fully differential transimpedance amplifier array with 4 parallel channels achieving an aggregate bandwidth of 10 Gb/s in 0.18 /spl mu/m digital CMOS technology. This array is intended to be bundled with an existing silicon-only photodetector to demonstrate the feasibility of monolithic silicon-based photo-detection in the GHz range. The presented transimpedance amplifier drives a load of up to 0.6 pF and handles photodiode capacitance of up to 1 pF.
{"title":"A 4-channel 2.5Gb/s/channel 66dB/spl Omega/ inductorless transimpedance amplifier [optical receiver applications]","authors":"P. Muller, Y. Leblebici, M. Emsley, M. Ünlü","doi":"10.1109/ESSCIR.2004.1356726","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356726","url":null,"abstract":"We present a fully differential transimpedance amplifier array with 4 parallel channels achieving an aggregate bandwidth of 10 Gb/s in 0.18 /spl mu/m digital CMOS technology. This array is intended to be bundled with an existing silicon-only photodetector to demonstrate the feasibility of monolithic silicon-based photo-detection in the GHz range. The presented transimpedance amplifier drives a load of up to 0.6 pF and handles photodiode capacitance of up to 1 pF.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128581246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356661
S. Ouzounov, E. Roza, H. Hegt, G. V. D. Weide, A. Roermund
This work describes a new circuit solution for a linear, CMOS voltage-to-current converter (V-I converter or transconductor). The circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third and the fifth order harmonic distortion components in the transconductor characteristics. The transistor implementation is presented and a prototype VI converter is realised in a digital 0.18 /spl mu/m CMOS technology. The measured SFDR is 75 dB in a frequency band of 10 MHz. The circuit occupies 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.
{"title":"CMOS V-I converter with 75dB SFDR and 360/spl mu/W power consumption","authors":"S. Ouzounov, E. Roza, H. Hegt, G. V. D. Weide, A. Roermund","doi":"10.1109/ESSCIR.2004.1356661","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356661","url":null,"abstract":"This work describes a new circuit solution for a linear, CMOS voltage-to-current converter (V-I converter or transconductor). The circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third and the fifth order harmonic distortion components in the transconductor characteristics. The transistor implementation is presented and a prototype VI converter is realised in a digital 0.18 /spl mu/m CMOS technology. The measured SFDR is 75 dB in a frequency band of 10 MHz. The circuit occupies 0.02 mm/sup 2/ and dissipates 360 /spl mu/W.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116981552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356689
Takahide Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, Hirovuki Okada
A 4-Gb/s track and hold (T/H) circuit with a parasitic capacitance canceller is proposed. The parasitic capacitance canceller is connected in parallel with the load capacitance of the T/H circuit and acts as a negative capacitance. The proposed T/H circuit can reduce by 26 % its chip area and by 37 % its power dissipation compared with those of a conventional one, since the cancellation circuit equivalently reduces the load capacitance of the T/H circuit. The proposed T/H circuit is applied to a 4-Gb/s 5-bit flash ADC, fabricated in a 90 nm CMOS process. Thanks to the cancellation circuit, there is not only a reduction of its power consumption but also an extension of its bandwidth. In particular, the bandwidth is extended up to 2 GHz. The measurement results show that the signal to noise and distortion ratio (SINAD) of the ADC, at 2 GHz, is improved to about 27 dB.
{"title":"4-Gb/s track and hold circuit using parasitic capacitance canceller [flash ADC application]","authors":"Takahide Sato, S. Takagi, N. Fujii, Y. Hashimoto, K. Sakata, Hirovuki Okada","doi":"10.1109/ESSCIR.2004.1356689","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356689","url":null,"abstract":"A 4-Gb/s track and hold (T/H) circuit with a parasitic capacitance canceller is proposed. The parasitic capacitance canceller is connected in parallel with the load capacitance of the T/H circuit and acts as a negative capacitance. The proposed T/H circuit can reduce by 26 % its chip area and by 37 % its power dissipation compared with those of a conventional one, since the cancellation circuit equivalently reduces the load capacitance of the T/H circuit. The proposed T/H circuit is applied to a 4-Gb/s 5-bit flash ADC, fabricated in a 90 nm CMOS process. Thanks to the cancellation circuit, there is not only a reduction of its power consumption but also an extension of its bandwidth. In particular, the bandwidth is extended up to 2 GHz. The measurement results show that the signal to noise and distortion ratio (SINAD) of the ADC, at 2 GHz, is improved to about 27 dB.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129057602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356630
F. Bahmani, E. Sánchez-Sinencio
This paper presents a pseudo differential, fully balanced, fully symmetric CMOS operational transconductance amplifier (OTA) with inherent common mode detection which shows a very linear behavior at frequencies around 10.7 MHz. A proposed feedback circuit helps to linearize the output while keeping the output voltage controllable. The OTA linearity behavior is measured in a unity voltage gain configuration which is the worst case for Gm-C filter realizations. Measurement results show an HD3 of -80 dB at 10.7 MHz with 1-Vp-p input signal. Two tone intermodulation measurement results show -70 dB from 1 MHz up to 10 MHz. The OTA is fabricated in the AMI 0.59 /spl mu/m CMOS process and consumes 6 mA current drawn from a /spl plusmn/1.65 V power supply and occupies a small area of 118 /spl mu/m/spl times/160 /spl mu/m.
{"title":"A highly linear pseudo-differential transconductance [CMOS OTA]","authors":"F. Bahmani, E. Sánchez-Sinencio","doi":"10.1109/ESSCIR.2004.1356630","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356630","url":null,"abstract":"This paper presents a pseudo differential, fully balanced, fully symmetric CMOS operational transconductance amplifier (OTA) with inherent common mode detection which shows a very linear behavior at frequencies around 10.7 MHz. A proposed feedback circuit helps to linearize the output while keeping the output voltage controllable. The OTA linearity behavior is measured in a unity voltage gain configuration which is the worst case for Gm-C filter realizations. Measurement results show an HD3 of -80 dB at 10.7 MHz with 1-Vp-p input signal. Two tone intermodulation measurement results show -70 dB from 1 MHz up to 10 MHz. The OTA is fabricated in the AMI 0.59 /spl mu/m CMOS process and consumes 6 mA current drawn from a /spl plusmn/1.65 V power supply and occupies a small area of 118 /spl mu/m/spl times/160 /spl mu/m.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126844686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356639
S. Chatterjee, Y. Tsividis, P. Kinget
We present a fully differential two-stage Miller op-amp operating from a 0.5 V power supply. The input signal is applied to the bulk nodes of the input devices. A prototype was designed in a standard 0.18 /spl mu/m CMOS process using standard 0.5 V V/sub T/ devices. It has a measured 52 dB DC gain, a 2.5 MHz gain-bandwidth and consumes 110 /spl mu/W.
{"title":"A 0.5-V bulk-input fully differential operational transconductance amplifier","authors":"S. Chatterjee, Y. Tsividis, P. Kinget","doi":"10.1109/ESSCIR.2004.1356639","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356639","url":null,"abstract":"We present a fully differential two-stage Miller op-amp operating from a 0.5 V power supply. The input signal is applied to the bulk nodes of the input devices. A prototype was designed in a standard 0.18 /spl mu/m CMOS process using standard 0.5 V V/sub T/ devices. It has a measured 52 dB DC gain, a 2.5 MHz gain-bandwidth and consumes 110 /spl mu/W.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125604112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356702
Jan F. J. Wouters, J. Sevenhans, S. V. Hoogenbemt, T. Fernandez, Jeff Biggs, C. Das, S. Dupont
This paper presents an inductive load driver. The circuit is realised in a standard low-voltage CMOS process. As the coil free-wheels when the driver is switched off, the circuit clamps the output voltage at 100 mV above the power supply. Hence no high-voltage technology or high-voltage tolerant circuit is required. 73 drivers are integrated in an ASIC, controlling 73 relays for a test access function on a POTS/ADSL splitter filter board. The driver also performs output voltage slope control and has an elegant, effective short-circuit protection.
{"title":"A novel active feedback flyback [inductive load driver]","authors":"Jan F. J. Wouters, J. Sevenhans, S. V. Hoogenbemt, T. Fernandez, Jeff Biggs, C. Das, S. Dupont","doi":"10.1109/ESSCIR.2004.1356702","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356702","url":null,"abstract":"This paper presents an inductive load driver. The circuit is realised in a standard low-voltage CMOS process. As the coil free-wheels when the driver is switched off, the circuit clamps the output voltage at 100 mV above the power supply. Hence no high-voltage technology or high-voltage tolerant circuit is required. 73 drivers are integrated in an ASIC, controlling 73 relays for a test access function on a POTS/ADSL splitter filter board. The driver also performs output voltage slope control and has an elegant, effective short-circuit protection.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"82 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133827740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356680
M. Ogawa, T. Shibata
Computationally very expensive, dynamic programming matching of data sequences has been directly implemented as a fully-parallel-architecture VLSI chip. The chip is organized as a 2D array of delay-encoding logic units, which works as an automatic best-match-sequence search network. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain. As a result, high-speed low-power operation has been established with a small chip area. A prototype chip was designed and fabricated in a 0.18-/spl mu/m CMOS technology, and a typical matching time of 80 ns with a power dissipation of 2 mW under a 1.3 V power supply has been demonstrated.
{"title":"A delay-encoding-logic array processor for dynamic programming matching","authors":"M. Ogawa, T. Shibata","doi":"10.1109/ESSCIR.2004.1356680","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356680","url":null,"abstract":"Computationally very expensive, dynamic programming matching of data sequences has been directly implemented as a fully-parallel-architecture VLSI chip. The chip is organized as a 2D array of delay-encoding logic units, which works as an automatic best-match-sequence search network. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain. As a result, high-speed low-power operation has been established with a small chip area. A prototype chip was designed and fabricated in a 0.18-/spl mu/m CMOS technology, and a typical matching time of 80 ns with a power dissipation of 2 mW under a 1.3 V power supply has been demonstrated.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117307650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356700
G. Ono, M. Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, T. Kawahara
A temperature referenced supply voltage and forward-body-bias (FBB) control architecture for ubiquitous computing processors is proposed. The architecture can minimize power consumption at all temperatures by using our discovered FBB self-feedback effect. The effect is that low temperature forces the FBB-controlled LSI to increase its performance. The TSFC reduced power consumption by 28% without any performance degradation compared with the conventional FBB technique. We also found and analyzed the dual parasitic bipolar modes in the FBB system by evaluating a test chip fabricated in 0.13-/spl mu/m CMOS technology. Moreover, the influence of supply and substrate wire resistances in the FBB system was found to be not significant. The TSFC architecture is effective for achieving ubiquitous computing LSIs.
提出了一种基于温度的普适计算处理器电源电压和正向偏置(FBB)控制架构。利用我们发现的FBB自反馈效应，该架构可以在所有温度下最大限度地降低功耗。其结果是，低温迫使fbb控制的LSI提高其性能。与传统的FBB技术相比，TSFC在没有任何性能下降的情况下降低了28%的功耗。我们还通过评估0.13-/spl μ m CMOS工艺制作的测试芯片，发现并分析了FBB系统中的双寄生双极模式。此外，在FBB系统中，电源和衬底导线电阻的影响并不显著。TSFC架构是实现泛在计算lsi的有效方法。
{"title":"Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]","authors":"G. Ono, M. Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, T. Kawahara","doi":"10.1109/ESSCIR.2004.1356700","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356700","url":null,"abstract":"A temperature referenced supply voltage and forward-body-bias (FBB) control architecture for ubiquitous computing processors is proposed. The architecture can minimize power consumption at all temperatures by using our discovered FBB self-feedback effect. The effect is that low temperature forces the FBB-controlled LSI to increase its performance. The TSFC reduced power consumption by 28% without any performance degradation compared with the conventional FBB technique. We also found and analyzed the dual parasitic bipolar modes in the FBB system by evaluating a test chip fabricated in 0.13-/spl mu/m CMOS technology. Moreover, the influence of supply and substrate wire resistances in the FBB system was found to be not significant. The TSFC architecture is effective for achieving ubiquitous computing LSIs.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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