Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356615
M. Vertregt, P. Scholtens
Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.
{"title":"Assessment of the merits of CMOS technology scaling for analog circuit design","authors":"M. Vertregt, P. Scholtens","doi":"10.1109/ESSCIR.2004.1356615","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356615","url":null,"abstract":"Key device parameters such as drain current, transconductance, current factor, capacitance, etc. are linked to typical analog circuit level performance criteria, as a function of the CMOS technology node. Subsequently, speed and power implications for an analog-to-digital converter building block are estimated. Significant power efficiency improvements are predicted as a result of scaling to deep sub-micron technology nodes.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128748848","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356715
G. D. Graaf, R. Wolffenbuttel
This work presents a general concept for the linearisation of impedance bridges with circuit components changing in only one polarity. The method can be applied for DC or AC bridges using resistive, capacitive or inductive circuit elements. The linearisation can conveniently be integrated with the readout circuit resulting in a highly linear sensor readout. A feedback-loop using a transadmittance amplifier properly designed and matched to the nominal value of the bridge components reduces non-linearity from 9% to 0.4% over /spl plusmn/20% of bridge imbalance. In addition to the linearization of the bridge transfer function itself the method can be applied for the linearization of a range of transducers with a hyperbolic transfer function.
{"title":"Circuit for readout and linearisation of sensor bridges","authors":"G. D. Graaf, R. Wolffenbuttel","doi":"10.1109/ESSCIR.2004.1356715","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356715","url":null,"abstract":"This work presents a general concept for the linearisation of impedance bridges with circuit components changing in only one polarity. The method can be applied for DC or AC bridges using resistive, capacitive or inductive circuit elements. The linearisation can conveniently be integrated with the readout circuit resulting in a highly linear sensor readout. A feedback-loop using a transadmittance amplifier properly designed and matched to the nominal value of the bridge components reduces non-linearity from 9% to 0.4% over /spl plusmn/20% of bridge imbalance. In addition to the linearization of the bridge transfer function itself the method can be applied for the linearization of a range of transducers with a hyperbolic transfer function.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"47 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121005226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356721
Peter Caputa, M. Anders, C. Svensson, R. Krishnamurthy, S. Borkar
This paper describes a 3.3 GHz low-swing single-ended L1 cache bus in 1.2 V, 90 nm dual-Vt CMOS technology. Accurate RLCK-modeling of the interconnect topology has been conducted using a 3D field solver. A signal-swing reduction of 25% and efficient sense amplifier-based receiver are employed to reach 3.3 GHz, 2.24 mW operation at 1.2 V and 110/spl deg/C. 70% energy and 54% peak-current reduction is achieved over an optimized high-performance conventional dynamic cache bus scheme. The design is fully functional up to 6.1 GHz operating-frequency with a 54% eye opening.
{"title":"A low-swing single-ended L1 cache bus technique for sub-90nm technologies","authors":"Peter Caputa, M. Anders, C. Svensson, R. Krishnamurthy, S. Borkar","doi":"10.1109/ESSCIR.2004.1356721","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356721","url":null,"abstract":"This paper describes a 3.3 GHz low-swing single-ended L1 cache bus in 1.2 V, 90 nm dual-Vt CMOS technology. Accurate RLCK-modeling of the interconnect topology has been conducted using a 3D field solver. A signal-swing reduction of 25% and efficient sense amplifier-based receiver are employed to reach 3.3 GHz, 2.24 mW operation at 1.2 V and 110/spl deg/C. 70% energy and 54% peak-current reduction is achieved over an optimized high-performance conventional dynamic cache bus scheme. The design is fully functional up to 6.1 GHz operating-frequency with a 54% eye opening.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115268969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356665
D. Muthers, R. Tielert
A 10 bit 10 MS/s cyclic analog-to-digital converter has been implemented using 0.18 /spl mu/m CMOS technology. The converter was optimized with respect to area and power consumption in order to allow the integration of a multichannel array within a complex logic chip. The power consumption is 9.5 mW. The area per A/D-converter cell is 0.11 mm/sup 2/. The proposed cyclic converter architecture together with some implementation aspects, like working with one amplifier only and reusing the signal capacitors for the common-mode feedback helped to meet the requirements of the application.
{"title":"A 0.11mm/sup 2/ low-power A/D-converter cell for 10b 10MS/s operation","authors":"D. Muthers, R. Tielert","doi":"10.1109/ESSCIR.2004.1356665","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356665","url":null,"abstract":"A 10 bit 10 MS/s cyclic analog-to-digital converter has been implemented using 0.18 /spl mu/m CMOS technology. The converter was optimized with respect to area and power consumption in order to allow the integration of a multichannel array within a complex logic chip. The power consumption is 9.5 mW. The area per A/D-converter cell is 0.11 mm/sup 2/. The proposed cyclic converter architecture together with some implementation aspects, like working with one amplifier only and reusing the signal capacitors for the common-mode feedback helped to meet the requirements of the application.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124586962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356707
D. Stoppa, L. Viarani, A. Simoni, L. Gonzo, M. Malfatti, G. Pedretti
This paper describes the design and characterization of a 16/spl times/16-pixel image sensor, fabricated in a 0.35 /spl mu/m, 3.3 V CMOS technology for real time three dimensional measurements based on multiple-pulse indirect time-of-flight technique. Owing to an innovative fully differential pixel (FDP) architecture, which allows for the detection of very short and low intensity light pulses, the sensor array provides a range map from 2 m to 9 m with a precision of /spl plusmn/4.0% at 2 m and /spl plusmn/1.7% at 9 m. The pixel power consumption is 100 /spl mu/W, whereas the overall power consumption of the chip is 47 mW in real time operation (30 fps).
{"title":"A 16/spl times/16-pixel range-finding CMOS image sensor","authors":"D. Stoppa, L. Viarani, A. Simoni, L. Gonzo, M. Malfatti, G. Pedretti","doi":"10.1109/ESSCIR.2004.1356707","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356707","url":null,"abstract":"This paper describes the design and characterization of a 16/spl times/16-pixel image sensor, fabricated in a 0.35 /spl mu/m, 3.3 V CMOS technology for real time three dimensional measurements based on multiple-pulse indirect time-of-flight technique. Owing to an innovative fully differential pixel (FDP) architecture, which allows for the detection of very short and low intensity light pulses, the sensor array provides a range map from 2 m to 9 m with a precision of /spl plusmn/4.0% at 2 m and /spl plusmn/1.7% at 9 m. The pixel power consumption is 100 /spl mu/W, whereas the overall power consumption of the chip is 47 mW in real time operation (30 fps).","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"273 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132895205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356703
H. Hara, Mikio Sakurai, M. Miyasaka, S. Tam, S. Inoue, T. Shimoda
We have developed a low-temperature polycrystalline silicon thin film transistor (LTPS-TFT) fingerprint sensor (FPS) based on a newly clarified detection principle and a unique driving scheme. We have also integrated a comparator circuit onto a glass substrate for the first time. The circuit recognizes ridges and valleys in a fingerprint. Using this system, we have succeeded in taking fine fingerprint images at 4 V operation. This fingerprint sensor is suitable for mobile applications that require thin devices that are low cost and low power.
{"title":"Low temperature polycrystalline silicon TFT fingerprint sensor with integrated comparator circuit","authors":"H. Hara, Mikio Sakurai, M. Miyasaka, S. Tam, S. Inoue, T. Shimoda","doi":"10.1109/ESSCIR.2004.1356703","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356703","url":null,"abstract":"We have developed a low-temperature polycrystalline silicon thin film transistor (LTPS-TFT) fingerprint sensor (FPS) based on a newly clarified detection principle and a unique driving scheme. We have also integrated a comparator circuit onto a glass substrate for the first time. The circuit recognizes ridges and valleys in a fingerprint. Using this system, we have succeeded in taking fine fingerprint images at 4 V operation. This fingerprint sensor is suitable for mobile applications that require thin devices that are low cost and low power.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"244 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132244357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356682
Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho
A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.
{"title":"Dual-level LVDS technique for reducing the data transmission lines by half of LCD driver IC","authors":"Doo-Hwan Kim, Sung-Hyun Yang, Kyoung-Rok Cho","doi":"10.1109/ESSCIR.2004.1356682","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356682","url":null,"abstract":"A dual low-voltage differential signalling (DLVDS) circuit has been proposed, aimed at reducing the number of transmission lines for an LCD driver IC. In the proposed circuit, we apply a pair of primitive data to the DLVDS circuit as inputs. The inputs act as complementary signals. Then, a transmitter converts the two inputs to two kinds of fully differential level signals. Thus, only two transmission lines are required to transfer two primitive inputs while keeping the LVDS feature. The receiver recovers the original input data through a level decoding circuit. We designed the proposed circuit using 0.25 /spl mu/m CMOS technology. As a result, the circuit shows 1-Gbps/2-line data rate and 35 mW power consumption at 2.5 V supply voltage.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116097978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356700
G. Ono, M. Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, T. Kawahara
A temperature referenced supply voltage and forward-body-bias (FBB) control architecture for ubiquitous computing processors is proposed. The architecture can minimize power consumption at all temperatures by using our discovered FBB self-feedback effect. The effect is that low temperature forces the FBB-controlled LSI to increase its performance. The TSFC reduced power consumption by 28% without any performance degradation compared with the conventional FBB technique. We also found and analyzed the dual parasitic bipolar modes in the FBB system by evaluating a test chip fabricated in 0.13-/spl mu/m CMOS technology. Moreover, the influence of supply and substrate wire resistances in the FBB system was found to be not significant. The TSFC architecture is effective for achieving ubiquitous computing LSIs.
提出了一种基于温度的普适计算处理器电源电压和正向偏置(FBB)控制架构。利用我们发现的FBB自反馈效应，该架构可以在所有温度下最大限度地降低功耗。其结果是，低温迫使fbb控制的LSI提高其性能。与传统的FBB技术相比，TSFC在没有任何性能下降的情况下降低了28%的功耗。我们还通过评估0.13-/spl μ m CMOS工艺制作的测试芯片，发现并分析了FBB系统中的双寄生双极模式。此外，在FBB系统中，电源和衬底导线电阻的影响并不显著。TSFC架构是实现泛在计算lsi的有效方法。
{"title":"Temperature referenced supply voltage and forward-body-bias control (TSFC) architecture for minimum power consumption [ubiquitous computing processors]","authors":"G. Ono, M. Miyazaki, Hidetoshi Tanaka, Nono Ohkubo, T. Kawahara","doi":"10.1109/ESSCIR.2004.1356700","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356700","url":null,"abstract":"A temperature referenced supply voltage and forward-body-bias (FBB) control architecture for ubiquitous computing processors is proposed. The architecture can minimize power consumption at all temperatures by using our discovered FBB self-feedback effect. The effect is that low temperature forces the FBB-controlled LSI to increase its performance. The TSFC reduced power consumption by 28% without any performance degradation compared with the conventional FBB technique. We also found and analyzed the dual parasitic bipolar modes in the FBB system by evaluating a test chip fabricated in 0.13-/spl mu/m CMOS technology. Moreover, the influence of supply and substrate wire resistances in the FBB system was found to be not significant. The TSFC architecture is effective for achieving ubiquitous computing LSIs.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126044026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356697
C. Jeong, C. Yoo, Jae-Jin Lee, J. Kih
A digital delay locked loop (DLL) for 1.2 Gb/s/pin double data rate (DDR) SDRAM is described, which incorporates duty cycle correction (DCC). The DCC locking information is also stored as a digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL, implemented in a 0.35 /spl mu/m CMOS technology, provides an output clock with 64 ps peak-to-peak jitter and the accuracy of the DCC is /spl plusmn/0.7% for /spl plusmn/10% input duty error from 250 MHz to 600 MHz clock frequency. The digital DLL, excluding I/O buffers, dissipates 10 mW from a 2.5 V power supply.
{"title":"Digital delay locked loop with open-loop digital duty cycle corrector for 1.2Gb/s/pin double data rate SDRAM","authors":"C. Jeong, C. Yoo, Jae-Jin Lee, J. Kih","doi":"10.1109/ESSCIR.2004.1356697","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356697","url":null,"abstract":"A digital delay locked loop (DLL) for 1.2 Gb/s/pin double data rate (DDR) SDRAM is described, which incorporates duty cycle correction (DCC). The DCC locking information is also stored as a digital code for fast wake-up from power-down mode and DCC control is done in an open-loop, enabling fast locking of the DCC loop with minimum additional power consumption. The DLL, implemented in a 0.35 /spl mu/m CMOS technology, provides an output clock with 64 ps peak-to-peak jitter and the accuracy of the DCC is /spl plusmn/0.7% for /spl plusmn/10% input duty error from 250 MHz to 600 MHz clock frequency. The digital DLL, excluding I/O buffers, dissipates 10 mW from a 2.5 V power supply.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114888593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-11-15DOI: 10.1109/ESSCIR.2004.1356648
M. Schimper, Lukas Dörrer, E. Riccio, G. Panov
A continuous-time 4th-order multi-bit /spl Sigma//spl Delta/-modulator for GSM/EDGE is presented. By introduction of a direct feed-forward path from the input to the quantiser, high immunity to adjacent channel interferers is achieved. The dynamic range is 90 dB (>14-bit) over a 240 kHz signal bandwidth. Accurate modelling allows optimisation of excess loop delay, thus yielding a very low power consumption of 3 mW at 1.25 V supply voltage. The modulator is clocked at 26 MHz (oversampling ratio=54). It occupies 0.5 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology.
{"title":"A 3mW continuous-time /spl Sigma//spl Delta/-modulator for EDGE/GSM with high adjacent channel tolerance","authors":"M. Schimper, Lukas Dörrer, E. Riccio, G. Panov","doi":"10.1109/ESSCIR.2004.1356648","DOIUrl":"https://doi.org/10.1109/ESSCIR.2004.1356648","url":null,"abstract":"A continuous-time 4th-order multi-bit /spl Sigma//spl Delta/-modulator for GSM/EDGE is presented. By introduction of a direct feed-forward path from the input to the quantiser, high immunity to adjacent channel interferers is achieved. The dynamic range is 90 dB (>14-bit) over a 240 kHz signal bandwidth. Accurate modelling allows optimisation of excess loop delay, thus yielding a very low power consumption of 3 mW at 1.25 V supply voltage. The modulator is clocked at 26 MHz (oversampling ratio=54). It occupies 0.5 mm/sup 2/ in a 0.13 /spl mu/m CMOS technology.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130429262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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