Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255678
Zeenat Hameed, S. Hashemi, C. Træholt
Battery energy storage systems (BESSs) have gained potential recognition for the grid services they can offer to power systems. Choosing an appropriate BESS location plays a key role in maximizing benefits from those services. This paper aims at analyzing the significance of site selection for placement of BESS in a power grid by providing a techno-economic evaluation with respect to specific grid services it can deliver, and benefits that can be extracted from those services in the form of revenue streams. The focus of the previous studies extended in this direction has been limited to the optimization techniques and software tools being used for BESS siting. However, questions around the benefits that stakeholders can derive from BESSs located at different levels of power network still remain unanswered. This paper handles those questions by drawing a link between technical considerations essential for BESS placement and their economic evaluations.
{"title":"Site Selection Criteria for Battery Energy Storage in Power Systems","authors":"Zeenat Hameed, S. Hashemi, C. Træholt","doi":"10.1109/CCECE47787.2020.9255678","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255678","url":null,"abstract":"Battery energy storage systems (BESSs) have gained potential recognition for the grid services they can offer to power systems. Choosing an appropriate BESS location plays a key role in maximizing benefits from those services. This paper aims at analyzing the significance of site selection for placement of BESS in a power grid by providing a techno-economic evaluation with respect to specific grid services it can deliver, and benefits that can be extracted from those services in the form of revenue streams. The focus of the previous studies extended in this direction has been limited to the optimization techniques and software tools being used for BESS siting. However, questions around the benefits that stakeholders can derive from BESSs located at different levels of power network still remain unanswered. This paper handles those questions by drawing a link between technical considerations essential for BESS placement and their economic evaluations.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134491390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255792
Wissal Attaoui, Essaid Sabir, H. Elbiaze, M. Sadik
With the emergence of network function virtualization (NFV) and Software-Defined Networking (SDN) technologies, virtual network functions (VNF) can be interconnected to deliver different mobile services in 5G communication networks. Our primary purpose is to find the optimal VNF placement reducing resource consumption while providing specific latency and throughput for slicing services. We consider VNFs as M/M/1/C queues chained together to serve customer requests. The problem relies on finding an efficient orchestration and placement of VNFs. In this context, we propose a decision algorithm based two-procedures, the first one, named orchestration phase, aims to manage the reuse of VNFs having the same required functions through a dynamic logit method, and the second one is related to the new placement of VNFs. In this paper, we focus on a simple scenario of delivering video streaming service traversing a standard chain of four VNFs. Simulation results prove the performance of our proposed algorithm in terms of End-to-End delay and dropping probability compared to greedy and affinity algorithms.
{"title":"Combined Latency-Aware and Resource-Effective Virtual Network Function Placement","authors":"Wissal Attaoui, Essaid Sabir, H. Elbiaze, M. Sadik","doi":"10.1109/CCECE47787.2020.9255792","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255792","url":null,"abstract":"With the emergence of network function virtualization (NFV) and Software-Defined Networking (SDN) technologies, virtual network functions (VNF) can be interconnected to deliver different mobile services in 5G communication networks. Our primary purpose is to find the optimal VNF placement reducing resource consumption while providing specific latency and throughput for slicing services. We consider VNFs as M/M/1/C queues chained together to serve customer requests. The problem relies on finding an efficient orchestration and placement of VNFs. In this context, we propose a decision algorithm based two-procedures, the first one, named orchestration phase, aims to manage the reuse of VNFs having the same required functions through a dynamic logit method, and the second one is related to the new placement of VNFs. In this paper, we focus on a simple scenario of delivering video streaming service traversing a standard chain of four VNFs. Simulation results prove the performance of our proposed algorithm in terms of End-to-End delay and dropping probability compared to greedy and affinity algorithms.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134316446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255813
Diego Felix de Almeida, Jason Yen, Michal Aibin
With an increasing demand for web content delivery, it is necessary to optimize the CAPEX and OPEX costs of the Content Delivery Networks. Ideally, all web content to be requested should be stored in local cache nodes at all times. However, the content demand varies across space and time. In this paper, we propose a Content Delivery Network model that allows us to choose the best trade-off between costs and cache hit ratio.
{"title":"Content Delivery Networks - Q-Learning Approach for Optimization of the Network Cost and the Cache Hit Ratio","authors":"Diego Felix de Almeida, Jason Yen, Michal Aibin","doi":"10.1109/CCECE47787.2020.9255813","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255813","url":null,"abstract":"With an increasing demand for web content delivery, it is necessary to optimize the CAPEX and OPEX costs of the Content Delivery Networks. Ideally, all web content to be requested should be stored in local cache nodes at all times. However, the content demand varies across space and time. In this paper, we propose a Content Delivery Network model that allows us to choose the best trade-off between costs and cache hit ratio.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132986263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255807
Ali R. Al-Roomi, M. El-Hawary
Real transmission lines are translated into mathematical models using either the lumped parameter approach or the distributed parameter approach. The first one is used for short- and medium-length transmission lines, while the other is used for long-length transmission lines where the accuracy and precision are required. For medium transmission lines, the lumped parameter approach can be applied using one of four popular circuit representations known as gamma ($Gamma$), opposite-gamma ┐, tee (T), and pi $Pi$. This study presents a new circuit representation called em (M). This model is inspired by the sagging phenomenon where, at the sag point, the distributed series impedance of the $Pi$-model is divided into two equal/unequal parts and the distributed shunt admittance at the center is bigger than that at both ends. For some numerical experiments, the M-model shows a stunning performance in estimating transmission line readings. It wins in most cases and, for the few remaining cases, the M-model shows very competitive results.
采用集总参数法或分布参数法将实际输电线路转换成数学模型。第一种用于中短长度输电线路，另一种用于对精度和精度有要求的长长度输电线路。对于中等传输线，集总参数方法可以使用四种流行的电路表示形式之一，即gamma ($Gamma$)，对向gamma -， tee (T)和pi $Pi$。本文提出了一种新的电路表示em (M)，该模型的灵感来自于凹陷现象，在凹陷点处，$Pi$ -模型的分布串联阻抗分为两个相等/不相等的部分，中心的分布并联导纳大于两端。在一些数值实验中，m模型在估计传输线读数方面表现出惊人的性能。它在大多数情况下获胜，而在剩下的少数情况下，m模型显示出非常有竞争力的结果。
{"title":"M-Model: A New Precise Medium-Length Transmission Line Model","authors":"Ali R. Al-Roomi, M. El-Hawary","doi":"10.1109/CCECE47787.2020.9255807","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255807","url":null,"abstract":"Real transmission lines are translated into mathematical models using either the lumped parameter approach or the distributed parameter approach. The first one is used for short- and medium-length transmission lines, while the other is used for long-length transmission lines where the accuracy and precision are required. For medium transmission lines, the lumped parameter approach can be applied using one of four popular circuit representations known as gamma ($Gamma$), opposite-gamma ┐, tee (T), and pi $Pi$. This study presents a new circuit representation called em (M). This model is inspired by the sagging phenomenon where, at the sag point, the distributed series impedance of the $Pi$-model is divided into two equal/unequal parts and the distributed shunt admittance at the center is bigger than that at both ends. For some numerical experiments, the M-model shows a stunning performance in estimating transmission line readings. It wins in most cases and, for the few remaining cases, the M-model shows very competitive results.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129498234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255728
Abdullah Hasan, K. Abugharbieh, Muntaser Al-Mousely, Waseem Al-Akel
This work presents a novel design of a sample and hold circuit which operates at 25GS/s. The circuit consists of three main stages. The first stage is the input buffer which provides a high frequency boost using an active-load inductor instead of the commonly used passive inductor. The second stage is the switch stage which is responsible for sampling the input signal with high linearity. Finally, the output buffer is used to recover the high frequency component of the signal. The circuit is designed in 28nm CMOS technology used in digital circuits and uses a 1V supply. It is simulated using a 3GHz input signal that has a differential peak to peak voltage amplitude of 0.4V and a 25GHz sampling clock signal. The proposed circuit consumes a total power of 2.47mW and occupies an area of 0.005mm2. The achieved Effective Number Of Bits (ENOB) is 5 bits and the Total Harmonic Distortion, THD, is −40dB. The sampled signal has a droop rate of 0.35mV/psec.
{"title":"A Low-Power 25GS/Sec Sample and Hold Circuit with Active-Load Inductors","authors":"Abdullah Hasan, K. Abugharbieh, Muntaser Al-Mousely, Waseem Al-Akel","doi":"10.1109/CCECE47787.2020.9255728","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255728","url":null,"abstract":"This work presents a novel design of a sample and hold circuit which operates at 25GS/s. The circuit consists of three main stages. The first stage is the input buffer which provides a high frequency boost using an active-load inductor instead of the commonly used passive inductor. The second stage is the switch stage which is responsible for sampling the input signal with high linearity. Finally, the output buffer is used to recover the high frequency component of the signal. The circuit is designed in 28nm CMOS technology used in digital circuits and uses a 1V supply. It is simulated using a 3GHz input signal that has a differential peak to peak voltage amplitude of 0.4V and a 25GHz sampling clock signal. The proposed circuit consumes a total power of 2.47mW and occupies an area of 0.005mm2. The achieved Effective Number Of Bits (ENOB) is 5 bits and the Total Harmonic Distortion, THD, is −40dB. The sampled signal has a droop rate of 0.35mV/psec.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132435201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255689
Abbas Panahi, P. Ghasemi, S. Magierowski, E. Ghafar-Zadeh
This paper introduces a new MEMS micro cantilever chip for mass flow rate and flow velocity measurement in a harsh environment where combustible gas flows are the working fluid. In such a condition, using thermal flow sensors is hazardous and may threaten a staggering amount of investment and human lives by igniting the gas flow which might lead to an explosion. To overcome these drawback mechanical sensors are more desirables for such environments. Here we have designed a MEMS chip consist of 74 polysilicon micro cantilevers that are operating based on a capacitive detection mode. There are micro cantilevers with 50, 100, 250 and 400 µm in length and same thickness and wideness, 2µm and 50µm, respectively. This sensor is capable of measuring moderate flows up to 200 m/s in a 10 cm diameter pipes based on the current design for bypass. According to experimental results, the sensor output capacitance varied from 3.3445 pF to 3.350 pF for a range of flow between 0 to 30 m/s. We have shown that MEMS flow sensor can meet large size flow measurements in the industry.
{"title":"A New Capacitive MEMS Flow Sensor for Industrial Gas Transport Monitoring Applications","authors":"Abbas Panahi, P. Ghasemi, S. Magierowski, E. Ghafar-Zadeh","doi":"10.1109/CCECE47787.2020.9255689","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255689","url":null,"abstract":"This paper introduces a new MEMS micro cantilever chip for mass flow rate and flow velocity measurement in a harsh environment where combustible gas flows are the working fluid. In such a condition, using thermal flow sensors is hazardous and may threaten a staggering amount of investment and human lives by igniting the gas flow which might lead to an explosion. To overcome these drawback mechanical sensors are more desirables for such environments. Here we have designed a MEMS chip consist of 74 polysilicon micro cantilevers that are operating based on a capacitive detection mode. There are micro cantilevers with 50, 100, 250 and 400 µm in length and same thickness and wideness, 2µm and 50µm, respectively. This sensor is capable of measuring moderate flows up to 200 m/s in a 10 cm diameter pipes based on the current design for bypass. According to experimental results, the sensor output capacitance varied from 3.3445 pF to 3.350 pF for a range of flow between 0 to 30 m/s. We have shown that MEMS flow sensor can meet large size flow measurements in the industry.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"13 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114098721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255748
Furat Al-Obaidy, A. Asad, F. Mohammadi
In this work, a new energy-efficient reconfigurable cache architecture for chip multiprocessors is proposed. We formulate the reconfiguration problem based on using a machine learning technique. The proposed approach predicts the latency of the last-level cache in the next interval and then detects the type of it at runtime. This work provides a new approach that uses a neural network algorithm to reconfigure cache components. Experimental results show that the proposed design improves energy consumption of a three-dimensional chip multiprocessor with 16 cores by about 45% and performance by about 13% in compared to non-reconfigurable baselines.
{"title":"Learning-Based Reconfigurable Cache for Heterogeneous Chip Multiprocessors","authors":"Furat Al-Obaidy, A. Asad, F. Mohammadi","doi":"10.1109/CCECE47787.2020.9255748","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255748","url":null,"abstract":"In this work, a new energy-efficient reconfigurable cache architecture for chip multiprocessors is proposed. We formulate the reconfiguration problem based on using a machine learning technique. The proposed approach predicts the latency of the last-level cache in the next interval and then detects the type of it at runtime. This work provides a new approach that uses a neural network algorithm to reconfigure cache components. Experimental results show that the proposed design improves energy consumption of a three-dimensional chip multiprocessor with 16 cores by about 45% and performance by about 13% in compared to non-reconfigurable baselines.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124281073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255794
Ali R. Al-Roomi, M. El-Hawary
Nowadays, many studies have been presented in the literature to solve various optimal relay coordination (ORC) problems. These highly constrained nonlinear nonconvex optimization problems are commonly solved using evolutionary algorithms (EAs). For online applications, where the processing speed is very crucial, some studies suggest using different types of linear programming (LP), including simplex and interior-point methods, while others suggest hybridizing both EAs and LPs. For these approaches, the ANSI/IEEE and IEC/BS standard models used to calculate the operating times of overcurrent relays (OCRs) are linearized by just fixing their plug settings (PS) and varying time multiplier settings (TMS). This study presents another way to linearize these models by doing the opposite where $TMS$ are fixed and $PS$ are varied for both standard models. These linearized models can be used to effectively tune the objective functions of ORC problems to achieve both performance criteria; the solution quality and the processing speed.
{"title":"Mathematical Schemes to Linearize Operating Times of Overcurrent Relays by Sequentially Fixing Plug Settings and Time Multiplier Settings","authors":"Ali R. Al-Roomi, M. El-Hawary","doi":"10.1109/CCECE47787.2020.9255794","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255794","url":null,"abstract":"Nowadays, many studies have been presented in the literature to solve various optimal relay coordination (ORC) problems. These highly constrained nonlinear nonconvex optimization problems are commonly solved using evolutionary algorithms (EAs). For online applications, where the processing speed is very crucial, some studies suggest using different types of linear programming (LP), including simplex and interior-point methods, while others suggest hybridizing both EAs and LPs. For these approaches, the ANSI/IEEE and IEC/BS standard models used to calculate the operating times of overcurrent relays (OCRs) are linearized by just fixing their plug settings (PS) and varying time multiplier settings (TMS). This study presents another way to linearize these models by doing the opposite where $TMS$ are fixed and $PS$ are varied for both standard models. These linearized models can be used to effectively tune the objective functions of ORC problems to achieve both performance criteria; the solution quality and the processing speed.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255755
Y. Seyedi, H. Karimi, S. Grijalva, B. Sansò
Networked protection systems use information, communication and computation technologies to collect and process sensor data from spatially distributed sensors, and launch protective and control actions by sending commands to local devices. Such protection systems are also capable of supporting specialized tasks including asset control and backup protection in case of traditional relaying failures. This paper explains the structure and the fundamental elements of the networked protection systems in distribution systems and microgrids. The overall system is divided into three subsystems which are interconnected by communication systems. Different types of cyber-attacks on the subsystems and their impacts are discussed from the vantage point of protection. False and delayed tripping, non-detection, cascading failures, and unstable operation of distributed energy resources (DERs) are discussed as the critical issues that can be related to cyber-attacks.
{"title":"Elements of Networked Protection Systems for Distribution Networks and Microgrids: A Cyber-Security Perspective","authors":"Y. Seyedi, H. Karimi, S. Grijalva, B. Sansò","doi":"10.1109/CCECE47787.2020.9255755","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255755","url":null,"abstract":"Networked protection systems use information, communication and computation technologies to collect and process sensor data from spatially distributed sensors, and launch protective and control actions by sending commands to local devices. Such protection systems are also capable of supporting specialized tasks including asset control and backup protection in case of traditional relaying failures. This paper explains the structure and the fundamental elements of the networked protection systems in distribution systems and microgrids. The overall system is divided into three subsystems which are interconnected by communication systems. Different types of cyber-attacks on the subsystems and their impacts are discussed from the vantage point of protection. False and delayed tripping, non-detection, cascading failures, and unstable operation of distributed energy resources (DERs) are discussed as the critical issues that can be related to cyber-attacks.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122628154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-30DOI: 10.1109/CCECE47787.2020.9255679
Xingwen Li, E. Rogers, Seyedfakhreddin Nabavi, Lihong Zhang
In this paper, the efficiency of a conventional cross-coupled gate CMOS bridge rectifier used in MEMS (microelectromechanical system) piezoelectric energy harvesters is investigated. The MOSFET threshold voltage is varied between 10 mV and 800 mV to evaluate the performance of the circuit for various threshold voltage levels. The circuit is simulated using the 130 nm CMOS technology process for each MOSFET to generate performance metrics for the rectifier. The results are evaluated for optimal load resistance, and it is confirmed that a lower threshold voltage results in significant improvements to the efficiency of the rectifier at lower input voltage amplitudes, with up to 62% at 0.5 V input amplitude when a smoothing capacitor is placed across the load.
{"title":"Effect of Varying Threshold Voltage on Efficiency of CMOS Rectifiers for Piezoelectric Energy Harvesting Applications","authors":"Xingwen Li, E. Rogers, Seyedfakhreddin Nabavi, Lihong Zhang","doi":"10.1109/CCECE47787.2020.9255679","DOIUrl":"https://doi.org/10.1109/CCECE47787.2020.9255679","url":null,"abstract":"In this paper, the efficiency of a conventional cross-coupled gate CMOS bridge rectifier used in MEMS (microelectromechanical system) piezoelectric energy harvesters is investigated. The MOSFET threshold voltage is varied between 10 mV and 800 mV to evaluate the performance of the circuit for various threshold voltage levels. The circuit is simulated using the 130 nm CMOS technology process for each MOSFET to generate performance metrics for the rectifier. The results are evaluated for optimal load resistance, and it is confirmed that a lower threshold voltage results in significant improvements to the efficiency of the rectifier at lower input voltage amplitudes, with up to 62% at 0.5 V input amplitude when a smoothing capacitor is placed across the load.","PeriodicalId":296506,"journal":{"name":"2020 IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124771178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：