Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1670524690
M. Hosseinpour, Armineh Dastgiri
Abstract— In this paper, a non-isolated quadratic and buck-boost converter based on the Zeta structure is proposed, and its operating principle and analysis of its steady-state is discussed. Also, the parameter design is presented, and on-idealities are considered in the power circuit to analyze - in detail - the real voltage gain and efficiency of the proposed converter. Moreover, a simulation prototype is implemented to validate the theoretical analysis, and a comparison of the proposed converter with other similar topologies and small-signal models is conducted. The results show that - unlike the classic buck-boost converters - the proposed converter has a positive output voltage and a quadratic voltage gain that is higher than the traditional Zeta converters. Also, it has advantages such as common ground characteristics between output/input voltage terminals, continuous input current, simple structure and high efficiency. Additionally, the voltage stresses across the power switches of the proposed converter are less than half of the output voltage or equal to the sum of the input and output voltages. Therefore, the low on-resistance power switches are employed to reduce power losses and improve efficiency. On top of that, the high quadratic voltage gain and positive output polarity features present the superiority of the proposed converter against other similar converters.
{"title":"A New Positive Output High Gain Quadratic Buck-Boost Converter: Analysis, Design and Control","authors":"M. Hosseinpour, Armineh Dastgiri","doi":"10.5455/jjee.204-1670524690","DOIUrl":"https://doi.org/10.5455/jjee.204-1670524690","url":null,"abstract":"Abstract— In this paper, a non-isolated quadratic and buck-boost converter based on the Zeta structure is proposed, and its operating principle and analysis of its steady-state is discussed. Also, the parameter design is presented, and on-idealities are considered in the power circuit to analyze - in detail - the real voltage gain and efficiency of the proposed converter. Moreover, a simulation prototype is implemented to validate the theoretical analysis, and a comparison of the proposed converter with other similar topologies and small-signal models is conducted. The results show that - unlike the classic buck-boost converters - the proposed converter has a positive output voltage and a quadratic voltage gain that is higher than the traditional Zeta converters. Also, it has advantages such as common ground characteristics between output/input voltage terminals, continuous input current, simple structure and high efficiency. Additionally, the voltage stresses across the power switches of the proposed converter are less than half of the output voltage or equal to the sum of the input and output voltages. Therefore, the low on-resistance power switches are employed to reduce power losses and improve efficiency. On top of that, the high quadratic voltage gain and positive output polarity features present the superiority of the proposed converter against other similar converters.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70823332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1660326012
I. Omeiza, O. Ogunbiyi, O. Ogundepo, Abdulrahaman Okino Otuoze, D. Egbune, K. Osunsanya
In this paper a new algorithm for classification of three Nigerian paper currency notes, namely 200, 500, and 1000 Naira (N) denominations is presented. The work examines the effectiveness of using only colour histograms to differentiate between the classes or denominations of the three Nigerian paper currency notes. The bin-heights of the histograms of the HSI component images for the paper currencies are used as features while a rule-based classifier designed to take advantage of the changes or variations in the histogram patterns is used to classify the paper currencies into the right denomination class. The algorithm involves the utilization of a simple and effective comparison strategy as opposed to the existing, too-rigid metrics for histogram-comparison used by other authors for color indexing in content-based image retrieval systems. Over a testing data-set of 300 samples, the algorithm achieved an average classification accuracy of 98.66%, and classification accuracies of 100%, 99% and 97% for the N=200, N=500 and N=1000 denominations, respectively. The proposed algorithm does not require extensive preprocessing of the paper-currency images and as such is fast in implementation.
{"title":"A Method of Colour-Histogram Matching for Nigerian Paper Currency Notes Classification.","authors":"I. Omeiza, O. Ogunbiyi, O. Ogundepo, Abdulrahaman Okino Otuoze, D. Egbune, K. Osunsanya","doi":"10.5455/jjee.204-1660326012","DOIUrl":"https://doi.org/10.5455/jjee.204-1660326012","url":null,"abstract":"In this paper a new algorithm for classification of three Nigerian paper currency notes, namely 200, 500, and 1000 Naira (N) denominations is presented. The work examines the effectiveness of using only colour histograms to differentiate between the classes or denominations of the three Nigerian paper currency notes. The bin-heights of the histograms of the HSI component images for the paper currencies are used as features while a rule-based classifier designed to take advantage of the changes or variations in the histogram patterns is used to classify the paper currencies into the right denomination class. The algorithm involves the utilization of a simple and effective comparison strategy as opposed to the existing, too-rigid metrics for histogram-comparison used by other authors for color indexing in content-based image retrieval systems. Over a testing data-set of 300 samples, the algorithm achieved an average classification accuracy of 98.66%, and classification accuracies of 100%, 99% and 97% for the N=200, N=500 and N=1000 denominations, respectively. The proposed algorithm does not require extensive preprocessing of the paper-currency images and as such is fast in implementation.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70822451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1672498383
S. Sharroush, Sherif F. Nafea
Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.
{"title":"A Novel Domino Logic Based on Floating-Gate MOS Transistors","authors":"S. Sharroush, Sherif F. Nafea","doi":"10.5455/jjee.204-1672498383","DOIUrl":"https://doi.org/10.5455/jjee.204-1672498383","url":null,"abstract":"Domino logic finds a wide variety of applications in both static and dynamic random-access memories and in high-speed microprocessors. However, the main limitation of the domino logic-circuit family is the trade-off between the noise immunity and speed. In order to resolve such a trade-off, this paper proposes a domino logic that is based on floating-gate MOS (FGMOS) transistors. Compact-form expressions are derived for the noise margins for the low and high inputs as well as the propagation delays. The proposed scheme is verified by simulation adopting the 45 nm CMOS predictive technology model (PTM) with a power-supply voltage of 1 V. The obtained results unveil that the proposed domino logic outperforms the conventional domino logic in terms of the power-delay product and the energy-delay product when realizing wide fan-in OR gates. The realized, with the proposed scheme, 16-input OR gate has an average power consumption of 3.7 µW and a propagation delay of 51 ps.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70823230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1670351192
N. Saadallah, S. Alabady
Wireless sensor networks (WSNs) have several uses in a variety of industries; they are crucial components in many cutting-edge applications. WSNs are considered one of the newest applications to emerge is in the field of the Internet of Things (IoT), which enables the interconnection of various items or machines over the Internet, including the Internet of Things. This is why increase in the lifetime of the networks requires a strategy (protocol) that reduces the power consumption of the transmission or reception of data by the sensor nodes. A lot of research has been conducted, recently, to extend the lifetime of network sensors. The Hierarchical Cluster-based protocols and the Hierarchical Chain-based approaches have been created as solutions to this issue to reduce network traffic heading down the sink and so increase the lifetime of the network. In this survey, we look into the benefits and drawbacks of clustering when IoT is combined with cutting-edge technologies for computing and communication like 5G, fog/edge computing, and blockchain. Additionally, this survey offers helpful insights into the field of IoT clustering studies, enables a deeper comprehension of its design issues for IoT networks, and sheds the light on its potential future applications in cutting-edge IoT-integrated technologies.
{"title":"A Comprehensive Study on Energy Efficient-Cluster Based Routing Protocols in the Internet of Things: Hierarchical Routing Protocol","authors":"N. Saadallah, S. Alabady","doi":"10.5455/jjee.204-1670351192","DOIUrl":"https://doi.org/10.5455/jjee.204-1670351192","url":null,"abstract":"Wireless sensor networks (WSNs) have several uses in a variety of industries; they are crucial components in many cutting-edge applications. WSNs are considered one of the newest applications to emerge is in the field of the Internet of Things (IoT), which enables the interconnection of various items or machines over the Internet, including the Internet of Things. This is why increase in the lifetime of the networks requires a strategy (protocol) that reduces the power consumption of the transmission or reception of data by the sensor nodes. A lot of research has been conducted, recently, to extend the lifetime of network sensors. The Hierarchical Cluster-based protocols and the Hierarchical Chain-based approaches have been created as solutions to this issue to reduce network traffic heading down the sink and so increase the lifetime of the network. In this survey, we look into the benefits and drawbacks of clustering when IoT is combined with cutting-edge technologies for computing and communication like 5G, fog/edge computing, and blockchain. Additionally, this survey offers helpful insights into the field of IoT clustering studies, enables a deeper comprehension of its design issues for IoT networks, and sheds the light on its potential future applications in cutting-edge IoT-integrated technologies.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70823324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1677985772
Y. Omura
This paper proposes covalent-semiconductor-based lateral p-n junction film solar devices based on a theoretical model, and examines their power generation performance under illumination. The proposed theoretical model is implemented and tested in simulations. The results demonstrate that while Ge film devices have much lower performance at room temperature than Si film devices, this order is significantly reversed at temperatures below 250 K, which is very interesting. The obtained simulation results also reveal that the carrier generation characteristic of Ge film devices is very stable in terms of temperature variation in comparison to Si film devices. The simulation results suggest that thin-Si-film lateral p-n junction solar devices - implemented as multi-stacked solar devices formed on a transparent panel - are applicable to field sensor devices on the ground at temperatures lower than 300 K. However, thin-Ge-film lateral p-n junction solar devices are applicable to field sensor devices on satellites in space because the ambient temperature is lower than 250 K; again as a multi-stacked solar device formed on a transparent panel.
{"title":"Theoretical Estimation of Power Generation Performance of Nano-Sheet Planar Lateral P-N Junction under Illumination","authors":"Y. Omura","doi":"10.5455/jjee.204-1677985772","DOIUrl":"https://doi.org/10.5455/jjee.204-1677985772","url":null,"abstract":"This paper proposes covalent-semiconductor-based lateral p-n junction film solar devices based on a theoretical model, and examines their power generation performance under illumination. The proposed theoretical model is implemented and tested in simulations. The results demonstrate that while Ge film devices have much lower performance at room temperature than Si film devices, this order is significantly reversed at temperatures below 250 K, which is very interesting. The obtained simulation results also reveal that the carrier generation characteristic of Ge film devices is very stable in terms of temperature variation in comparison to Si film devices. The simulation results suggest that thin-Si-film lateral p-n junction solar devices - implemented as multi-stacked solar devices formed on a transparent panel - are applicable to field sensor devices on the ground at temperatures lower than 300 K. However, thin-Ge-film lateral p-n junction solar devices are applicable to field sensor devices on satellites in space because the ambient temperature is lower than 250 K; again as a multi-stacked solar device formed on a transparent panel.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70823285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1670927775
Ankush Tandon, Sarfaraz Nawaz
Optimal deployment of photovoltaic-based distributed generators (PVDG) and shunt capacitor units is a perilous task in modern power system planning. This work presents an effective Imperialist Competitive Algorithm (ICA) based on social political process for selecting the best locations and sizes for PVDGs and shunt capacitor units. Three different load patterns, i.e., nominal, decremented and incremented are taken into account while installing PVDG and shunt capacitor units in the typical radial distribution systems of 69-bus. The primary objective of this work is to reduce active power losses and to significantly improve the voltage pattern after positioning of PVDG and capacitor units. The results show that the losses are reduced significantly by integrating the PVDG and capacitor units simultaneously at the optimum position in the test system. Furthermore, results of simulating the 69 bus system (with the integrated PVDG and capacitors) prove to be promising and authentic.
{"title":"Optimal Integration of PV-Based Distributed Generators and Shunt Capacitors for 69 Bus System using Imperialist Competitive Algorithm and ETAP Software","authors":"Ankush Tandon, Sarfaraz Nawaz","doi":"10.5455/jjee.204-1670927775","DOIUrl":"https://doi.org/10.5455/jjee.204-1670927775","url":null,"abstract":"Optimal deployment of photovoltaic-based distributed generators (PVDG) and shunt capacitor units is a perilous task in modern power system planning. This work presents an effective Imperialist Competitive Algorithm (ICA) based on social political process for selecting the best locations and sizes for PVDGs and shunt capacitor units. Three different load patterns, i.e., nominal, decremented and incremented are taken into account while installing PVDG and shunt capacitor units in the typical radial distribution systems of 69-bus. The primary objective of this work is to reduce active power losses and to significantly improve the voltage pattern after positioning of PVDG and capacitor units. The results show that the losses are reduced significantly by integrating the PVDG and capacitor units simultaneously at the optimum position in the test system. Furthermore, results of simulating the 69 bus system (with the integrated PVDG and capacitors) prove to be promising and authentic.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70823346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1665256518
M. Hosseinpour, Tooraj Sabetfar, A. Dejamkhooy
In this paper, the design, control and stability analysis of the inverter-based power conditioner - which is connected to the low voltage grid via an LCL filter - is presented to manage the power flow of the Proton Exchange Membrane Fuel Cell (PEMFC). Since the PEMFC-generated voltage is lower than the grid voltage, a DC-DC converter is utilized to increase the PEMFC output voltage. The LCL filter is employed to improve the injected current quality and to reduce the inverter output voltage distortions. This filter can cause resonance and system instability. The current double feedback control method, which uses inverter side and grid side currents as feedback current, is suggested to dampen the resonance and improve harmonic eliminations. The suggested power conditioner system is simulated in MATLAB/Simulink to verify the model performance and the suggested control method. The obtained results show i) good performance of the suggested system in managing PEMFC power flow into the grid, ii) high quality of the injected current and iii) system stability against the grid impedance change disturbances.
{"title":"Power Conditioner Design and Control for a Grid-Connected Proton Exchange Membrane Fuel Cell","authors":"M. Hosseinpour, Tooraj Sabetfar, A. Dejamkhooy","doi":"10.5455/jjee.204-1665256518","DOIUrl":"https://doi.org/10.5455/jjee.204-1665256518","url":null,"abstract":"In this paper, the design, control and stability analysis of the inverter-based power conditioner - which is connected to the low voltage grid via an LCL filter - is presented to manage the power flow of the Proton Exchange Membrane Fuel Cell (PEMFC). Since the PEMFC-generated voltage is lower than the grid voltage, a DC-DC converter is utilized to increase the PEMFC output voltage. The LCL filter is employed to improve the injected current quality and to reduce the inverter output voltage distortions. This filter can cause resonance and system instability. The current double feedback control method, which uses inverter side and grid side currents as feedback current, is suggested to dampen the resonance and improve harmonic eliminations. The suggested power conditioner system is simulated in MATLAB/Simulink to verify the model performance and the suggested control method. The obtained results show i) good performance of the suggested system in managing PEMFC power flow into the grid, ii) high quality of the injected current and iii) system stability against the grid impedance change disturbances.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70822548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1670228110
M. N, A. R., K. S.
Underwater medium is the most difficult medium for data communication while Electromagnetic waves, acoustic waves, and optical signals are some of the present modes of communication in water. Electromagnetic waves would suffer a significant loss, limiting them to short-range communication; optical waves on the other hand, have line-of-sight concerns. The proposed work employs a Light Fidelity (Li-Fi) data transmission technology in a water medium to address these issues. Visible light communication allows to use a wide range of frequencies to send messages, when compared to other transmission technologies, the data transfer rate is likewise relatively high. Electronic components and level converters are utilized to regulate flickering and communicate data on both the transmitter and receiver sides, when exposed to the outer environment, it will lose the signal due to noise. To help with noise level estimate and signal reconstruction, the proposed work employs a machine learning technique that uses an encrypted block chain approach to check for data loss and a weighted Long Short-Term Memory (LSTM) algorithm to predict data from a Neural Network. The proposed work concludes that block chain can be the best way for data transfer in terms of minimizing errors while maintaining high accuracy.
{"title":"Block Chain Based Underwater Communication Using Li-Fi and Eliminating Noise Using Machine Learning","authors":"M. N, A. R., K. S.","doi":"10.5455/jjee.204-1670228110","DOIUrl":"https://doi.org/10.5455/jjee.204-1670228110","url":null,"abstract":"Underwater medium is the most difficult medium for data communication while Electromagnetic waves, acoustic waves, and optical signals are some of the present modes of communication in water. Electromagnetic waves would suffer a significant loss, limiting them to short-range communication; optical waves on the other hand, have line-of-sight concerns. The proposed work employs a Light Fidelity (Li-Fi) data transmission technology in a water medium to address these issues. Visible light communication allows to use a wide range of frequencies to send messages, when compared to other transmission technologies, the data transfer rate is likewise relatively high. Electronic components and level converters are utilized to regulate flickering and communicate data on both the transmitter and receiver sides, when exposed to the outer environment, it will lose the signal due to noise. To help with noise level estimate and signal reconstruction, the proposed work employs a machine learning technique that uses an encrypted block chain approach to check for data loss and a weighted Long Short-Term Memory (LSTM) algorithm to predict data from a Neural Network. The proposed work concludes that block chain can be the best way for data transfer in terms of minimizing errors while maintaining high accuracy.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70822648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1669028936
M. Tuka
A voltage dip is a sudden drop of voltages - generally between 10 and 90 % of the rated RMS value - during a period lasting from half a cycle to a few seconds on the phases of the power lines. It is one of the most important power quality problems affecting the stability of the Doubly Fed Induction Generator (DFIG) in Wind Energy Conversion System (WECS) and hence needs to be analyzed for a given machine for its performance analysis under grid disturbances. When a voltage dip problem happens in the given power as of faults, the magnitude of the rotor and stator currents of DFIG get increased, and hence disturbs steady state operation of the system. Therefore, in this paper, the worst voltage dip of 90 % is tested for grid faults on a 5 kW DFIG to validate its performance under this phenomenon. Based on the results of the simulation - along with its experimental validation - the machine is found to be robust for faults staying a shorter period without disconnecting it from the grid. On the other hand, operating a machine for a longer period while keeping it connected to a grid during a heavy dip, may result in its degradation as the rated limits are violated. To rectify and mitigate the aforesaid problems, a control system - with and without a crowbar - is developed for symmetrical faults to tackle such a problematic situation, and to discuss its fulfillment of the current grid code requirements. Finally, a complete model of the DFIG coupled with the grid is developed, modeled, analyzed and simulated using MATLAB/Simulink user-defined function toolbox block.
{"title":"Investigation of Voltage Dip Problems during Faults on a Grid-Tied Doubly Fed Induction Generator in a Wind Energy System","authors":"M. Tuka","doi":"10.5455/jjee.204-1669028936","DOIUrl":"https://doi.org/10.5455/jjee.204-1669028936","url":null,"abstract":"A voltage dip is a sudden drop of voltages - generally between 10 and 90 % of the rated RMS value - during a period lasting from half a cycle to a few seconds on the phases of the power lines. It is one of the most important power quality problems affecting the stability of the Doubly Fed Induction Generator (DFIG) in Wind Energy Conversion System (WECS) and hence needs to be analyzed for a given machine for its performance analysis under grid disturbances. When a voltage dip problem happens in the given power as of faults, the magnitude of the rotor and stator currents of DFIG get increased, and hence disturbs steady state operation of the system. Therefore, in this paper, the worst voltage dip of 90 % is tested for grid faults on a 5 kW DFIG to validate its performance under this phenomenon. Based on the results of the simulation - along with its experimental validation - the machine is found to be robust for faults staying a shorter period without disconnecting it from the grid. On the other hand, operating a machine for a longer period while keeping it connected to a grid during a heavy dip, may result in its degradation as the rated limits are violated. To rectify and mitigate the aforesaid problems, a control system - with and without a crowbar - is developed for symmetrical faults to tackle such a problematic situation, and to discuss its fulfillment of the current grid code requirements. Finally, a complete model of the DFIG coupled with the grid is developed, modeled, analyzed and simulated using MATLAB/Simulink user-defined function toolbox block.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70822759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-01-01DOI: 10.5455/jjee.204-1671142029
S. Sharroush, Y. Abdalla
— In this paper, an electronically tunable universal biquadratic voltage-mode filter that is based only on MOS transistors is proposed. Configuration of the proposed filter is simple and there is no need to use component matching. Since the proposed filter contains only MOS transistors, it is very suitable for implementation in system-on-chip (SoC) applications. The cutoff frequency of the lowpass (LP) and highpass (HP) filters as well as the center frequency and the bandwidth of the bandpass (BP) and bandstop (BS) filters can be controlled either in a continuous range or in a discrete manner by means of a digital control word. Besides, the filter type can be changed during the real time by an appropriate code. Operation of all the filtering functions are verified by simulation using the Berkeley predictive-technology models (BPTM) of the 130 nm complementary metal-oxide semiconductor (CMOS) technology with power-supply voltage, VDD, of 1.2 V. The proposed filter is analyzed quantitatively, and the effects of the total-harmonic distortion (THD), noise, process, voltage and temperature (PVT) variations are also investigated. The average power consumption of the LP, HP, BP, BS, and allpass (AP) filters are found to be 30, 118, 74, 118, and 30 (all in µW). The price paid for all these advantages is more sensitivity to process variations for the lowpass filter.
{"title":"A Real-Time Electronically Tunable All-MOS Universal Biquadratic Voltage-Mode Filter","authors":"S. Sharroush, Y. Abdalla","doi":"10.5455/jjee.204-1671142029","DOIUrl":"https://doi.org/10.5455/jjee.204-1671142029","url":null,"abstract":"— In this paper, an electronically tunable universal biquadratic voltage-mode filter that is based only on MOS transistors is proposed. Configuration of the proposed filter is simple and there is no need to use component matching. Since the proposed filter contains only MOS transistors, it is very suitable for implementation in system-on-chip (SoC) applications. The cutoff frequency of the lowpass (LP) and highpass (HP) filters as well as the center frequency and the bandwidth of the bandpass (BP) and bandstop (BS) filters can be controlled either in a continuous range or in a discrete manner by means of a digital control word. Besides, the filter type can be changed during the real time by an appropriate code. Operation of all the filtering functions are verified by simulation using the Berkeley predictive-technology models (BPTM) of the 130 nm complementary metal-oxide semiconductor (CMOS) technology with power-supply voltage, VDD, of 1.2 V. The proposed filter is analyzed quantitatively, and the effects of the total-harmonic distortion (THD), noise, process, voltage and temperature (PVT) variations are also investigated. The average power consumption of the LP, HP, BP, BS, and allpass (AP) filters are found to be 30, 118, 74, 118, and 30 (all in µW). The price paid for all these advantages is more sensitivity to process variations for the lowpass filter.","PeriodicalId":29729,"journal":{"name":"Jordan Journal of Electrical Engineering","volume":null,"pages":null},"PeriodicalIF":0.7,"publicationDate":"2023-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70823207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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