Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582412
I. Gibson, Chris Amies
This paper describes the evolution of a design and verification methodology successfully used to develop advanced ASICs as components of multiple new commercial products. The ASICs are typically large, high speed, algorithmically complex and implement novel functionality. The ASIC development process is driven by the commercial pressures of low cost and short schedules of multiple projects. It is carried out using a team of designers of varying experience including new staff. The dual emphasis of our methodology is maintaining fine control over the design and verification process, together with full independent cross verification as an integral part of the entire ASIC and system development process.
{"title":"Practical concurrent ASIC and system design and verification","authors":"I. Gibson, Chris Amies","doi":"10.1109/EDTC.1997.582412","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582412","url":null,"abstract":"This paper describes the evolution of a design and verification methodology successfully used to develop advanced ASICs as components of multiple new commercial products. The ASICs are typically large, high speed, algorithmically complex and implement novel functionality. The ASIC development process is driven by the commercial pressures of low cost and short schedules of multiple projects. It is carried out using a team of designers of varying experience including new staff. The dual emphasis of our methodology is maintaining fine control over the design and verification process, together with full independent cross verification as an integral part of the entire ASIC and system development process.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116723662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582368
U. Geigenmuller, N. P. van der Meijs
Application of the hierarchical Schur algorithm to the boundary element method for 3D capacitance extraction shifts the speed bottleneck from inversion of the influence matrix to its calculation. We show how the numerical integration required for the latter can be accelerated by an order of magnitude with the aid of a multipole expansion in Cartesian formulation. The scheme differs essentially from that of the FASTCAP extractor.
{"title":"Cartesian multipole based numerical integration for 3D capacitance extraction","authors":"U. Geigenmuller, N. P. van der Meijs","doi":"10.1109/EDTC.1997.582368","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582368","url":null,"abstract":"Application of the hierarchical Schur algorithm to the boundary element method for 3D capacitance extraction shifts the speed bottleneck from inversion of the influence matrix to its calculation. We show how the numerical integration required for the latter can be accelerated by an order of magnitude with the aid of a multipole expansion in Cartesian formulation. The scheme differs essentially from that of the FASTCAP extractor.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132881364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582353
A. Hett, R. Drechsler, B. Becker
We present a new approach to symbolic simulation with BDDs. Our method uses Reordering Based Synthesis (RBS) which allows the integration of dynamic variable ordering (even) within a single synthesis operation (e.g. an AND-operation). Thus, huge peak sizes during the construction can often be avoided, and we obtain a method that, with no penalty in runtime, is more memory efficient than traditional ITE operator based symbolic simulation. The results are confirmed by experiments on a large set of benchmarks: We give a comparison to previously published approaches and also consider some industrial benchmarks which are known to be hard to handle.
{"title":"Fast and efficient construction of BDDs by reordering based synthesis","authors":"A. Hett, R. Drechsler, B. Becker","doi":"10.1109/EDTC.1997.582353","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582353","url":null,"abstract":"We present a new approach to symbolic simulation with BDDs. Our method uses Reordering Based Synthesis (RBS) which allows the integration of dynamic variable ordering (even) within a single synthesis operation (e.g. an AND-operation). Thus, huge peak sizes during the construction can often be avoided, and we obtain a method that, with no penalty in runtime, is more memory efficient than traditional ITE operator based symbolic simulation. The results are confirmed by experiments on a large set of benchmarks: We give a comparison to previously published approaches and also consider some industrial benchmarks which are known to be hard to handle.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125794495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582340
J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev
This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library, while preserving speed-independence. The algorithm exploits known efficient factorization techniques from combinational multi-level logic synthesis, but achieves also Boolean simplification. Experimental results show a significant improvement in terms of number and complexity of solvable circuits with respect to existing methods.
{"title":"Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis","authors":"J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, A. Yakovlev","doi":"10.1109/EDTC.1997.582340","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582340","url":null,"abstract":"This paper presents a solution to the problem of sequential multi-level logic synthesis of asynchronous speed-independent circuits. The starting point is a technology-independent speed-independent circuit obtained using, e.g., the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library, while preserving speed-independence. The algorithm exploits known efficient factorization techniques from combinational multi-level logic synthesis, but achieves also Boolean simplification. Experimental results show a significant improvement in terms of number and complexity of solvable circuits with respect to existing methods.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123960753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582392
S. Gavrilov, A. Glebov, S. Rusakov, D. Blaauw, L. G. Jones, G. Vijayan
In this paper we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level simulation algorithm that takes into account both short-circuit power and charge-sharing power effects. In benchmarks against a popular commercial power simulation tool, our approach yields power measurements on average within 3% of the commercial solution, while taking between 15 to 20 times less CPU time.
{"title":"Fast power loss calculation for digital static CMOS circuits","authors":"S. Gavrilov, A. Glebov, S. Rusakov, D. Blaauw, L. G. Jones, G. Vijayan","doi":"10.1109/EDTC.1997.582392","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582392","url":null,"abstract":"In this paper we present a new dynamic power estimation method that produces accurate power measures at considerably faster run times. The approach uses an enhanced switch-level simulation algorithm that takes into account both short-circuit power and charge-sharing power effects. In benchmarks against a popular commercial power simulation tool, our approach yields power measurements on average within 3% of the commercial solution, while taking between 15 to 20 times less CPU time.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127331330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582432
Renate Beckmann, J. Herrmann
Summary form only. In modern computer systems the performance is dominated by the memory performance. Currently, there is neither a systematic design methodology nor a tool for the design of memory systems for general purpose computers. We present a first approach to CAD support for this crucial subtask of system level design. Dependencies between influencing factors and design decisions are explicitly represented by constraints, and constraint logic programming is used to make the design decisions. The memory design is optimized with respect to several objectives by iterating the (re)design cycle. Event driven simulation is used for evaluation of the intermediate results. The system is organized as an interactive design assistant.
{"title":"Using constraint logic programming in memory synthesis for general purpose computers","authors":"Renate Beckmann, J. Herrmann","doi":"10.1109/EDTC.1997.582432","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582432","url":null,"abstract":"Summary form only. In modern computer systems the performance is dominated by the memory performance. Currently, there is neither a systematic design methodology nor a tool for the design of memory systems for general purpose computers. We present a first approach to CAD support for this crucial subtask of system level design. Dependencies between influencing factors and design decisions are explicitly represented by constraints, and constraint logic programming is used to make the design decisions. The memory design is optimized with respect to several objectives by iterating the (re)design cycle. Event driven simulation is used for evaluation of the intermediate results. The system is organized as an interactive design assistant.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130003142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582430
V. Székely, A. Pahi, A. Poppe, M. Rencz, A. Csendes
Summary form only given. With the decreasing feature sizes and increasing packaging densities, thermal effects influence more and more the operation of integrated circuits. The accurate consideration of thermal effects while predicting the electrical behaviour of the ICs became crucial in case of high performance integrated circuits both for analog and digital ones. The SISSSI electro-thermal simulator family can be applied for the above purpose, both for analog and digital designs. The common feature of the SISSSI versions (SISSSI-Classic and SISSSI-Logitherm) is that they construct the layout based thermal model of the IC automatically and consider accurately the effect of the chip encapsulation as well. Here we present the developments in the SISSSI-Classic version which is aimed at device level (analog) electro-thermal simulation.
{"title":"SISSSI-A tool for dynamic electro-thermal simulation of analog VLSI cells","authors":"V. Székely, A. Pahi, A. Poppe, M. Rencz, A. Csendes","doi":"10.1109/EDTC.1997.582430","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582430","url":null,"abstract":"Summary form only given. With the decreasing feature sizes and increasing packaging densities, thermal effects influence more and more the operation of integrated circuits. The accurate consideration of thermal effects while predicting the electrical behaviour of the ICs became crucial in case of high performance integrated circuits both for analog and digital ones. The SISSSI electro-thermal simulator family can be applied for the above purpose, both for analog and digital designs. The common feature of the SISSSI versions (SISSSI-Classic and SISSSI-Logitherm) is that they construct the layout based thermal model of the IC automatically and consider accurately the effect of the chip encapsulation as well. Here we present the developments in the SISSSI-Classic version which is aimed at device level (analog) electro-thermal simulation.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129064482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582429
H. Ihs, C. Dufaza
Built-In Self Test (BIST) consists of integrating totally or partially a Test Pattern Generator (TPG) and/or a Response Analyzer (RA) in the same chip with the Circuit Under Test (CUT). Generally, an efficient analog test requires the monitoring of several performances by applying different frequencies as test stimuli. For BIST application, the integration of a frequency TPG and RA can not be economically viable for most applications because of their corresponding area overhead and complexity. BIST techniques based on frequency analysis are very expensive for the silicon area. On the other hand, BIST solutions based on a DC test remain poor concerning the fault coverage. This is true if no Design For Testability (DFT) elements are used in conjunction with a DC BIST to eliminate this problem. Exactly, our approach consists of using some DFT means so as all defects of SC circuits become detectable in the DC domain. Then a DC stimulus as an existing voltage source Vdd, Gnd and Vss corresponds to a simple TPG while the RA is a small window comparator. Finally, the addition of these DFT elements allows to decrease considerably the DC BIST hardware and corresponds in fact to a tradeoff between BIST complexity and DFT resources. With this mixed BIST/DFT technique we obtain a comparable fault coverage than frequency based approaches and this for a lower hardware cost.
{"title":"Test synthesis for DC test of switched-capacitors circuits","authors":"H. Ihs, C. Dufaza","doi":"10.1109/EDTC.1997.582429","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582429","url":null,"abstract":"Built-In Self Test (BIST) consists of integrating totally or partially a Test Pattern Generator (TPG) and/or a Response Analyzer (RA) in the same chip with the Circuit Under Test (CUT). Generally, an efficient analog test requires the monitoring of several performances by applying different frequencies as test stimuli. For BIST application, the integration of a frequency TPG and RA can not be economically viable for most applications because of their corresponding area overhead and complexity. BIST techniques based on frequency analysis are very expensive for the silicon area. On the other hand, BIST solutions based on a DC test remain poor concerning the fault coverage. This is true if no Design For Testability (DFT) elements are used in conjunction with a DC BIST to eliminate this problem. Exactly, our approach consists of using some DFT means so as all defects of SC circuits become detectable in the DC domain. Then a DC stimulus as an existing voltage source Vdd, Gnd and Vss corresponds to a simple TPG while the RA is a small window comparator. Finally, the addition of these DFT elements allows to decrease considerably the DC BIST hardware and corresponds in fact to a tradeoff between BIST complexity and DFT resources. With this mixed BIST/DFT technique we obtain a comparable fault coverage than frequency based approaches and this for a lower hardware cost.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"4 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120857373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582403
F. Thoen, J. V. D. Steen, G. D. Jong, G. Goossens, H. Man
Software synthesis is a new approach which focuses on the support of real-time embedded multi-tasking software without the use of operating systems. A software synthesis system starts from a concurrent process system specification and maps this description automatically onto one or more processors. In this paper the internal system-level model which captures the embedded software and which is the backbone of our software synthesis methodology, is presented. The model captures the fine-grain behaviour of a system, and supports multiple threads of control (concurrency), synchronisation, data communication, hierarchy and timing constraints.
{"title":"Multi-thread graph: a system model for real-time embedded software synthesis","authors":"F. Thoen, J. V. D. Steen, G. D. Jong, G. Goossens, H. Man","doi":"10.1109/EDTC.1997.582403","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582403","url":null,"abstract":"Software synthesis is a new approach which focuses on the support of real-time embedded multi-tasking software without the use of operating systems. A software synthesis system starts from a concurrent process system specification and maps this description automatically onto one or more processors. In this paper the internal system-level model which captures the embedded software and which is the backbone of our software synthesis methodology, is presented. The model captures the fine-grain behaviour of a system, and supports multiple threads of control (concurrency), synchronisation, data communication, hierarchy and timing constraints.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121267127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582410
P. Surti, L. Chao, A. Tyagi
This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.
{"title":"Low power FSM design using Huffman-style encoding","authors":"P. Surti, L. Chao, A. Tyagi","doi":"10.1109/EDTC.1997.582410","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582410","url":null,"abstract":"This paper presents a novel approach to synthesize low power FSMs using non-uniform code length. Switching activity is reduced by decreasing the expected number of state bits switched less than [log |S|] The state set S of the FSM is decomposed into two sets based on the limit state probabilities. The state set with very high probability is encoded with less than [log|S|] bits. The other state set, being less probable, is encoded using more than [log|S|] bits. To the best of our knowledge, this is the first time two code lengths ore used for one state machine. This encoding is realized by using flip-flops with gated clock. The logic generating the enable signal of the clock uses only a single minterm. The state sets can be encoded using any uniform-length encoding algorithm with objectives of low power and low area. The experiments show an average of 13% and 18% reduction in power for two encoding algorithms respectively.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"174 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121310812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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