Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582418
M. Renovell, F. Azais, Y. Bertrand
In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal integrated circuits. The integration function is identified as a powerful analog compression scheme and an analog signature analyzer is proposed. The op amp-based implementation allows one to define single and multiple-input versions. The multiple-input analyzer permits the monitoring of some extra internal nodes in addition to the classical output nodes, or the concurrent control of both voltage and current levels. This ability leads to an improvement of the circuit testability and consequently, the on-chip response evaluation gives a higher fault coverage than the off-chip one.
{"title":"On-chip analog output response compaction","authors":"M. Renovell, F. Azais, Y. Bertrand","doi":"10.1109/EDTC.1997.582418","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582418","url":null,"abstract":"In this paper, we propose a technique for on-chip analog output response compaction in order to implement self-test capabilities in analog and mixed-signal integrated circuits. The integration function is identified as a powerful analog compression scheme and an analog signature analyzer is proposed. The op amp-based implementation allows one to define single and multiple-input versions. The multiple-input analyzer permits the monitoring of some extra internal nodes in addition to the classical output nodes, or the concurrent control of both voltage and current levels. This ability leads to an improvement of the circuit testability and consequently, the on-chip response evaluation gives a higher fault coverage than the off-chip one.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"546 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123113866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582349
S. Bhattacharya, S. Dey, B. SenGupta
This paper introduces a low overhead test methodology, RT-SCAN, applicable to RT Level designs. The methodology enables using combinational test patterns for testing the circuit, as done by traditional full-scan or parallel-scan schemes. However, by exploiting existing connectivity of registers through multiplexors and functional units, RT-SCAN reduces area overhead and test application times significantly compared to full-scan and parallel-scan schemes. Unlike most of the existing high-level test synthesis and test generation schemes which can be most effectively applied to data-flow/arithmetic intensive designs like DSPs and processor designs, the RT-SCAN test scheme can be applied to designs from any application domain, including control-flow intensive designs.
{"title":"An RTL methodology to enable low overhead combinational testing","authors":"S. Bhattacharya, S. Dey, B. SenGupta","doi":"10.1109/EDTC.1997.582349","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582349","url":null,"abstract":"This paper introduces a low overhead test methodology, RT-SCAN, applicable to RT Level designs. The methodology enables using combinational test patterns for testing the circuit, as done by traditional full-scan or parallel-scan schemes. However, by exploiting existing connectivity of registers through multiplexors and functional units, RT-SCAN reduces area overhead and test application times significantly compared to full-scan and parallel-scan schemes. Unlike most of the existing high-level test synthesis and test generation schemes which can be most effectively applied to data-flow/arithmetic intensive designs like DSPs and processor designs, the RT-SCAN test scheme can be applied to designs from any application domain, including control-flow intensive designs.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"208 0 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582333
M. Nourani, C. Papachristou
The purpose of this work is to develop a test synthesis technique based on BIST methodology which uses the test metrics (i.e. controllability and observability) obtained by test analysis of the behavior to enhance the testability quality (fault coverage) of the corresponding structure and obtain the scheduled test behavior accordingly. The key feature of this work is in using the Structured Data Flow Graph (SDG) which annotates the behavioral information (e.g. data dependency) and structural information (e.g. binding, connectivity). To enhance testability of the structure, the SDG is modified using transformation technique to improve the fault coverage and shorten the test schedule.
{"title":"Structural BIST insertion using behavioral test analysis","authors":"M. Nourani, C. Papachristou","doi":"10.1109/EDTC.1997.582333","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582333","url":null,"abstract":"The purpose of this work is to develop a test synthesis technique based on BIST methodology which uses the test metrics (i.e. controllability and observability) obtained by test analysis of the behavior to enhance the testability quality (fault coverage) of the corresponding structure and obtain the scheduled test behavior accordingly. The key feature of this work is in using the Structured Data Flow Graph (SDG) which annotates the behavioral information (e.g. data dependency) and structural information (e.g. binding, connectivity). To enhance testability of the structure, the SDG is modified using transformation technique to improve the fault coverage and shorten the test schedule.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134412286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582400
S. Govindarajan, R. Vemuri
List scheduling algorithms attempt to minimize latency under resource constraints using a priority list. We propose a new heuristic that can be used in conjunction with any priority function. At each time-step, the proposed clustering heuristic tries to find a best match between ready operations and the resource set. The heuristic arbitrates among equal priority operations based on operation-clusters formed from the dependency graph. Based on this heuristic we have presented a new Cone-Based List Scheduling (CBLS) algorithm. Results presented in this paper compare CBLS with the well-known Force Directed List Scheduling (FDLS) algorithm, for several synthesis benchmarks. In cases where FDLS produces sub-optimal schedules, CBLS produces better schedules and in other cases CBLS performs as good as FDLS. Moreover, in conjunction with a simple priority function (namely the self-force of an operator), CBLS results in considerable improvement in latency when compared to FDLS that has the same priority function. Finally, we show that CBLS with the simple priority function performs better in execution time as well as latency when compared to the original FDLS that has a relatively complex priority function.
{"title":"Cone-based clustering heuristic for list-scheduling algorithms","authors":"S. Govindarajan, R. Vemuri","doi":"10.1109/EDTC.1997.582400","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582400","url":null,"abstract":"List scheduling algorithms attempt to minimize latency under resource constraints using a priority list. We propose a new heuristic that can be used in conjunction with any priority function. At each time-step, the proposed clustering heuristic tries to find a best match between ready operations and the resource set. The heuristic arbitrates among equal priority operations based on operation-clusters formed from the dependency graph. Based on this heuristic we have presented a new Cone-Based List Scheduling (CBLS) algorithm. Results presented in this paper compare CBLS with the well-known Force Directed List Scheduling (FDLS) algorithm, for several synthesis benchmarks. In cases where FDLS produces sub-optimal schedules, CBLS produces better schedules and in other cases CBLS performs as good as FDLS. Moreover, in conjunction with a simple priority function (namely the self-force of an operator), CBLS results in considerable improvement in latency when compared to FDLS that has the same priority function. Finally, we show that CBLS with the simple priority function performs better in execution time as well as latency when compared to the original FDLS that has a relatively complex priority function.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132918704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582362
Jacobo Riesco, J. C. Diaz, L. A. Merayo, J. L. Conesa, Carlos Santos, E. J. Martínez
The present paper describes the AMDA integrated circuit (ATM Multiplexer/Demultiplexor ASIC). The circuit has two operation modes: in multiplexer mode an ATM low speed flow (up to 622 Mbits/s) is inserted in the empty slots of a high speed ATM flow (2.5 Gbits/s); in demultiplexer mode, the cells belonging to the low speed channels are extracted from the high speed ATM flow. An specific algorithm of distributed control has been developed, simulated and implemented, in order to guarantee an even bandwidth distribution independently of the network node position. The circuit is able to handle 8 K connections, with four different qualities of service; it manages a local queue of up to 16 K ATM cells using an external high speed SSRAM. The maximum clock frequency of the circuit is 155,52 MHz and it has been processed with the LSI-LOGIC's LCB5OOK technology (0,5 /spl mu/m CMOS). It contains 34800 equivalent gates, 48 Kbit of single port memory and 8,5 Kbit dual port memory, using an area of 6,7/spl times/6,7 mm and it is packaged in a 208 pins QFP.
{"title":"On the way to the 2.5 Gbits/s ATM network ATM multiplexer demultiplexer ASIC","authors":"Jacobo Riesco, J. C. Diaz, L. A. Merayo, J. L. Conesa, Carlos Santos, E. J. Martínez","doi":"10.1109/EDTC.1997.582362","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582362","url":null,"abstract":"The present paper describes the AMDA integrated circuit (ATM Multiplexer/Demultiplexor ASIC). The circuit has two operation modes: in multiplexer mode an ATM low speed flow (up to 622 Mbits/s) is inserted in the empty slots of a high speed ATM flow (2.5 Gbits/s); in demultiplexer mode, the cells belonging to the low speed channels are extracted from the high speed ATM flow. An specific algorithm of distributed control has been developed, simulated and implemented, in order to guarantee an even bandwidth distribution independently of the network node position. The circuit is able to handle 8 K connections, with four different qualities of service; it manages a local queue of up to 16 K ATM cells using an external high speed SSRAM. The maximum clock frequency of the circuit is 155,52 MHz and it has been processed with the LSI-LOGIC's LCB5OOK technology (0,5 /spl mu/m CMOS). It contains 34800 equivalent gates, 48 Kbit of single port memory and 8,5 Kbit dual port memory, using an area of 6,7/spl times/6,7 mm and it is packaged in a 208 pins QFP.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134375757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582396
S. Hendricx, L. Claesen
In the past, formal verification-the promising alternative to simulation-based verification-has primarily been applied to digital system designs. Despite the ever-growing importance of integrated mixed analog/digital systems, hardly any formal approaches have been introduced to verify such designs. In this paper, a preliminary study of a symbolic modelling technique is presented which allows us to formally verify the functional correctness of integrated mixed-mode systems. The usefulness of the approach has been demonstrated by verifying the SmartPen/sup T/M a practical integrated mixed-mode application.
{"title":"A symbolic core approach to the formal verification of integrated mixed-mode applications","authors":"S. Hendricx, L. Claesen","doi":"10.1109/EDTC.1997.582396","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582396","url":null,"abstract":"In the past, formal verification-the promising alternative to simulation-based verification-has primarily been applied to digital system designs. Despite the ever-growing importance of integrated mixed analog/digital systems, hardly any formal approaches have been introduced to verify such designs. In this paper, a preliminary study of a symbolic modelling technique is presented which allows us to formally verify the functional correctness of integrated mixed-mode systems. The usefulness of the approach has been demonstrated by verifying the SmartPen/sup T/M a practical integrated mixed-mode application.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"37 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132120158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582325
M. Hsiao, E. Rudnick, J. Patel
A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.
{"title":"Sequential circuit test generation using dynamic state traversal","authors":"M. Hsiao, E. Rudnick, J. Patel","doi":"10.1109/EDTC.1997.582325","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582325","url":null,"abstract":"A new method for state justification is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132256123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582373
M. Corbalan, M. Kaspar, F. Catthoor, H. Man
A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure.
{"title":"Architectural exploration and optimization for counter based hardware address generation","authors":"M. Corbalan, M. Kaspar, F. Catthoor, H. Man","doi":"10.1109/EDTC.1997.582373","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582373","url":null,"abstract":"A set of automated system level techniques is presented for architectural exploration and optimization of counter based address generation units in real time signal processing systems. The goal is to explore different architectural alternatives available when mapping array references in order to select the most promising ones in area cost. The techniques are demonstrated on realistic test-vehicles, showing that architectural decision at early stages of the design process, can have a very large impact on the resulting area figure.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132371464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582366
J. Fishburn
Euler's differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the load-end wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimal-width rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width.
{"title":"Shaping a VLSI wire to minimize Elmore delay","authors":"J. Fishburn","doi":"10.1109/EDTC.1997.582366","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582366","url":null,"abstract":"Euler's differential equation of the calculus of variations is used to determine the shape of a VLSI wire that minimizes Elmore delay. The solution is given as a power series whose coefficients are formulas involving the load-end wire width, the load capacitance, the capacitance per unit area, and the capacitance per unit perimeter. In contrast to an optimal-width rectangular wire, the RC Elmore delay of the optimally tapered wire goes to zero as the driver resistance goes to zero. The optimal taper is immune, to first order, to process variations affecting wire width.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130107676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582365
A. Wahba, D. Borrione
We present new diagnostic algorithms for localizing connection errors in combinational circuits. Three types of errors are considered: extra, missing, and bad connection errors. Special test patterns are generated to rapidly locate the error. The algorithms are integrated within the Prevail/sup TM/ system. Results on benchmarks show that the error is always located within a time proportional to the product of the circuit size, and the number of used patterns.
{"title":"Connection error location and correction in combinational circuits","authors":"A. Wahba, D. Borrione","doi":"10.1109/EDTC.1997.582365","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582365","url":null,"abstract":"We present new diagnostic algorithms for localizing connection errors in combinational circuits. Three types of errors are considered: extra, missing, and bad connection errors. Special test patterns are generated to rapidly locate the error. The algorithms are integrated within the Prevail/sup TM/ system. Results on benchmarks show that the error is always located within a time proportional to the product of the circuit size, and the number of used patterns.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114879396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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