Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582355
G. Cabodi, P. Camurati, L. Lavagno, S. Quer
Symbolic Techniques have undergone major improvements but extending their applicability to new fields is still a key issue. A great limitation on standard Symbolic Traversals is represented by Finite State Machines with a very high sequential depth. A typical example of this behaviour are counters. On the other hand systems containing counters, e.g. embedded systems, are of great practical importance in several fields. Iterative squaring can produce solutions with a logarithmic execution time with respect to the sequential depth but a few drawbacks usually limit its application. We successfully tailored iterative squaring to allow its application for symbolic verification and synthesis of circuits containing counters. Experiments on large and complex home-made and industrials circuits containing counters show the feasibility of the approach.
{"title":"Verification and synthesis of counters based on symbolic techniques","authors":"G. Cabodi, P. Camurati, L. Lavagno, S. Quer","doi":"10.1109/EDTC.1997.582355","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582355","url":null,"abstract":"Symbolic Techniques have undergone major improvements but extending their applicability to new fields is still a key issue. A great limitation on standard Symbolic Traversals is represented by Finite State Machines with a very high sequential depth. A typical example of this behaviour are counters. On the other hand systems containing counters, e.g. embedded systems, are of great practical importance in several fields. Iterative squaring can produce solutions with a logarithmic execution time with respect to the sequential depth but a few drawbacks usually limit its application. We successfully tailored iterative squaring to allow its application for symbolic verification and synthesis of circuits containing counters. Experiments on large and complex home-made and industrials circuits containing counters show the feasibility of the approach.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124321110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582398
M. Favalli, C. Metra
This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.
{"title":"Testing scheme for IC's clocks","authors":"M. Favalli, C. Metra","doi":"10.1109/EDTC.1997.582398","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582398","url":null,"abstract":"This paper proposes a testing scheme to detect abnormal skews between clock signals inside digital synchronous ICs. The scheme is based on a new CMOS sensing circuit whose compactness and testability with respect to a large set of failures make it suitable for both off-line and on-line testing.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117044564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582367
S. Kundu, U. Ghoshal
It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency of circuits rises above GHz level. In this paper we show that this perception is not true. It becomes necessary to consider the inductive effects in all circuits implemented in deep submicron CMOS technologies. For 0.25 /spl mu/m (lithography) technologies, where the supply voltage is expected to be in the range of 1.2-1.8 V, inductive effects are an important consideration regardless of system frequency. Furthermore, contrary to the popular belief we show that inductive effects are important even for highly resistive lines.
{"title":"Inductance analysis of on-chip interconnects [deep submicron CMOS]","authors":"S. Kundu, U. Ghoshal","doi":"10.1109/EDTC.1997.582367","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582367","url":null,"abstract":"It is generally believed that inductance analysis of on-chip interconnect becomes important when the clock frequency of circuits rises above GHz level. In this paper we show that this perception is not true. It becomes necessary to consider the inductive effects in all circuits implemented in deep submicron CMOS technologies. For 0.25 /spl mu/m (lithography) technologies, where the supply voltage is expected to be in the range of 1.2-1.8 V, inductive effects are an important consideration regardless of system frequency. Furthermore, contrary to the popular belief we show that inductive effects are important even for highly resistive lines.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132943967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582341
K. Hofmann, M. Glesner, N. Sebe, A. Manolescu, S. Marco, J. Samitier, J. Karam, B. Courtois
A CAD tool for the automated generation of behavioral models in HDL-A is presented. This CAD tool has been implemented in the frame of a project for the automatic modeling of microsystem components for the co-simulation with VHDLor Spice-models. Starting from the finite-element-description of a microcomponent a nonlinear behavioral HDL-A-model is generated by successively adding or deleting effects to the HDL-A-model according to the observed differences between the two models. Using the example of a micromembrane the practicability of this approach is demonstrated. This CAD tool provides a method for decoupling the generation of behavioral models from the finite-element-simulation process.
{"title":"Generation of the HDL-A-model of a micromembrane from its finite-element-description","authors":"K. Hofmann, M. Glesner, N. Sebe, A. Manolescu, S. Marco, J. Samitier, J. Karam, B. Courtois","doi":"10.1109/EDTC.1997.582341","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582341","url":null,"abstract":"A CAD tool for the automated generation of behavioral models in HDL-A is presented. This CAD tool has been implemented in the frame of a project for the automatic modeling of microsystem components for the co-simulation with VHDLor Spice-models. Starting from the finite-element-description of a microcomponent a nonlinear behavioral HDL-A-model is generated by successively adding or deleting effects to the HDL-A-model according to the observed differences between the two models. Using the example of a micromembrane the practicability of this approach is demonstrated. This CAD tool provides a method for decoupling the generation of behavioral models from the finite-element-simulation process.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134193541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582337
Andre Hertwig, H. Wunderlich
A target structure for implementing fast edge-triggered control units is presented. In many cases, the proposed controller is faster than a one-hot encoded structure as its correct timing does not require master-slave flip-flops even in the presence of unpredictable clocking skews. A synthesis procedure is proposed which leads to a performance improvement of 40% on average for the standard benchmark set whereas the additional area is less than 25% compared with conventional finite state machine (FSM) synthesis. The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.
{"title":"Fast controllers for data dominated applications","authors":"Andre Hertwig, H. Wunderlich","doi":"10.1109/EDTC.1997.582337","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582337","url":null,"abstract":"A target structure for implementing fast edge-triggered control units is presented. In many cases, the proposed controller is faster than a one-hot encoded structure as its correct timing does not require master-slave flip-flops even in the presence of unpredictable clocking skews. A synthesis procedure is proposed which leads to a performance improvement of 40% on average for the standard benchmark set whereas the additional area is less than 25% compared with conventional finite state machine (FSM) synthesis. The proposed approach is compatible with the state-of-the-art methods for FSM decomposition, state encoding and logic synthesis.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123344571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582376
Le-Chin Eugene Liu, C. Sechen
We present a chip-level global router based on a new, more accurate global routing model for the multi-layer macro-cell technology. The routing model uses a 3-dimensional mixed directed/undirected routing graph, which accurately models the multi-layer routing problem. However the complexity of the routing graph challenges previous route-generating algorithms. Generating the routes is to search for the Steiner minimum trees for the nets, which is an NP-hard problem. We developed an improved Steiner tree heuristic algorithm suitable for large routing graphs and able to generate high quality Steiner tree routing. Tested on industrial circuits, our algorithm yields comparable results while having dramatically lower time and space complexities than the leading heuristics. While minimizing the wire length, our global router can also minimize the number of vias or solve the routing resource congestion problems.
{"title":"Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic","authors":"Le-Chin Eugene Liu, C. Sechen","doi":"10.1109/EDTC.1997.582376","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582376","url":null,"abstract":"We present a chip-level global router based on a new, more accurate global routing model for the multi-layer macro-cell technology. The routing model uses a 3-dimensional mixed directed/undirected routing graph, which accurately models the multi-layer routing problem. However the complexity of the routing graph challenges previous route-generating algorithms. Generating the routes is to search for the Steiner minimum trees for the nets, which is an NP-hard problem. We developed an improved Steiner tree heuristic algorithm suitable for large routing graphs and able to generate high quality Steiner tree routing. Tested on industrial circuits, our algorithm yields comparable results while having dramatically lower time and space complexities than the leading heuristics. While minimizing the wire length, our global router can also minimize the number of vias or solve the routing resource congestion problems.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114445613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582439
Y. Higami, K. Kinoshita
This paper presents a design-for-testability technique, called partially parallel scan chain (PPSC), which aims at reduction of test length for sequential circuits. Since the partially parallel scan chain allows to control and observe subset of flip-flops (FFs) concurrently during scan shift operations, the number of scan shift clocks is reduced.
{"title":"Design of partially parallel scan chain","authors":"Y. Higami, K. Kinoshita","doi":"10.1109/EDTC.1997.582439","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582439","url":null,"abstract":"This paper presents a design-for-testability technique, called partially parallel scan chain (PPSC), which aims at reduction of test length for sequential circuits. Since the partially parallel scan chain allows to control and observe subset of flip-flops (FFs) concurrently during scan shift operations, the number of scan shift clocks is reduced.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116743112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582323
P. Panda, N. Dutt, A. Nicolau
Efficient utilization of on-chip memory space is extremely important in modern embedded system applications based on microprocessor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called Scratch-Pad memory, is often used in several applications. We present a technique for efficiently exploiting on-chip Scratch-Pad memory by partitioning the application's scalar and array variables into off-chip DRAM and on-chip Scratch-Pad SRAM, with the goal of minimizing the total execution time of embedded applications. Our experiments on code kernels from typical applications show that our technique results in significant performance improvements.
{"title":"Efficient utilization of scratch-pad memory in embedded processor applications","authors":"P. Panda, N. Dutt, A. Nicolau","doi":"10.1109/EDTC.1997.582323","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582323","url":null,"abstract":"Efficient utilization of on-chip memory space is extremely important in modern embedded system applications based on microprocessor cores. In addition to a data cache that interfaces with slower off-chip memory, a fast on-chip SRAM, called Scratch-Pad memory, is often used in several applications. We present a technique for efficiently exploiting on-chip Scratch-Pad memory by partitioning the application's scalar and array variables into off-chip DRAM and on-chip Scratch-Pad SRAM, with the goal of minimizing the total execution time of embedded applications. Our experiments on code kernels from typical applications show that our technique results in significant performance improvements.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126961128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582357
J. Fradin, L. Molla, B. Desaunettes
An efficient method for the analysis of real 3D conjugate heat transfer for electronic devices is presented. This methodology is based on the coupling of two software: a conductive software based on the Boundary Element Method (REBECA-3D(R)) and a convective software based on the Volume Finite Method (FLUENT). The methodology is tested on a Multi Chip Module (CPGA224) for which experiments have been performed by the CNRS (French National Center for Scientific Research).
{"title":"Analysis of 3D conjugate heat transfers in electronics","authors":"J. Fradin, L. Molla, B. Desaunettes","doi":"10.1109/EDTC.1997.582357","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582357","url":null,"abstract":"An efficient method for the analysis of real 3D conjugate heat transfer for electronic devices is presented. This methodology is based on the coupling of two software: a conductive software based on the Boundary Element Method (REBECA-3D(R)) and a convective software based on the Volume Finite Method (FLUENT). The methodology is tested on a Multi Chip Module (CPGA224) for which experiments have been performed by the CNRS (French National Center for Scientific Research).","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"87 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123568015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582391
A. Bogliolo, L. Benini, G. Micheli
In this work we propose an effective solution to the main challenges of behavioral power modeling: the generation of models for the power dissipation of technology-independent soft macros and the strong dependence of power from input pattern statistics. Our methodology is based on a fast characterization performed by simulating the gate-level implementation of instances of soft macros within the behavioral description of the complete design. Once characterization has been completed, the backannotated behavioral model replaces the gate-level representation, thus allowing fast but accurate power estimates in a fully behavioral context. Our power characterization procedure is a very efficient process that can be easily embedded in synthesis-based design flows. No additional effort is required from the designer, since power characterization merges seamlessly with a natural top-down design methodology with iterative improvement. After characterization, the behavioral power simulation produces accurate average and instantaneous pourer estimates (with errors around 7% and 25%, respectively, from accurate gate-level power simulation).
{"title":"Adaptive least mean square behavioral power modeling","authors":"A. Bogliolo, L. Benini, G. Micheli","doi":"10.1109/EDTC.1997.582391","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582391","url":null,"abstract":"In this work we propose an effective solution to the main challenges of behavioral power modeling: the generation of models for the power dissipation of technology-independent soft macros and the strong dependence of power from input pattern statistics. Our methodology is based on a fast characterization performed by simulating the gate-level implementation of instances of soft macros within the behavioral description of the complete design. Once characterization has been completed, the backannotated behavioral model replaces the gate-level representation, thus allowing fast but accurate power estimates in a fully behavioral context. Our power characterization procedure is a very efficient process that can be easily embedded in synthesis-based design flows. No additional effort is required from the designer, since power characterization merges seamlessly with a natural top-down design methodology with iterative improvement. After characterization, the behavioral power simulation produces accurate average and instantaneous pourer estimates (with errors around 7% and 25%, respectively, from accurate gate-level power simulation).","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125776438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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