Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582423
S. Turgis, J. Daga, J. Portal, D. Auvergne
We present in this paper an alternative for the internal (short-circuit and overshoot) power dissipation estimation of CMOS structures. Using a first order macro-modelling, we consider submicronic additional effects such as: input slow dependency of short-circuit currents and input-to-output coupling. Considering an equivalent capacitance concept we directly compare the different power components. Validations are presented by comparing simulated values (HSPICE level 6, foundry model 0.7 /spl mu/m) to calculated ones. Application to buffer design enlightens the importance of the internal power component and clearly shows that common sizing alternatives for power and delay minimization can be considered.
本文提出了CMOS结构内部(短路和超调)功耗估计的一种替代方法。使用一阶宏观模型，我们考虑了亚微米附加效应，如:短路电流的输入慢依赖和输入输出耦合。考虑到等效电容的概念，我们直接比较了不同的功率元件。通过将模拟值(HSPICE level 6, foundry model 0.7 /spl mu/m)与计算值进行比较，提出了验证。在缓冲器设计中的应用启发了内部功率元件的重要性，并清楚地表明可以考虑最小化功率和延迟的通用尺寸选择。
{"title":"Internal power modelling and minimization in CMOS inverters","authors":"S. Turgis, J. Daga, J. Portal, D. Auvergne","doi":"10.1109/EDTC.1997.582423","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582423","url":null,"abstract":"We present in this paper an alternative for the internal (short-circuit and overshoot) power dissipation estimation of CMOS structures. Using a first order macro-modelling, we consider submicronic additional effects such as: input slow dependency of short-circuit currents and input-to-output coupling. Considering an equivalent capacitance concept we directly compare the different power components. Validations are presented by comparing simulated values (HSPICE level 6, foundry model 0.7 /spl mu/m) to calculated ones. Application to buffer design enlightens the importance of the internal power component and clearly shows that common sizing alternatives for power and delay minimization can be considered.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"11 suppl_1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123015314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582394
S. Chiusano, Fulvio Corno, P. Prinetto, M. Reorda
This paper presents an algorithmic technique based on hybridizing Symbolic Manipulation Techniques based on BDDs with more traditional Explicit solving algorithms. To validate the approach, the graph coloring problem has been selected as a hard-to-solve problem, and an optimized solution based on hybrid techniques has been implemented. Experimental results on a set of benchmarks derived from the CAD for VLSI area show the applicability of the approach to graphs with millions of vertices in a limited CPU time.
{"title":"Hybrid symbolic-explicit techniques for the graph coloring problem","authors":"S. Chiusano, Fulvio Corno, P. Prinetto, M. Reorda","doi":"10.1109/EDTC.1997.582394","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582394","url":null,"abstract":"This paper presents an algorithmic technique based on hybridizing Symbolic Manipulation Techniques based on BDDs with more traditional Explicit solving algorithms. To validate the approach, the graph coloring problem has been selected as a hard-to-solve problem, and an optimized solution based on hybrid techniques has been implemented. Experimental results on a set of benchmarks derived from the CAD for VLSI area show the applicability of the approach to graphs with millions of vertices in a limited CPU time.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582417
A. Benso, P. Prinetto, M. Rebaudengo, M. Reorda, R. Ubar
In this paper a new approach is presented to build a list of faults to be used by the fault injection environment; the list is built starting from a high-level description of the system. The approach especially aims at identifying malicious faults, i.e. faults having a critical impact on the system reliability. To overcome the complexity problem inherent in low-level descriptions, high-level ones are exploited, and alternative graphs are applied to carry our the cause-effect analysis, to build up a fault tree and to carry out fault collapsing. The reduced high-level malicious fault list is converted so that it can be used together with the low level description for the final fault injection.
{"title":"A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs","authors":"A. Benso, P. Prinetto, M. Rebaudengo, M. Reorda, R. Ubar","doi":"10.1109/EDTC.1997.582417","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582417","url":null,"abstract":"In this paper a new approach is presented to build a list of faults to be used by the fault injection environment; the list is built starting from a high-level description of the system. The approach especially aims at identifying malicious faults, i.e. faults having a critical impact on the system reliability. To overcome the complexity problem inherent in low-level descriptions, high-level ones are exploited, and alternative graphs are applied to carry our the cause-effect analysis, to build up a fault tree and to carry out fault collapsing. The reduced high-level malicious fault list is converted so that it can be used together with the low level description for the final fault injection.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128806087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582386
P. Walker, Sumit Ghosh
In digital circuit simulation hidden opportunities for concurrent execution of models often exist, arising from the propagation delay associated with the generation of output events by the circuit models. An event prediction algorithm is developed to identify such parallelism, increasing the simulation execution rate. The algorithm uses an event prediction network and simulates circuits asynchronously and deadlock free, while honoring the preemptive semantics associated with digital circuit simulation.
{"title":"Exploiting temporal independence in distributed preemptive circuit simulation","authors":"P. Walker, Sumit Ghosh","doi":"10.1109/EDTC.1997.582386","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582386","url":null,"abstract":"In digital circuit simulation hidden opportunities for concurrent execution of models often exist, arising from the propagation delay associated with the generation of output events by the circuit models. An event prediction algorithm is developed to identify such parallelism, increasing the simulation execution rate. The algorithm uses an event prediction network and simulates circuits asynchronously and deadlock free, while honoring the preemptive semantics associated with digital circuit simulation.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129044049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582358
R. Tangelder, Guido Diemel, H. Kerkhoff
A fully integrable electronic compass has been designed based on the pulse position method, using micro-machined fluxgate magnetic sensors. The compass has been designed to have an accuracy of one degree. The analogue and digital circuitry in the system fit on a single Sea-of-Gates array of 200 k transistors. Together with the sensors it will be combined on a single MCM.
{"title":"Smart sensor system application: an integrated compass","authors":"R. Tangelder, Guido Diemel, H. Kerkhoff","doi":"10.1109/EDTC.1997.582358","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582358","url":null,"abstract":"A fully integrable electronic compass has been designed based on the pulse position method, using micro-machined fluxgate magnetic sensors. The compass has been designed to have an accuracy of one degree. The analogue and digital circuitry in the system fit on a single Sea-of-Gates array of 200 k transistors. Together with the sensors it will be combined on a single MCM.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115367120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582385
M. Shoji, F. Hirose, S. Shimogori, Satoshi Kowatari, Hiroshi Nagai
Behavioral simulation is faster than gate-level logic simulation, however the simulation speed is too slow for large systems. Simulation specific machines accelerate simulation by parallel processing. We developed the method to extract parallelism from behavioral descriptions for fast simulation utilizing these machines. We evaluated our methods utilizing CAD accelerator TP5000. By the extraction of the parallelism the simulation speed is accelerated by about 7 times.
{"title":"Acceleration of behavioral simulation on simulation specific machines","authors":"M. Shoji, F. Hirose, S. Shimogori, Satoshi Kowatari, Hiroshi Nagai","doi":"10.1109/EDTC.1997.582385","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582385","url":null,"abstract":"Behavioral simulation is faster than gate-level logic simulation, however the simulation speed is too slow for large systems. Simulation specific machines accelerate simulation by parallel processing. We developed the method to extract parallelism from behavioral descriptions for fast simulation utilizing these machines. We evaluated our methods utilizing CAD accelerator TP5000. By the extraction of the parallelism the simulation speed is accelerated by about 7 times.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125471212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582371
B. Laquai, H. Richter, H. Werkmann
The paper describes a measurement method to perform an iddq test on each vector of a test pattern. The measurement is performed using the functional test mode of a digital tester. Vector rates between 100 KHz and 10 MHz yield a current resolution of 10 uA to 100 uA. The great advantage of the method is that the measurements are performed by using only the tester's pin electronic and the existing control software. No additional equipment is neccessary and the setup of the loadboard is made without any additional components except a buffering capacitance for the device, if needed. The application of the method to the iddq test of an 8 bit microcontroller is described.
{"title":"A production-oriented measurement method for fast and exhaustive Iddq tests","authors":"B. Laquai, H. Richter, H. Werkmann","doi":"10.1109/EDTC.1997.582371","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582371","url":null,"abstract":"The paper describes a measurement method to perform an iddq test on each vector of a test pattern. The measurement is performed using the functional test mode of a digital tester. Vector rates between 100 KHz and 10 MHz yield a current resolution of 10 uA to 100 uA. The great advantage of the method is that the measurements are performed by using only the tester's pin electronic and the existing control software. No additional equipment is neccessary and the setup of the loadboard is made without any additional components except a buffering capacitance for the device, if needed. The application of the method to the iddq test of an 8 bit microcontroller is described.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121527824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582408
I. Pomeranz, S. Reddy
Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In a genetic optimization procedure, the crossover operator accepts two test patterns t/sub 1/ and t/sub 2/, and randomly copies parts of t/sub 1/ and parts of t/sub 2/ into one or more new test patterns. Such a procedure does not take advantage of circuit properties that may aid in generating more effective test patterns. In this work, we propose a representation of test patterns where subsets of inputs are considered as indivisible entities. Using this representation, crossover copies all the values of each subset either from t/sub 1/ or from t/sub 2/. By keeping input subsets undivided, activation and propagation capabilities of t/sub 1/ and t/sub 2/ are captured and carried over to the new test patterns. The effectiveness of this scheme is demonstrated by experimental results.
{"title":"On improving genetic optimization based test generation","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/EDTC.1997.582408","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582408","url":null,"abstract":"Test generation procedures based on genetic optimization were shown to be effective in achieving high fault coverage for benchmark circuits. In a genetic optimization procedure, the crossover operator accepts two test patterns t/sub 1/ and t/sub 2/, and randomly copies parts of t/sub 1/ and parts of t/sub 2/ into one or more new test patterns. Such a procedure does not take advantage of circuit properties that may aid in generating more effective test patterns. In this work, we propose a representation of test patterns where subsets of inputs are considered as indivisible entities. Using this representation, crossover copies all the values of each subset either from t/sub 1/ or from t/sub 2/. By keeping input subsets undivided, activation and propagation capabilities of t/sub 1/ and t/sub 2/ are captured and carried over to the new test patterns. The effectiveness of this scheme is demonstrated by experimental results.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122070056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582334
C. Dufaza, Y. Zorian
Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.
{"title":"On the generation of pseudo-deterministic two-patterns test sequence with LFSRs","authors":"C. Dufaza, Y. Zorian","doi":"10.1109/EDTC.1997.582334","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582334","url":null,"abstract":"Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"606 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131586764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-03-17DOI: 10.1109/EDTC.1997.582369
V. Stopjaková, H. Manhaeve
In this paper, a quiescent built-in current (BIC) monitor based on a second generation current conveyor CCII+ is presented. The monitor circuit minimises the power supply voltage degradation and provides a sensitive detection of defects that cause an elevated value of the I/sub DDQ/ current The proposed monitor offers an accurate current measurement and has a wide operation range. The CCII+ based current monitor is able to handle huge digital ASICs. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design was implemented through Alcatel-Mietec 0.7 /spl mu/m CMOS technology and an evaluation of the prototype chips has been carried out. An experimental application of the proposed monitor in new analogue self-test structure was considered.
本文介绍了一种基于第二代电流输送器CCII+的静态内置电流监测仪。监测电路最大限度地减少了电源电压下降，并提供了一个敏感的缺陷检测，导致I/sub DDQ/电流升高的值。建议的监测提供了一个准确的电流测量，并具有广泛的工作范围。基于CCII+的电流监视器能够处理巨大的数字asic。讨论了总结电路的可能性和局限性的重要结果。该设计通过Alcatel-Mietec 0.7 /spl μ m CMOS技术实现，并对原型芯片进行了评估。考虑了该监测器在新型模拟自检结构中的实验应用。
{"title":"CCII+ current conveyor based BIC monitor for I/sub DDQ/ testing of complex CMOS circuits","authors":"V. Stopjaková, H. Manhaeve","doi":"10.1109/EDTC.1997.582369","DOIUrl":"https://doi.org/10.1109/EDTC.1997.582369","url":null,"abstract":"In this paper, a quiescent built-in current (BIC) monitor based on a second generation current conveyor CCII+ is presented. The monitor circuit minimises the power supply voltage degradation and provides a sensitive detection of defects that cause an elevated value of the I/sub DDQ/ current The proposed monitor offers an accurate current measurement and has a wide operation range. The CCII+ based current monitor is able to handle huge digital ASICs. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design was implemented through Alcatel-Mietec 0.7 /spl mu/m CMOS technology and an evaluation of the prototype chips has been carried out. An experimental application of the proposed monitor in new analogue self-test structure was considered.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122242993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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