Trusted platforms have been proposed as a promising approach to enhance the security of general-purpose computing systems. However, for many resource-constrained embedded systems, the size and cost overheads of a separate trusted platform module (TPM) chip are not acceptable. One alternative is to use a software-based TPM (SW-TPM), which implements TPM functions using software that executes in a protected execution domain on the embedded processor itself. However, since many embedded systems have limited processing capabilities and are battery-powered, it is also important to ensure that the computational and energy requirements for SW-TPMs are acceptable. In this work, an evaluation of the energy and execution time overheads for a SW-TPM implementation on a Sharp Zaurus PDA was performed. The execution time and energy required by each TPM command was characterized through actual measurements on the target platform. In addition, the overheads of using SW-TPM in the context of various end applications, including trusted boot of the Linux operating system (OS), secure file storage, secure VoIP client, and secure Web browser was also evaluated. Furthermore, it was observed that for most TPM commands, the overheads are primarily due to the use of 2048-bit RSA operations that are performed within SW-TPM. In order to alleviate SW-TPM overheads, the use of elliptic curve cryptography (ECC) as a replacement for the RSA algorithm specified in the trusted computing group (TCG) standards was evaluated. Experiments indicate that this optimization can significantly reduce SW-TPM overheads (an average of 6.51times execution time reduction and 6.75times energy consumption reduction for individual TPM commands, and an average of 10.25times execution time reduction and 10.75times energy consumption reduction for applications). This work demonstrates that ECC-based SW-TPMs are a viable approach to realizing the benefits of trusted computing in resource-constrained embedded systems
{"title":"Energy and Execution Time Analysis of a Software-based Trusted Platform Module","authors":"N. Aaraj, A. Raghunathan, S. Ravi, N. Jha","doi":"10.1145/1266366.1266610","DOIUrl":"https://doi.org/10.1145/1266366.1266610","url":null,"abstract":"Trusted platforms have been proposed as a promising approach to enhance the security of general-purpose computing systems. However, for many resource-constrained embedded systems, the size and cost overheads of a separate trusted platform module (TPM) chip are not acceptable. One alternative is to use a software-based TPM (SW-TPM), which implements TPM functions using software that executes in a protected execution domain on the embedded processor itself. However, since many embedded systems have limited processing capabilities and are battery-powered, it is also important to ensure that the computational and energy requirements for SW-TPMs are acceptable. In this work, an evaluation of the energy and execution time overheads for a SW-TPM implementation on a Sharp Zaurus PDA was performed. The execution time and energy required by each TPM command was characterized through actual measurements on the target platform. In addition, the overheads of using SW-TPM in the context of various end applications, including trusted boot of the Linux operating system (OS), secure file storage, secure VoIP client, and secure Web browser was also evaluated. Furthermore, it was observed that for most TPM commands, the overheads are primarily due to the use of 2048-bit RSA operations that are performed within SW-TPM. In order to alleviate SW-TPM overheads, the use of elliptic curve cryptography (ECC) as a replacement for the RSA algorithm specified in the trusted computing group (TCG) standards was evaluated. Experiments indicate that this optimization can significantly reduce SW-TPM overheads (an average of 6.51times execution time reduction and 6.75times energy consumption reduction for individual TPM commands, and an average of 10.25times execution time reduction and 10.75times energy consumption reduction for applications). This work demonstrates that ECC-based SW-TPMs are a viable approach to realizing the benefits of trusted computing in resource-constrained embedded systems","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115884331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364668
H. Moussa, O. Muller, A. Baghdadi, M. Jézéquel
Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Besides application algorithm optimizations and application-specific instruction-set processor design, the on-chip communication network constitutes a major issue in this application domain. In this paper, the authors propose to use multistage interconnection networks as on-chip communication networks for parallel turbo decoding. Adapted benes and butterfly networks are proposed with detailed hardware implementation of network interfaces, routers, and topologies. In addition, appropriate packet format and routing for interleaved/deinterleaved extrinsic information exchanges are proposed. The flexibility of these on-chip communication networks enables their use for all turbo code standards and constitutes a promising feature for their reuse for any similar interleaved/deinterleaved iterative communication profile
{"title":"Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding","authors":"H. Moussa, O. Muller, A. Baghdadi, M. Jézéquel","doi":"10.1109/DATE.2007.364668","DOIUrl":"https://doi.org/10.1109/DATE.2007.364668","url":null,"abstract":"Several research activities have recently emerged aiming to propose multiprocessor implementations in order to achieve flexible and high throughput parallel iterative decoding. Besides application algorithm optimizations and application-specific instruction-set processor design, the on-chip communication network constitutes a major issue in this application domain. In this paper, the authors propose to use multistage interconnection networks as on-chip communication networks for parallel turbo decoding. Adapted benes and butterfly networks are proposed with detailed hardware implementation of network interfaces, routers, and topologies. In addition, appropriate packet format and routing for interleaved/deinterleaved extrinsic information exchanges are proposed. The flexibility of these on-chip communication networks enables their use for all turbo code standards and constitutes a promising feature for their reuse for any similar interleaved/deinterleaved iterative communication profile","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114750359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
W. Ecker, Volkan Esen, T. Steininger, Michael Velten, M. Hull
Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling
{"title":"Implementation of a Transaction Level Assertion Framework in SystemC","authors":"W. Ecker, Volkan Esen, T. Steininger, Michael Velten, M. Hull","doi":"10.1145/1266366.1266559","DOIUrl":"https://doi.org/10.1145/1266366.1266559","url":null,"abstract":"Current hardware design and verification methodologies reflect a trend towards abstraction levels higher than RTL, referred to as transaction level (TL). Since transaction level models (TLMs) are used for early prototyping and as reference models for the verification of their RTL representation, the quality assurance of TLMs is vital. Assertion based verification (ABV) of RTL models has improved quality assurance of IP blocks and SoC systems to a great extent. Since mapping of an RTL ABV methodology to TL poses severe problems due to different design paradigms, current ABV approaches need extensions towards TL. In this paper we present a prototype implementation of a TL assertion framework using SystemC which is currently the de facto standard for system modeling","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117126693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364402
Shan Tang, Qiang Xu
Network-on-chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in giga-scale integrated circuits. As traditional debug architecture for bus-based systems is not readily applicable to identify bugs in NoC-based systems, in this paper, we present a novel debug platform that supports concurrent debug access to the cores under debug (CUDs) and the NoC in a unified architecture. By introducing core-level debug probes in between the CUDs and their network interfaces and a system-level debug agent controlled by an off-chip multi-core debug controller, the proposed debug platform provides in-depth analysis features for NoC-based systems, such as NoC transaction analysis, multi-core cross-triggering and global synchronized timestamping. Therefore, the proposed solution is expected to facilitate the designers to identify bugs in NoC-based systems more effectively and efficiently. Experimental results show that the design-for-debug cost for the proposed technique in terms of area and traffic requirements is moderate
{"title":"A Multi-Core Debug Platform for NoC-Based Systems","authors":"Shan Tang, Qiang Xu","doi":"10.1109/DATE.2007.364402","DOIUrl":"https://doi.org/10.1109/DATE.2007.364402","url":null,"abstract":"Network-on-chip (NoC) is generally regarded as the most promising solution for the future on-chip communication scheme in giga-scale integrated circuits. As traditional debug architecture for bus-based systems is not readily applicable to identify bugs in NoC-based systems, in this paper, we present a novel debug platform that supports concurrent debug access to the cores under debug (CUDs) and the NoC in a unified architecture. By introducing core-level debug probes in between the CUDs and their network interfaces and a system-level debug agent controlled by an off-chip multi-core debug controller, the proposed debug platform provides in-depth analysis features for NoC-based systems, such as NoC transaction analysis, multi-core cross-triggering and global synchronized timestamping. Therefore, the proposed solution is expected to facilitate the designers to identify bugs in NoC-based systems more effectively and efficiently. Experimental results show that the design-for-debug cost for the proposed technique in terms of area and traffic requirements is moderate","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117146165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364675
Robert Lissel, J. Gerlach
Today the task of design verification has become one of the key bottlenecks in hardware and system design. To address this topic, several verification languages, methods and tools, which address several issues of the verification process, were developed by multiple EDA vendors over the last years. This paper takes an industrial user's point of view and explores the difficulties introducing new verification methods into a company's "naturally grown" and well established design flow - taking into account application domain specific requirements, constraints given by the existing design environment and economical aspects. The presented approach extends the capabilities of an existing verification strategy by powerful new features while keeping in mind integration, reuse and applicability aspects. Based on an industrial design example the effectiveness and potential of the developed approach is shown
{"title":"Introducing New Verification Methods into a Company's Design Flow: An Industrial User's Point of View","authors":"Robert Lissel, J. Gerlach","doi":"10.1109/DATE.2007.364675","DOIUrl":"https://doi.org/10.1109/DATE.2007.364675","url":null,"abstract":"Today the task of design verification has become one of the key bottlenecks in hardware and system design. To address this topic, several verification languages, methods and tools, which address several issues of the verification process, were developed by multiple EDA vendors over the last years. This paper takes an industrial user's point of view and explores the difficulties introducing new verification methods into a company's \"naturally grown\" and well established design flow - taking into account application domain specific requirements, constraints given by the existing design environment and economical aspects. The presented approach extends the capabilities of an existing verification strategy by powerful new features while keeping in mind integration, reuse and applicability aspects. Based on an industrial design example the effectiveness and potential of the developed approach is shown","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121957591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the widespread demands for efficient SAT solvers in electronic design automation applications, methods to boost the performance of the SAT solver are highly desired. The paper proposed a hybrid solution to boost SAT solver performance in this paper, via an integration of local and DPLL-based search approaches. A local search is used to identify a subset of clauses to be passed to a DPLL SAT solver through an incremental interface. In addition, the solution obtained by the DPLL solver on the subset of clauses is fed back to the local search solver to jump over any locally optimal points. The proposed solution is highly portable to the existing SAT solvers. For satisfiable instances, up to an order of magnitude speedup can be obtained via the proposed hybrid solver
{"title":"A New Hybrid Solution to Boost SAT Solver Performance","authors":"Lei Fang, M. Hsiao","doi":"10.1145/1266366.1266652","DOIUrl":"https://doi.org/10.1145/1266366.1266652","url":null,"abstract":"Due to the widespread demands for efficient SAT solvers in electronic design automation applications, methods to boost the performance of the SAT solver are highly desired. The paper proposed a hybrid solution to boost SAT solver performance in this paper, via an integration of local and DPLL-based search approaches. A local search is used to identify a subset of clauses to be passed to a DPLL SAT solver through an incremental interface. In addition, the solution obtained by the DPLL solver on the subset of clauses is fed back to the local search solver to jump over any locally optimal points. The proposed solution is highly portable to the existing SAT solvers. For satisfiable instances, up to an order of magnitude speedup can be obtained via the proposed hybrid solver","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"158 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124491161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper is in two parts, to elaborate the two pillars of technology transfer in the context of the aeronautics and space industry. The first part illustrates the methodological pillar, showing the state of the art in the industrial approaches to technology transfer. The second part illustrates the technological pillar, giving an overview of recent successes in technology transfer and emerging trends and opportunities, for both hardware and software. These two pillars are further mirrored in the two technical sessions
{"title":"Tutorial: The Methodological and Technological Dimensions of Technology Transfer for Embedded Systems in Aeronautics and Space","authors":"Thierry Pardessus, H. Daembkes, Richard Arning","doi":"10.1145/1266366.1266605","DOIUrl":"https://doi.org/10.1145/1266366.1266605","url":null,"abstract":"This paper is in two parts, to elaborate the two pillars of technology transfer in the context of the aeronautics and space industry. The first part illustrates the methodological pillar, showing the state of the art in the industrial approaches to technology transfer. The second part illustrates the technological pillar, giving an overview of recent successes in technology transfer and emerging trends and opportunities, for both hardware and software. These two pillars are further mirrored in the two technical sessions","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125949235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364599
G. A. Sammane, M. Zaki, S. Tahar
The paper proposed a new symbolic verification methodology for proving the properties of analog and mixed signal (AMS) designs. Starting with an AMS description and a set of properties and using symbolic computation, a normal mathematical representation was extracted for the system in terms of recurrence equations. These normalized equations are used along with an induction verification strategy defined inside the computer algebra system Mathematica to prove the correctness of the properties. The methodology was applied on a third order DeltaSigma modulator
{"title":"A Symbolic Methodology for the Verification of Analog and Mixed Signal Designs","authors":"G. A. Sammane, M. Zaki, S. Tahar","doi":"10.1109/DATE.2007.364599","DOIUrl":"https://doi.org/10.1109/DATE.2007.364599","url":null,"abstract":"The paper proposed a new symbolic verification methodology for proving the properties of analog and mixed signal (AMS) designs. Starting with an AMS description and a set of properties and using symbolic computation, a normal mathematical representation was extracted for the system in terms of recurrence equations. These normalized equations are used along with an induction verification strategy defined inside the computer algebra system Mathematica to prove the correctness of the properties. The methodology was applied on a third order DeltaSigma modulator","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129872679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364569
V. Aggarwal, Una-May O’Reilly
The paper presents an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the geometric programming flow for automatic circuit sizing. The models are reusable for multiple circuits on a given silicon technology and hence don't adversely affect the scalability of the geometric programming approach. The proposed method is a combination of genetic algorithms and quadratic programming. It is the only approach for posynomial modeling with real-valued exponents which is easily extensible to different error metrics. The authors compare the proposed technique with state-of-art posynomial/monomial modeling techniques and show its superiority
{"title":"Simulation-based reusable posynomial models for MOS transistor parameters","authors":"V. Aggarwal, Una-May O’Reilly","doi":"10.1109/DATE.2007.364569","DOIUrl":"https://doi.org/10.1109/DATE.2007.364569","url":null,"abstract":"The paper presents an algorithm to automatically design posynomial models for parameters of the MOS transistors using simulation data. These models improve the accuracy of the geometric programming flow for automatic circuit sizing. The models are reusable for multiple circuits on a given silicon technology and hence don't adversely affect the scalability of the geometric programming approach. The proposed method is a combination of genetic algorithms and quadratic programming. It is the only approach for posynomial modeling with real-valued exponents which is easily extensible to different error metrics. The authors compare the proposed technique with state-of-art posynomial/monomial modeling techniques and show its superiority","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128695639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364666
A. C. Nacul, F. Regazzoni, M. Lajolo
In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates
{"title":"Hardware Scheduling Support in SMP Architectures","authors":"A. C. Nacul, F. Regazzoni, M. Lajolo","doi":"10.1109/DATE.2007.364666","DOIUrl":"https://doi.org/10.1109/DATE.2007.364666","url":null,"abstract":"In this paper the authors propose a hardware real time operating system (HW-RTOS) that implements the OS layer in a dual-processor SMP architecture. Intertask communication is specified by means of dedicated APIs and the HW-RTOS takes care of the communication requirements of the application and also implements the task scheduling algorithm. The HW-RTOS allows to have smaller footprints, since it avoids the need to link to the final executables traditional software RTOS libraries. Moreover, the HW-RTOS is able to exploit the easy task migration feature provided by an SMP architecture much more efficiently than a traditional software RTOS, due to its faster execution and the authors show how this significantly overcomes the performance achievable with optimal static task partitioning among two processors. Preliminary results show that the hardware overhead in a dual processor architecture is less than 20K gates","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130181598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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