Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364678
J. Anders, Shaji Krishnan, G. Gronthoud
AC sensitivities guide most analogue automatic test pattern generator (AATPG) while determining the optimal frequencies of a sinusoidal test stimulus. The optimal frequencies thus determined, normally lie in the close vicinity of the operating frequency of the circuit. Although these frequencies are justifiable by the principles of the circuit, these test frequencies do not bring any added value to the ultimate goal of cheap alternatives (low frequency test signal and cheaper measurement equipment) for the analogue and RF tests. In this paper, we propose to re-configure the circuit blocks, in such a way that the operating frequencies of the respective sub-block are shifted to lower testable frequencies. We have validated our proposal on a sub-block of a satellite receiver circuit that resulted in lowering the test frequencies of the corresponding sub-blocks from 12 GHz to 4MHz, while attaining the same level of defect coverage
{"title":"Re-Configuration of Sub-blocks for Effective Application of Time Domain Tests","authors":"J. Anders, Shaji Krishnan, G. Gronthoud","doi":"10.1109/DATE.2007.364678","DOIUrl":"https://doi.org/10.1109/DATE.2007.364678","url":null,"abstract":"AC sensitivities guide most analogue automatic test pattern generator (AATPG) while determining the optimal frequencies of a sinusoidal test stimulus. The optimal frequencies thus determined, normally lie in the close vicinity of the operating frequency of the circuit. Although these frequencies are justifiable by the principles of the circuit, these test frequencies do not bring any added value to the ultimate goal of cheap alternatives (low frequency test signal and cheaper measurement equipment) for the analogue and RF tests. In this paper, we propose to re-configure the circuit blocks, in such a way that the operating frequencies of the respective sub-block are shifted to lower testable frequencies. We have validated our proposal on a sub-block of a satellite receiver circuit that resulted in lowering the test frequencies of the corresponding sub-blocks from 12 GHz to 4MHz, while attaining the same level of defect coverage","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"369 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133937749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364570
D. Mueller, H. Graeb, Ulf Schlichtmann
One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be optimized at cost of others, therefore a sizing must aim at an optimal trade-off between the important circuit performances. This paper presents a new deterministic method to calculate the complete range of performance trade-offs, the so-called Pareto-optimal front, of a given circuit topology. Known deterministic methods solve a set of constrained multi-objective optimization problems independently of each other. The presented method minimizes a set of goal attainment (GA) optimization problems simultaneously. In a parallel algorithm, the individual GA optimization processes compare and exchange their iterative solutions. This leads to a significant improvement in the efficiency and quality of analog trade-off design
{"title":"Trade-Off Design of Analog Circuits using Goal Attainment and \"Wave Front\" Sequential Quadratic Programming","authors":"D. Mueller, H. Graeb, Ulf Schlichtmann","doi":"10.1109/DATE.2007.364570","DOIUrl":"https://doi.org/10.1109/DATE.2007.364570","url":null,"abstract":"One of the main tasks in analog design is the sizing of the circuit parameters, such as transistor lengths and widths, in order to obtain optimal circuit performances, such as high gain or low power consumption. In most cases one performance can only be optimized at cost of others, therefore a sizing must aim at an optimal trade-off between the important circuit performances. This paper presents a new deterministic method to calculate the complete range of performance trade-offs, the so-called Pareto-optimal front, of a given circuit topology. Known deterministic methods solve a set of constrained multi-objective optimization problems independently of each other. The presented method minimizes a set of goal attainment (GA) optimization problems simultaneously. In a parallel algorithm, the individual GA optimization processes compare and exchange their iterative solutions. This leads to a significant improvement in the efficiency and quality of analog trade-off design","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131899318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The failure rate, the sources of failures and the test costs for nanometer devices are all increasing. Therefore, to create a reliable system-on-a-chip device requires designers to implement fault tolerance. However, while system-level fault tolerance could significantly relax the quality requirements of the system's building blocks, every fault-tolerant scheme only works under certain failure mechanisms and within a certain range of error probabilities. Also, designing a system with a high failure-rate component could be very expensive because the growth rate of the design complexity and the system overhead for fault tolerance could be significantly greater than the component failure rate. Therefore, it is desirable to understand the trade-offs between component test quality and system fault-tolerant capability for achieving the desired reliability under cost constraints. In this paper, the authors propose an analysis framework for system reliability considering (a) the test quality achieved by manufacturing testing, on-line self-checking, and off-line built-in self-test; (b) the fault-tolerant and spare schemes; and (c) the component defect and error probabilities. The authors demonstrate that, through proper redundancy configurations and low-cost testing to insure a certain degree of component test quality, a low-redundant system might achieve equal or higher reliability than a high-redundant system
{"title":"A Framework for System Reliability Analysis Considering Both System Error Tolerance and Component Test Quality","authors":"Sung-Jui Pan, K. Cheng","doi":"10.1145/1266366.1266714","DOIUrl":"https://doi.org/10.1145/1266366.1266714","url":null,"abstract":"The failure rate, the sources of failures and the test costs for nanometer devices are all increasing. Therefore, to create a reliable system-on-a-chip device requires designers to implement fault tolerance. However, while system-level fault tolerance could significantly relax the quality requirements of the system's building blocks, every fault-tolerant scheme only works under certain failure mechanisms and within a certain range of error probabilities. Also, designing a system with a high failure-rate component could be very expensive because the growth rate of the design complexity and the system overhead for fault tolerance could be significantly greater than the component failure rate. Therefore, it is desirable to understand the trade-offs between component test quality and system fault-tolerant capability for achieving the desired reliability under cost constraints. In this paper, the authors propose an analysis framework for system reliability considering (a) the test quality achieved by manufacturing testing, on-line self-checking, and off-line built-in self-test; (b) the fault-tolerant and spare schemes; and (c) the component defect and error probabilities. The authors demonstrate that, through proper redundancy configurations and low-cost testing to insure a certain degree of component test quality, a low-redundant system might achieve equal or higher reliability than a high-redundant system","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114444886","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364593
Oliver Spang, Hans Martin von Staudt, M. Wahl
Economic testing of small devices like LCD drivers is a real challenge. In this paper we describe an approach where a production tester is extended by a memory test engine (MTE). This MTE, which consists of hardware and software components allows testing the LCD driver memory at speed, allowing at the same time the concurrent execution of other tests. It is fully integrated into the tester. The MTE leads to a significant increase of memory test quality and at the same time to a significant reduction of the test time. The test time reduction that was achieved by executing the memory test in parallel to other analog tests lead to the test cost reduction, which was the impetus for developing the MTE
{"title":"A Sophisticated Memory Test Engine for LCD Display Drivers","authors":"Oliver Spang, Hans Martin von Staudt, M. Wahl","doi":"10.1109/DATE.2007.364593","DOIUrl":"https://doi.org/10.1109/DATE.2007.364593","url":null,"abstract":"Economic testing of small devices like LCD drivers is a real challenge. In this paper we describe an approach where a production tester is extended by a memory test engine (MTE). This MTE, which consists of hardware and software components allows testing the LCD driver memory at speed, allowing at the same time the concurrent execution of other tests. It is fully integrated into the tester. The MTE leads to a significant increase of memory test quality and at the same time to a significant reduction of the test time. The test time reduction that was achieved by executing the memory test in parallel to other analog tests lead to the test cost reduction, which was the impetus for developing the MTE","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125642662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nonvolatile flash memories are becoming more and more popular in systems-on-chip (SoC). Embedded flash (eFlash) memories are based on the well-known floating-gate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as error correction code (ECC), redundancy or threshold voltage (VT ) analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed
{"title":"Evaluation of Design for Reliability Techniques in Embedded Flash Memories","authors":"B. Godard, J. Daga, L. Torres, G. Sassatelli","doi":"10.1145/1266366.1266716","DOIUrl":"https://doi.org/10.1145/1266366.1266716","url":null,"abstract":"Nonvolatile flash memories are becoming more and more popular in systems-on-chip (SoC). Embedded flash (eFlash) memories are based on the well-known floating-gate transistor concept. The reliability of such type of technology is a growing up issue for embedded systems; endurance and retention are of course the main features to analyze. To enhance memory reliability current eFlash memories designs use techniques such as error correction code (ECC), redundancy or threshold voltage (VT ) analysis. In this paper, a memory model to evaluate the reliability of eFlash memory arrays under distinct enhancement schemes is developed","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132416759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364602
J. Lataire, G. Vandersteen, R. Pintelon
Nonlinear distortions in submicron analog circuits are gaining importance, especially when power constraints are imposed and when operating in moderate inversion. This paper proposes a method to optimize the design of analog filters for minimum noise and nonlinear distortions. For this purpose a technique is presented for quantifying these nonlinearities, such that their influence can be compared with that of the system noise. Having quantified the non-idealities, an optimization can be carried out which involves the tuning of design parameters
{"title":"Optimizing Analog Filter Designs for Minimum Nonlinear Distortions Using Multisine Excitations","authors":"J. Lataire, G. Vandersteen, R. Pintelon","doi":"10.1109/DATE.2007.364602","DOIUrl":"https://doi.org/10.1109/DATE.2007.364602","url":null,"abstract":"Nonlinear distortions in submicron analog circuits are gaining importance, especially when power constraints are imposed and when operating in moderate inversion. This paper proposes a method to optimize the design of analog filters for minimum noise and nonlinear distortions. For this purpose a technique is presented for quantifying these nonlinearities, such that their influence can be compared with that of the system noise. Having quantified the non-idealities, an optimization can be carried out which involves the tuning of design parameters","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"5 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129087933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364619
Kim Petersén, Johnny Öberg
This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%
{"title":"Toward a Scalable Test Methodology for 2D-mesh Network-on-Chips","authors":"Kim Petersén, Johnny Öberg","doi":"10.1109/DATE.2007.364619","DOIUrl":"https://doi.org/10.1109/DATE.2007.364619","url":null,"abstract":"This paper presents a BIST strategy for testing the NoC interconnect network, and investigates if the strategy is a suitable approach for the task. All switches and links in the NoC are tested with BIST, running at full clock-speed, and in a functional-like mode. The BIST is carried out as a go/no-go BIST operation at start up, or on command. It is shown that the proposed methodology can be applied for different implementations of deflecting switches, and that the test time is limited to a few thousand-clock cycles with fault coverage close to 100%","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"360 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131519564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364398
B. Jang, Y. Kim, F. Lombardi
This paper proposes a novel technique based on profiling the monomers for reducing the error rate in DNA self-assembly. This technique utilizes the average concentration of the monomers (tiles) for a specific pattern as found by profiling its growth. The validity of profiling and the large difference in the concentrations of the monomers are shown to be applicable to different tile sets. To evaluate the error rate new Markov based models are proposed to account for the different types of bonding (i.e. single, double and triple) in the monomers as modification to the commonly assumed kinetic trap model. A significant error rates reduction is accomplished compared to a scheme with constant concentration as commonly utilized under the kinetic trap model. Simulation results are provided
{"title":"Error Rate Reduction in DNA Self-Assembly by Non-Constant Monomer Concentrations and Profiling","authors":"B. Jang, Y. Kim, F. Lombardi","doi":"10.1109/DATE.2007.364398","DOIUrl":"https://doi.org/10.1109/DATE.2007.364398","url":null,"abstract":"This paper proposes a novel technique based on profiling the monomers for reducing the error rate in DNA self-assembly. This technique utilizes the average concentration of the monomers (tiles) for a specific pattern as found by profiling its growth. The validity of profiling and the large difference in the concentrations of the monomers are shown to be applicable to different tile sets. To evaluate the error rate new Markov based models are proposed to account for the different types of bonding (i.e. single, double and triple) in the monomers as modification to the commonly assumed kinetic trap model. A significant error rates reduction is accomplished compared to a scheme with constant concentration as commonly utilized under the kinetic trap model. Simulation results are provided","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132336803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364430
S. Mamagkakis, D. Soudris, F. Catthoor
Today, wireless networks are moving big amounts of data between mobile devices, which have to work in an ubiquitous computing environment, which perpetually changes at run-time (i.e., nodes log on and off, varied user activity, etc.). These changes introduce problems that can not be fully analyzed at design-time and require dynamic (runtime) solutions. These solutions are implemented with the use of run-time resource management at the middleware level for a wide variety of embedded systems. In this paper, the authors motivate and propose the characterization of the dynamic inputs of wireless protocols (e.g., input to the IEEE 802.11b protocol coming from IPv4 data fragmentation). Thus, through statistical analysis, patterns were derived that will guide the optimization process of the middleware for run-time resource management design. The effectiveness of the approach was assessed with inputs of 18 real life case studies of wireless networks. Finally, an increase in the performance of the proposed design solution of up to 81.97% compared to the state-of-the-art solutions was shown, without compromising memory footprint or energy consumption
{"title":"Middleware Design Optimization of Wireless Protocols Based on the Exploitation of Dynamic Input Patterns","authors":"S. Mamagkakis, D. Soudris, F. Catthoor","doi":"10.1109/DATE.2007.364430","DOIUrl":"https://doi.org/10.1109/DATE.2007.364430","url":null,"abstract":"Today, wireless networks are moving big amounts of data between mobile devices, which have to work in an ubiquitous computing environment, which perpetually changes at run-time (i.e., nodes log on and off, varied user activity, etc.). These changes introduce problems that can not be fully analyzed at design-time and require dynamic (runtime) solutions. These solutions are implemented with the use of run-time resource management at the middleware level for a wide variety of embedded systems. In this paper, the authors motivate and propose the characterization of the dynamic inputs of wireless protocols (e.g., input to the IEEE 802.11b protocol coming from IPv4 data fragmentation). Thus, through statistical analysis, patterns were derived that will guide the optimization process of the middleware for run-time resource management design. The effectiveness of the approach was assessed with inputs of 18 real life case studies of wireless networks. Finally, an increase in the performance of the proposed design solution of up to 81.97% compared to the state-of-the-art solutions was shown, without compromising memory footprint or energy consumption","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133919262","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-04-16DOI: 10.1109/DATE.2007.364653
N. H. Zamora, Jung-Chun Kao, R. Marculescu
Wireless sensor networks operating on limited energy resources need to be power efficient to extend the system lifetime. This is especially challenging for video sensor networks due to the large volumes of data they need to process in short periods of time. Towards this end, this paper proposes two coordinated power management policies for video sensor networks. These policies are scalable as the system grows and flexible to video parameters and network characteristics. In addition to simulation results, the prototype demonstrates the feasibility of implementing these policies. Finally, the analytical framework we provide gives an upper bound for the achievable sleep fraction and insight into how adjusting select parameters will affect the performance of the power management policies
{"title":"Distributed Power-Management Techniques for Wireless Network Video Systems","authors":"N. H. Zamora, Jung-Chun Kao, R. Marculescu","doi":"10.1109/DATE.2007.364653","DOIUrl":"https://doi.org/10.1109/DATE.2007.364653","url":null,"abstract":"Wireless sensor networks operating on limited energy resources need to be power efficient to extend the system lifetime. This is especially challenging for video sensor networks due to the large volumes of data they need to process in short periods of time. Towards this end, this paper proposes two coordinated power management policies for video sensor networks. These policies are scalable as the system grows and flexible to video parameters and network characteristics. In addition to simulation results, the prototype demonstrates the feasibility of implementing these policies. Finally, the analytical framework we provide gives an upper bound for the achievable sleep fraction and insight into how adjusting select parameters will affect the performance of the power management policies","PeriodicalId":298961,"journal":{"name":"2007 Design, Automation & Test in Europe Conference & Exhibition","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133485665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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