Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012476
S. W. Miller, D.G. Wang
Stacking two tubeaxial fans in series can simultaneously achieve fan redundancy, high airflow delivery and high packaging density. However, the impact of packing two fans together on overall noise emissions is far from well defined and much less well understood as compared to noise emission from isolated fans. This study demonstrates that spacing between two series fans has a significant impact on overall acoustic noise emissions. Using sound power measured for two tightly bolted 120 mm Nidec fans as a reference, a noise reduction of 5 dB can be achieved by separating two fans 40 mm apart when the air channel between two fans is enclosed. The overall sound power can further be reduced by nearly 3 dB when the channel between two series fans is open to ambient. The impact of open/closed channel and spacing on overall volumetric airflow is also investigated for normal operation and various fan failure scenarios. Flow degradation becomes obvious only in certain fan failure scenarios with the biggest impact observed for downstream fan failure with its fan blades locked at the maximum spacing.
两台管轴风机串联堆叠，可同时实现风机冗余、大气流输送和高包装密度。然而，与孤立风扇的噪声排放相比，将两个风扇包装在一起对总体噪声排放的影响远没有很好地定义，也没有很好地理解。本研究表明，两个系列风机之间的间距对总体声噪声发射有显著影响。以两台螺栓紧固的120 mm Nidec风扇的声功率为参考，当两台风扇之间的风道被封闭时，将两台风扇分开40 mm，可实现5db的降噪。当两个系列风扇之间的通道对环境开放时，整体声音功率可以进一步降低近3db。在正常运行和各种风扇故障情况下，还研究了开/闭通道和间距对总体容积气流的影响。只有在某些风扇故障情况下，流量退化才会变得明显，其中对下游风扇故障的影响最大，风扇叶片锁定在最大间距。
{"title":"A study on acoustic noise and flow rate from two tandem tubeaxial fans","authors":"S. W. Miller, D.G. Wang","doi":"10.1109/ITHERM.2002.1012476","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012476","url":null,"abstract":"Stacking two tubeaxial fans in series can simultaneously achieve fan redundancy, high airflow delivery and high packaging density. However, the impact of packing two fans together on overall noise emissions is far from well defined and much less well understood as compared to noise emission from isolated fans. This study demonstrates that spacing between two series fans has a significant impact on overall acoustic noise emissions. Using sound power measured for two tightly bolted 120 mm Nidec fans as a reference, a noise reduction of 5 dB can be achieved by separating two fans 40 mm apart when the air channel between two fans is enclosed. The overall sound power can further be reduced by nearly 3 dB when the channel between two series fans is open to ambient. The impact of open/closed channel and spacing on overall volumetric airflow is also investigated for normal operation and various fan failure scenarios. Flow degradation becomes obvious only in certain fan failure scenarios with the biggest impact observed for downstream fan failure with its fan blades locked at the maximum spacing.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"384 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134454302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012506
R. Stout
Thermal characteristics of packaged semiconductor devices are difficult to compare, especially between suppliers and sometimes even across packages from the same supplier. Yet at a fundamental level, "standard" thermal test boards are relatively simple thermal systems characterized by just a few critical parameters, and they should respond simply and consistently to thermal inputs (that is, a heat source of certain dimensions and power level). There should be a means by which data taken on one style of board could be extrapolated quickly and reasonably accurately to any other type of standard test board. To this end, an axisymmetric thermal model (essentially a 1D cylindrical "fin") is developed and its closed-form solution expressed as a two-port network (heat flow and temperature, in and out). The resulting two-port network is utilized to describe a more complex thermal model consisting of multiple regions of differing thermal properties. Its application to thermal characterization of semiconductor devices is discussed, as an example demonstrating the relationship between so called "min pad" and "1-inch pad" device characteristics. The model is also compared to other experimental data, where the "best fit" of the axisymmetric model shows a reasonable correlation with the normalized temperature values of the experiment.
{"title":"A two-port analytical model for thermal characterization boards","authors":"R. Stout","doi":"10.1109/ITHERM.2002.1012506","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012506","url":null,"abstract":"Thermal characteristics of packaged semiconductor devices are difficult to compare, especially between suppliers and sometimes even across packages from the same supplier. Yet at a fundamental level, \"standard\" thermal test boards are relatively simple thermal systems characterized by just a few critical parameters, and they should respond simply and consistently to thermal inputs (that is, a heat source of certain dimensions and power level). There should be a means by which data taken on one style of board could be extrapolated quickly and reasonably accurately to any other type of standard test board. To this end, an axisymmetric thermal model (essentially a 1D cylindrical \"fin\") is developed and its closed-form solution expressed as a two-port network (heat flow and temperature, in and out). The resulting two-port network is utilized to describe a more complex thermal model consisting of multiple regions of differing thermal properties. Its application to thermal characterization of semiconductor devices is discussed, as an example demonstrating the relationship between so called \"min pad\" and \"1-inch pad\" device characteristics. The model is also compared to other experimental data, where the \"best fit\" of the axisymmetric model shows a reasonable correlation with the normalized temperature values of the experiment.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012454
M. June, K. Sikka
For high-power electronic packages, chip hot-spots and cross-chip temperature gradients represent a significant portion of the total thermal resistance from chip to ambient. This paper presents a technique of reducing the chip hot-spot temperatures using cap integral standoffs. The thermal benefit of the standoffs is shown experimentally and validated using thermal modeling. Thermal modeling is then extended to non-uniform power dissipation chips. Results show that the chip hot-spot temperature can be reduced by 5-10 /spl deg/C in a 100 W electronic package.
{"title":"Using cap-integral standoffs to reduce chip hot-spot temperatures in electronic packages","authors":"M. June, K. Sikka","doi":"10.1109/ITHERM.2002.1012454","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012454","url":null,"abstract":"For high-power electronic packages, chip hot-spots and cross-chip temperature gradients represent a significant portion of the total thermal resistance from chip to ambient. This paper presents a technique of reducing the chip hot-spot temperatures using cap integral standoffs. The thermal benefit of the standoffs is shown experimentally and validated using thermal modeling. Thermal modeling is then extended to non-uniform power dissipation chips. Results show that the chip hot-spot temperature can be reduced by 5-10 /spl deg/C in a 100 W electronic package.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134354115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012462
W. Jones, Y. Liu, Mingchen Gao
With projected power densities above 100 W/cm/sup 2/ for devices, new methods for thermal management from the heat generation at the die to heat removal to the ambient must be addressed. By integrating micro heat pipes directly within the ceramic substrate, effective thermal conductivity for spreading heat both in both radial and axial directions was achieved. New materials and processes were developed to fabricate the unique components required to handle high thermal loads. Enhanced thermal vias to minimize the thermal impedance through the ceramic in the evaporator and condenser sections were developed, increasing the effective thermal conductivity from 2.63 to near 250 W/m/spl deg/C. The use of an organic insert fabricated into the desired complex shape using rapid prototyping methods, coupled with the viscoelastic flow of the low temperature cofired ceramic (LTCC) during lamination, allowed complex shapes to be developed while ensuring uniform green tape density during lamination prior to tape firing. Large cavities, three dimensional fine structures and porous wicks for capillary 3D flow have, been utilized to fabricate the heat pipes. Heat pipes and spreaders, utilizing water as the working fluid, have been demonstrated operating with power densities in excess of 160 W/cm/sup 2/.
{"title":"Micro heat pipes in low temperature cofire ceramic (LTCC) substrates","authors":"W. Jones, Y. Liu, Mingchen Gao","doi":"10.1109/ITHERM.2002.1012462","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012462","url":null,"abstract":"With projected power densities above 100 W/cm/sup 2/ for devices, new methods for thermal management from the heat generation at the die to heat removal to the ambient must be addressed. By integrating micro heat pipes directly within the ceramic substrate, effective thermal conductivity for spreading heat both in both radial and axial directions was achieved. New materials and processes were developed to fabricate the unique components required to handle high thermal loads. Enhanced thermal vias to minimize the thermal impedance through the ceramic in the evaporator and condenser sections were developed, increasing the effective thermal conductivity from 2.63 to near 250 W/m/spl deg/C. The use of an organic insert fabricated into the desired complex shape using rapid prototyping methods, coupled with the viscoelastic flow of the low temperature cofired ceramic (LTCC) during lamination, allowed complex shapes to be developed while ensuring uniform green tape density during lamination prior to tape firing. Large cavities, three dimensional fine structures and porous wicks for capillary 3D flow have, been utilized to fabricate the heat pipes. Heat pipes and spreaders, utilizing water as the working fluid, have been demonstrated operating with power densities in excess of 160 W/cm/sup 2/.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134397076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012477
J. Koo, Linan Jiang, A. Bari, L. Zhang, E. Wang, T. Kenny, J. Santiago, K. Goodson
Two-phase microchannel heat sinks are promising for VLSI chip cooling, but little is known about their ability to minimize the impact of chip hotspots (regions of very high heat generation). The wall temperature distribution is governed in part by the coupling between the pressure drop and the saturation temperature, whose distributions will change in the vicinity and downstream of a region of high heat generation. This study theoretically examines the heat transfer and fluid flow characteristics of two-phase flow in microchannels with hydraulic diameters of 150/spl sim/450 micrometers for strongly varying wall heat flux conditions. The theory developed aims to help minimize the pressure drop in the two-phase region and to provide the foundation for optimizing channel dimensions to reduce temperature variations. The results suggest that a two-phase microchannel heat sink should be arranged so that downstream is located near the hotspot to minimize the pressure drop in two-phase flow region and maximum wall temperature. This work is particularly promising for a practical closed loop microchannel cooling system that competes directly with heat pipe technology and is based on an electroosmotic pump.
{"title":"Convective boiling in microchannel heat sinks with spatially-varying heat generation","authors":"J. Koo, Linan Jiang, A. Bari, L. Zhang, E. Wang, T. Kenny, J. Santiago, K. Goodson","doi":"10.1109/ITHERM.2002.1012477","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012477","url":null,"abstract":"Two-phase microchannel heat sinks are promising for VLSI chip cooling, but little is known about their ability to minimize the impact of chip hotspots (regions of very high heat generation). The wall temperature distribution is governed in part by the coupling between the pressure drop and the saturation temperature, whose distributions will change in the vicinity and downstream of a region of high heat generation. This study theoretically examines the heat transfer and fluid flow characteristics of two-phase flow in microchannels with hydraulic diameters of 150/spl sim/450 micrometers for strongly varying wall heat flux conditions. The theory developed aims to help minimize the pressure drop in the two-phase region and to provide the foundation for optimizing channel dimensions to reduce temperature variations. The results suggest that a two-phase microchannel heat sink should be arranged so that downstream is located near the hotspot to minimize the pressure drop in two-phase flow region and maximum wall temperature. This work is particularly promising for a practical closed loop microchannel cooling system that competes directly with heat pipe technology and is based on an electroosmotic pump.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129381458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012499
T. Montes de Oca, B. Joiner, T. Koschmieder
The Quad Flat No-Lead (QFN) package, with its exposed die pad soldered to the printed wiring board (PWB), has a thermal performance highly dependent on the PWB design and thermal environment. This paper documents the impact of the following changes to the PWB on the thermal performance of a 44-lead 9/spl times/9 mm QFN package: PWB overall thickness, board area, PWB internal plane thicknesses, number of plated through hole (PTH) vias, PTH via drill diameter, PTH via plating thickness, and PTH via fill material conductivity. The impact of die size and die attach conductivity is also presented in this paper. The effects of these changes are evaluated with a validated finite element model. Two thermal environments are used to evaluate these variables: (1) natural convection with radiation and (2) constant temperature on the bottom side of PWB. Results are listed using two thermal resistances: junction-to-ambient thermal resistance in natural convection on a 2s2p test board (Theta-JMA) according to EIA/JESD51-6 and junction-to-heat sink (Theta-JS) determined with the bottom of the board held at a constant temperature. Theta-JMA is most sensitive to test board area, number of PTH vias, and test board internal plane thickness. Theta-JS is most sensitive to number of PTH vias. The thermal performance of the QFN is also evaluated in two distinct arrangements meant to illustrate the application environment conditions: (1) in a 3/spl times/3 cluster on a board, and (2) on the board where it is attached to an aluminum heat rail. Heat sinking the bottom of the board allows packages to dissipate more heat for a given junction-to-ambient temperature difference than the packages that rely only on natural convection.
{"title":"Impact of board variables on the thermal performance of a QFN package","authors":"T. Montes de Oca, B. Joiner, T. Koschmieder","doi":"10.1109/ITHERM.2002.1012499","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012499","url":null,"abstract":"The Quad Flat No-Lead (QFN) package, with its exposed die pad soldered to the printed wiring board (PWB), has a thermal performance highly dependent on the PWB design and thermal environment. This paper documents the impact of the following changes to the PWB on the thermal performance of a 44-lead 9/spl times/9 mm QFN package: PWB overall thickness, board area, PWB internal plane thicknesses, number of plated through hole (PTH) vias, PTH via drill diameter, PTH via plating thickness, and PTH via fill material conductivity. The impact of die size and die attach conductivity is also presented in this paper. The effects of these changes are evaluated with a validated finite element model. Two thermal environments are used to evaluate these variables: (1) natural convection with radiation and (2) constant temperature on the bottom side of PWB. Results are listed using two thermal resistances: junction-to-ambient thermal resistance in natural convection on a 2s2p test board (Theta-JMA) according to EIA/JESD51-6 and junction-to-heat sink (Theta-JS) determined with the bottom of the board held at a constant temperature. Theta-JMA is most sensitive to test board area, number of PTH vias, and test board internal plane thickness. Theta-JS is most sensitive to number of PTH vias. The thermal performance of the QFN is also evaluated in two distinct arrangements meant to illustrate the application environment conditions: (1) in a 3/spl times/3 cluster on a board, and (2) on the board where it is attached to an aluminum heat rail. Heat sinking the bottom of the board allows packages to dissipate more heat for a given junction-to-ambient temperature difference than the packages that rely only on natural convection.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"25 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131200043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012443
E. Sansoucy, G. Refai-Ahmed, K. Karimanal
The present study numerically investigates the thermal characterization of a 420 ball copper lid ball grid array (TBGA) package. The purpose of this work is to study a thermal characterization approach for determining the resistances of a two-resistor thermal model. The investigation employed different boundary conditions to obtain the thermal resistances through the package. This compact model was numerically validated by comparison with its detailed equivalent in a board level simulation. The results indicate that the accuracy of the two resistor compact modeling approach depends on the boundary conditions such as the approaching velocity and the thermal conductivity of the PCB.
{"title":"Thermal characterization of TBGA package for an integration in board level analysis","authors":"E. Sansoucy, G. Refai-Ahmed, K. Karimanal","doi":"10.1109/ITHERM.2002.1012443","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012443","url":null,"abstract":"The present study numerically investigates the thermal characterization of a 420 ball copper lid ball grid array (TBGA) package. The purpose of this work is to study a thermal characterization approach for determining the resistances of a two-resistor thermal model. The investigation employed different boundary conditions to obtain the thermal resistances through the package. This compact model was numerically validated by comparison with its detailed equivalent in a board level simulation. The results indicate that the accuracy of the two resistor compact modeling approach depends on the boundary conditions such as the approaching velocity and the thermal conductivity of the PCB.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133396040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012479
S. Mukherjee, I. Mudawar
Two-phase cooling of a square simulated electronic device surface of 21.3 mm side was successfully carried out without the need for a pump. This smart, passive, low-cost cooling system incorporates a self-enhancing and self-sustaining mechanism, wherein the system inherently enhances its cooling capacity by increasing the velocity of the two-phase mixture along the boiling surface when an increase in heat flux is sensed. Other practical attributes of this pumpless loop are small liquid inventory requirements and absence of the incipient boiling temperature drop. It is shown small surface tension and contact angle render dielectric coolants such as FC-72 ideally suited for flow in narrow gaps. These unique properties are responsible for very small bubble size, precluding any appreciable blockage of the replenishment liquid flow even in narrow gaps. Critical heat flux (CHF) was found to generally increase with decreasing boiler gap. CHF for flat, micro-channel (with 0.2 mm rectangular fins) and mini-channel (with 1.98 mm rectangular fins) surfaces was 4.5, 5.9, and 5.7 times greater than for pool boiling from a flat surface for corresponding gaps. A pressure drop model was formulated to predict coolant mass flow rate, boiling surface inlet and exit velocities, and pressure drop components throughout the loop. The model predictions illustrate the pumpless loop's self-sustaining and self-enhancing attributes, and relate CHF trends to those of the two-phase mixture acceleration along the boiling surface.
{"title":"Smart, low-cost, pumpless loop for micro-channel electronic cooling using flat and enhanced surfaces","authors":"S. Mukherjee, I. Mudawar","doi":"10.1109/ITHERM.2002.1012479","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012479","url":null,"abstract":"Two-phase cooling of a square simulated electronic device surface of 21.3 mm side was successfully carried out without the need for a pump. This smart, passive, low-cost cooling system incorporates a self-enhancing and self-sustaining mechanism, wherein the system inherently enhances its cooling capacity by increasing the velocity of the two-phase mixture along the boiling surface when an increase in heat flux is sensed. Other practical attributes of this pumpless loop are small liquid inventory requirements and absence of the incipient boiling temperature drop. It is shown small surface tension and contact angle render dielectric coolants such as FC-72 ideally suited for flow in narrow gaps. These unique properties are responsible for very small bubble size, precluding any appreciable blockage of the replenishment liquid flow even in narrow gaps. Critical heat flux (CHF) was found to generally increase with decreasing boiler gap. CHF for flat, micro-channel (with 0.2 mm rectangular fins) and mini-channel (with 1.98 mm rectangular fins) surfaces was 4.5, 5.9, and 5.7 times greater than for pool boiling from a flat surface for corresponding gaps. A pressure drop model was formulated to predict coolant mass flow rate, boiling surface inlet and exit velocities, and pressure drop components throughout the loop. The model predictions illustrate the pumpless loop's self-sustaining and self-enhancing attributes, and relate CHF trends to those of the two-phase mixture acceleration along the boiling surface.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131316191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012444
K. Karimanal, G. Ahmed
This work focuses the application of compact conduction model (CCM) creation approach to BGA packages under steady state conditions. The procedure of creating CCM from detailed BGA model is demonstrated. The authors have imposed realistic boundary condition scenarios that are likely to test the boundary condition independence necessary for the compact modeling approach. Results showed acceptable agreement in die temperature and heat flow predictions from simulations using detailed BGA models and their CCM equivalents.
{"title":"Validation of compact conduction models of BGA under an expanded boundary condition set","authors":"K. Karimanal, G. Ahmed","doi":"10.1109/ITHERM.2002.1012444","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012444","url":null,"abstract":"This work focuses the application of compact conduction model (CCM) creation approach to BGA packages under steady state conditions. The procedure of creating CCM from detailed BGA model is demonstrated. The authors have imposed realistic boundary condition scenarios that are likely to test the boundary condition independence necessary for the compact modeling approach. Results showed acceptable agreement in die temperature and heat flow predictions from simulations using detailed BGA models and their CCM equivalents.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124869331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012524
C. Bruns, S. Sundaram
With the increased popularity of multi-processor systems and ever-increasing power requirements, the problem of preventing re-circulation of preheated air is becoming more important to consider in system-level designs. For the common setup of a desktop tower chassis with two impingement-cooled heat sinks and one or more system fans, the problem is that pre-heated air exiting the heat sink from the upstream processor can cause a significant rise in the intake temperature for the other processor. For many systems, temperature rises of up to 10 degrees were observed for the rear processor over the front one, all other factors being equal. Air deflectors were designed with the goal of controlling this problem in multiprocessor systems. They have been optimized and tested through experiments. The effect of these devices was that the temperature of the downstream processor dropped by 68 degrees in most cases, and there is usually a smaller effect on the temperature of the upstream processor. Consequently, higher speed processors could be supported without major changes to chassis, system layout, or heat sink cost. This method could be applicable not only to computer processors, but to general convection-cooled systems with multiple heat sources.
{"title":"Controlling air recirculation in multi-processor systems","authors":"C. Bruns, S. Sundaram","doi":"10.1109/ITHERM.2002.1012524","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012524","url":null,"abstract":"With the increased popularity of multi-processor systems and ever-increasing power requirements, the problem of preventing re-circulation of preheated air is becoming more important to consider in system-level designs. For the common setup of a desktop tower chassis with two impingement-cooled heat sinks and one or more system fans, the problem is that pre-heated air exiting the heat sink from the upstream processor can cause a significant rise in the intake temperature for the other processor. For many systems, temperature rises of up to 10 degrees were observed for the rear processor over the front one, all other factors being equal. Air deflectors were designed with the goal of controlling this problem in multiprocessor systems. They have been optimized and tested through experiments. The effect of these devices was that the temperature of the downstream processor dropped by 68 degrees in most cases, and there is usually a smaller effect on the temperature of the upstream processor. Consequently, higher speed processors could be supported without major changes to chassis, system layout, or heat sink cost. This method could be applicable not only to computer processors, but to general convection-cooled systems with multiple heat sources.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128674221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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