Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012574
C. Gillot, Y. Avenas, N. Cezac, G. Poupon, C. Schaeffer, E. Fournier
An increase in power densities in electronic devices is a direct consequence of their miniaturization and performance improvements. We propose the use of flat miniature heat pipes with micro capillary grooves to spread heat flux across a beat sink. Models of the structure were developed to calculate heat transfer limitations and temperature drops. A brass/water prototype was fabricated to demonstrate the feasibility of heat spreading using this type of heat pipe. Simulation and experimental results obtained with the prototype are described. The dissipated power reached 110 W/cm/sup 2/ without heat transfer limitations. The results are then extended to the design of this type of heat pipe in silicon. Thermal performance was calculated. Simulation, experimental results and the fabrication process are presented.
{"title":"Silicon heat pipes used as thermal spreaders","authors":"C. Gillot, Y. Avenas, N. Cezac, G. Poupon, C. Schaeffer, E. Fournier","doi":"10.1109/ITHERM.2002.1012574","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012574","url":null,"abstract":"An increase in power densities in electronic devices is a direct consequence of their miniaturization and performance improvements. We propose the use of flat miniature heat pipes with micro capillary grooves to spread heat flux across a beat sink. Models of the structure were developed to calculate heat transfer limitations and temperature drops. A brass/water prototype was fabricated to demonstrate the feasibility of heat spreading using this type of heat pipe. Simulation and experimental results obtained with the prototype are described. The dissipated power reached 110 W/cm/sup 2/ without heat transfer limitations. The results are then extended to the design of this type of heat pipe in silicon. Thermal performance was calculated. Simulation, experimental results and the fabrication process are presented.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133962602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012460
X.Y. Huang, H. Zhang
An experimental study was conducted on buoyancy-induced flow patterns and heat transfer characteristics of airflow through a horizontal rectangular channel. The channel had an aspect ratio of six, and its bottom and sidewalls were heated, whereas the top of the channel was cooled. The experiments were conducted at Reynolds numbers of 40 and 100 and Rayleigh numbers ranging from 100 to 4200. The Nusselt number and the temperature distributions on the top surface of the channel were measured simultaneously at different thermal/flow conditions, and the heat transfer characteristics of the channel were evaluated, together with the flow patterns in the channel. The results showed that due to the heated sidewalls, which was an 'imperfect' factor comparing with the classic Rayleigh-Benard channel, longitudinal vortex rolls can occur at a Rayleigh number Ra=100, starting with number of rolls N=2 and then N=4 as Ra increases, rather than the N=6 mode for the same channel with 'perfect' sidewalls. It was demonstrated that the high modes can be excited actively in the channel to produce significant heat transfer enhancement in low Reynolds and Rayleigh number flow.
{"title":"An experimental study on flow patterns and heat transfer enhancement in low-Reynolds-Rayleigh-number channel flow","authors":"X.Y. Huang, H. Zhang","doi":"10.1109/ITHERM.2002.1012460","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012460","url":null,"abstract":"An experimental study was conducted on buoyancy-induced flow patterns and heat transfer characteristics of airflow through a horizontal rectangular channel. The channel had an aspect ratio of six, and its bottom and sidewalls were heated, whereas the top of the channel was cooled. The experiments were conducted at Reynolds numbers of 40 and 100 and Rayleigh numbers ranging from 100 to 4200. The Nusselt number and the temperature distributions on the top surface of the channel were measured simultaneously at different thermal/flow conditions, and the heat transfer characteristics of the channel were evaluated, together with the flow patterns in the channel. The results showed that due to the heated sidewalls, which was an 'imperfect' factor comparing with the classic Rayleigh-Benard channel, longitudinal vortex rolls can occur at a Rayleigh number Ra=100, starting with number of rolls N=2 and then N=4 as Ra increases, rather than the N=6 mode for the same channel with 'perfect' sidewalls. It was demonstrated that the high modes can be excited actively in the channel to produce significant heat transfer enhancement in low Reynolds and Rayleigh number flow.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133522919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012433
W.K. Coxe, G. Solbrekken, K. Yazawa, A. Bar-Cohen
Rapid expansion of the portable computing market segment coupled with ever increasing power dissipation and severe battery power limitations are combining to bring new importance to the development of minimum-energy thermal solutions for notebook-type computers. Passive cooling provides a very attractive thermal management option for such systems. Determination of the amount of heat that can be passively dissipated from the outer surfaces of a notebook computer provides thermal designers with a well-defined performance target and a quantitative demarcation between actively and passively cooled equipment categories. Previous work has analytically and numerically estimated the passive cooling limit from the external surfaces of a 305/spl times/248 mm notebook and found that as much as 38.8 Watts could be dissipated. The current paper describes the experimental validation of the natural convection models, underpinning those results, and the apparatus used to obtain the necessary data. The measurement error and repeatability in this apparatus are also described. In addition to validating the isolated, isothermal natural convection models, experiments were conducted to explore "real world" behavior, such as 3-D flow effects and interactions between heat dissipating surfaces. The experimental results are used to refine the theoretical limits on passive cooling.
{"title":"Experimental modeling of the passive cooling limit of notebook computers","authors":"W.K. Coxe, G. Solbrekken, K. Yazawa, A. Bar-Cohen","doi":"10.1109/ITHERM.2002.1012433","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012433","url":null,"abstract":"Rapid expansion of the portable computing market segment coupled with ever increasing power dissipation and severe battery power limitations are combining to bring new importance to the development of minimum-energy thermal solutions for notebook-type computers. Passive cooling provides a very attractive thermal management option for such systems. Determination of the amount of heat that can be passively dissipated from the outer surfaces of a notebook computer provides thermal designers with a well-defined performance target and a quantitative demarcation between actively and passively cooled equipment categories. Previous work has analytically and numerically estimated the passive cooling limit from the external surfaces of a 305/spl times/248 mm notebook and found that as much as 38.8 Watts could be dissipated. The current paper describes the experimental validation of the natural convection models, underpinning those results, and the apparatus used to obtain the necessary data. The measurement error and repeatability in this apparatus are also described. In addition to validating the isolated, isothermal natural convection models, experiments were conducted to explore \"real world\" behavior, such as 3-D flow effects and interactions between heat dissipating surfaces. The experimental results are used to refine the theoretical limits on passive cooling.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126946145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012483
C. Bash, C. Patel, A. Beitelmal
This paper introduces a unique thermal management architecture that employs vapor-compression refrigeration to cool, above the dew point, multiple independently operating microprocessors in a small volume. The refrigeration system is driven by a novel acoustic compressor technology that has the virtues of, among other things, being highly variable, oil-less, and orientation independent, and thus able to operate under significant variations in loading and deployment. The paper will also, therefore, introduce acoustic compression and discuss its application to the thermal management of electronics. A prototype 5U server with four 100 W, independently variable, heat loads demonstrating the technology has been built and experimental results are reviewed.
{"title":"Acoustic compression for the thermal management of multi-load electronic systems","authors":"C. Bash, C. Patel, A. Beitelmal","doi":"10.1109/ITHERM.2002.1012483","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012483","url":null,"abstract":"This paper introduces a unique thermal management architecture that employs vapor-compression refrigeration to cool, above the dew point, multiple independently operating microprocessors in a small volume. The refrigeration system is driven by a novel acoustic compressor technology that has the virtues of, among other things, being highly variable, oil-less, and orientation independent, and thus able to operate under significant variations in loading and deployment. The paper will also, therefore, introduce acoustic compression and discuss its application to the thermal management of electronics. A prototype 5U server with four 100 W, independently variable, heat loads demonstrating the technology has been built and experimental results are reviewed.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129219496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012514
D. Gardell
Electronic devices are routinely tested multiple times during the manufacturing process: at the wafer level, at module level test and during module burn-in. The challenges of temperature control are significant because the devices are not yet fitted with a permanent heat sink; device powers may be very high and temperature specifications can be tight. Ideally, the thermal solution will provide excellent temperature control, be fast and easy to apply, will have indefinite life, and leave the device clean and dry. Cost, weight, noise and power consumption of the thermal solution are generally of secondary concern. High power thermal solutions typically consist of a passive or actively controlled, liquid-cooled heat sink temporarily pressed into contact with the silicon device surface. Methods have been developed to evaluate the thermal performance of these temporary heat sinks. Device-to-heat sink thermal interface resistance is evaluated with thermal test chips. Temperature gradients across the uniformly powered test chips are presented as a function of device power, heat loss into the socket, test temperature, heat sink force, centrality of the force and time.
{"title":"Temperature control during test and burn-in","authors":"D. Gardell","doi":"10.1109/ITHERM.2002.1012514","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012514","url":null,"abstract":"Electronic devices are routinely tested multiple times during the manufacturing process: at the wafer level, at module level test and during module burn-in. The challenges of temperature control are significant because the devices are not yet fitted with a permanent heat sink; device powers may be very high and temperature specifications can be tight. Ideally, the thermal solution will provide excellent temperature control, be fast and easy to apply, will have indefinite life, and leave the device clean and dry. Cost, weight, noise and power consumption of the thermal solution are generally of secondary concern. High power thermal solutions typically consist of a passive or actively controlled, liquid-cooled heat sink temporarily pressed into contact with the silicon device surface. Methods have been developed to evaluate the thermal performance of these temporary heat sinks. Device-to-heat sink thermal interface resistance is evaluated with thermal test chips. Temperature gradients across the uniformly powered test chips are presented as a function of device power, heat loss into the socket, test temperature, heat sink force, centrality of the force and time.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117284638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012556
G. Ramakrishna, Fuhan Liu, S. Sitaraman
Dramatic advances in the electronics industry have lead to higher I/O, finer pitch and smaller footprint off chip interconnects to meet the cost, performance and size requirements. Microvia substrate technologies will play a crucial role in the printed wiring board (PWB) industry to accommodate these high I/O chips. A comprehensive experimental and theoretical program is underway at the Georgia Institute of Technology to develop the microvia, substrate technologies. The experimental aspect of this program involves fabrication in a class 1000 clean room facility to understand the effect of process parameters on yield and reliability of the microvia and high density wiring (HDW) structures. The theoretical program aims to understand the mechanics of deformation and thus predict and enhance the reliability of the microvia structures. The focus of this paper is (a) to characterize the effect of microvia geometry parameters on the evolution of stain and (b) to determine the effect of dielectric material property on the thermomechanical reliability of the microvias (c) to understand the effect of processing parameters on yield.
{"title":"Experimental and numerical investigation of microvia reliability","authors":"G. Ramakrishna, Fuhan Liu, S. Sitaraman","doi":"10.1109/ITHERM.2002.1012556","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012556","url":null,"abstract":"Dramatic advances in the electronics industry have lead to higher I/O, finer pitch and smaller footprint off chip interconnects to meet the cost, performance and size requirements. Microvia substrate technologies will play a crucial role in the printed wiring board (PWB) industry to accommodate these high I/O chips. A comprehensive experimental and theoretical program is underway at the Georgia Institute of Technology to develop the microvia, substrate technologies. The experimental aspect of this program involves fabrication in a class 1000 clean room facility to understand the effect of process parameters on yield and reliability of the microvia and high density wiring (HDW) structures. The theoretical program aims to understand the mechanics of deformation and thus predict and enhance the reliability of the microvia structures. The focus of this paper is (a) to characterize the effect of microvia geometry parameters on the evolution of stain and (b) to determine the effect of dielectric material property on the thermomechanical reliability of the microvias (c) to understand the effect of processing parameters on yield.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124521822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012516
K. Sikka, H. Toy, D. Edwards, S. Iruvanti, E. Ingalls, P. Dehaven
A method of reducing the thermal paste chip-to-cap interface gap is presented to achieve enhanced cooling of single flip-chip electronic modules. The structure and assembly process steps of the gap reduction design are described. The thermal reliability of the design is evaluated by measuring the thermal resistance for several permutations of the structural design variables, allowing identification of an optimum design configuration.
{"title":"Gap-reduced thermal paste package design for cooling single flip-chip electronic modules","authors":"K. Sikka, H. Toy, D. Edwards, S. Iruvanti, E. Ingalls, P. Dehaven","doi":"10.1109/ITHERM.2002.1012516","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012516","url":null,"abstract":"A method of reducing the thermal paste chip-to-cap interface gap is presented to achieve enhanced cooling of single flip-chip electronic modules. The structure and assembly process steps of the gap reduction design are described. The thermal reliability of the design is evaluated by measuring the thermal resistance for several permutations of the structural design variables, allowing identification of an optimum design configuration.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122450129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012496
Y. Shabany
Numerical solutions of the three-dimensional heat conduction equation were used to study variation of the effective thermal conductivity of printed circuit boards (PCBs) with component size. Solutions were obtained for two PCB thicknesses, three numbers of internal copper layers, and different size components. Cases with and without a copper layer on the component side were investigated. It was shown that the effective thermal conductivity of a PCB with/without a copper layer on the component side would be larger/smaller than the values given by the one-dimensional effective thermal conductivity model if the components mounted on the PCB were smaller than the PCB itself. The difference was more pronounced for smaller components. Correlations were obtained for the effective thermal conductivity of PCBs.
{"title":"Component size and effective thermal conductivity of printed circuit boards","authors":"Y. Shabany","doi":"10.1109/ITHERM.2002.1012496","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012496","url":null,"abstract":"Numerical solutions of the three-dimensional heat conduction equation were used to study variation of the effective thermal conductivity of printed circuit boards (PCBs) with component size. Solutions were obtained for two PCB thicknesses, three numbers of internal copper layers, and different size components. Cases with and without a copper layer on the component side were investigated. It was shown that the effective thermal conductivity of a PCB with/without a copper layer on the component side would be larger/smaller than the values given by the one-dimensional effective thermal conductivity model if the components mounted on the PCB were smaller than the PCB itself. The difference was more pronounced for smaller components. Correlations were obtained for the effective thermal conductivity of PCBs.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122674984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012436
V. Eveloy, P. Rodgers, J. Lohan
Numerical predictive accuracy is investigated for transient component heat transfer using a computational fluid dynamics (CFD) code dedicated to the thermal analysis of electronic equipment. The test cases are based on a single printed circuit board (PCB)-mounted, 160-lead PQFP component, analyzed in still-air, and both 1 and 2.25 m/s forced airflows. Three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. Benchmark criteria are based on component junction temperature and component-PCB surface temperature, measured using thermal test dies and infrared thermography respectively. Using both nominal component/PCB geometry dimensions and material properties, component junction temperature is found to be accurately predicted for component dynamic power dissipation, in both fixed and varying ambient air temperature conditions.
{"title":"Comparison of numerical predictions and experimental measurements for the transient thermal behavior of a board-mounted electronic component","authors":"V. Eveloy, P. Rodgers, J. Lohan","doi":"10.1109/ITHERM.2002.1012436","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012436","url":null,"abstract":"Numerical predictive accuracy is investigated for transient component heat transfer using a computational fluid dynamics (CFD) code dedicated to the thermal analysis of electronic equipment. The test cases are based on a single printed circuit board (PCB)-mounted, 160-lead PQFP component, analyzed in still-air, and both 1 and 2.25 m/s forced airflows. Three types of transient operating conditions are considered, namely (i) component dynamic power dissipation in fixed ambient conditions, (ii) passive component operation in dynamic ambient conditions, and (iii) combined component dynamic power dissipation in varying ambient conditions. Benchmark criteria are based on component junction temperature and component-PCB surface temperature, measured using thermal test dies and infrared thermography respectively. Using both nominal component/PCB geometry dimensions and material properties, component junction temperature is found to be accurately predicted for component dynamic power dissipation, in both fixed and varying ambient air temperature conditions.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123382268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-08-07DOI: 10.1109/ITHERM.2002.1012540
D. Wheeler, D. Josell, T. Moffat
Damascene copper is rapidly replacing aluminum as the interconnect material of choice in silicon technology. The change is driven by the lower electrical resistivity of copper, which decreases power consumption and permits increased central processor unit (CPU) clocking speeds. Electroplating is the preferred deposition method because it permits filling of high-aspect ratio features without seams or voids through the process of superconformal deposition, also called "superfill." This process has been demonstrated to depend critically on the inclusion of additives in the electrolyte. Superfill occurs when a high aspect ratio feature on a silicon wafer fills due to preferential metal deposition permitting the bottom surface to rise before the side walls close off. Two crucial mechanisms by which the additives enable superfill to occur are (a) accelerator behavior increasing the copper deposition rate as a function of coverage and (b) conservation of accelerator coverage with increasing/decreasing arc length. A model that includes these effects is implemented using the level set method. Trench superfilling simulations will be presented and compared with experiment.
{"title":"Modeling superconformal electrodeposition in trenches","authors":"D. Wheeler, D. Josell, T. Moffat","doi":"10.1109/ITHERM.2002.1012540","DOIUrl":"https://doi.org/10.1109/ITHERM.2002.1012540","url":null,"abstract":"Damascene copper is rapidly replacing aluminum as the interconnect material of choice in silicon technology. The change is driven by the lower electrical resistivity of copper, which decreases power consumption and permits increased central processor unit (CPU) clocking speeds. Electroplating is the preferred deposition method because it permits filling of high-aspect ratio features without seams or voids through the process of superconformal deposition, also called \"superfill.\" This process has been demonstrated to depend critically on the inclusion of additives in the electrolyte. Superfill occurs when a high aspect ratio feature on a silicon wafer fills due to preferential metal deposition permitting the bottom surface to rise before the side walls close off. Two crucial mechanisms by which the additives enable superfill to occur are (a) accelerator behavior increasing the copper deposition rate as a function of coverage and (b) conservation of accelerator coverage with increasing/decreasing arc length. A model that includes these effects is implemented using the level set method. Trench superfilling simulations will be presented and compared with experiment.","PeriodicalId":299933,"journal":{"name":"ITherm 2002. Eighth Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.02CH37258)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114702238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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