Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47139
M. Namjoo
The first two implementations of the SPARC architecture, MB86900 and CY7601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS (millions of instructions per second). MB86900 design uses a single 20000-gate 1.3- mu m CMOS gate array and operates at a cycle time of 60 ns. CY7601 is a full custom chip designed using a 0.8- mu m CMOS process and operates at a cycle time of 30 ns. The basic features of these processors, their similarities and differences, and the tradeoffs used in their design. Design verification, test generation, and fault simulation are addressed.<>
SPARC架构的前两种实现MB86900和CY7601采用高速CMOS技术设计，处理器时钟速度在16.6至33 MHz范围内。在具有合理大小的外部缓存的系统中，这些处理器以每条指令大约1.5个时钟周期的速率执行整数操作，从而获得10到20 MIPS(每秒数百万条指令)的持续性能。MB86900设计采用单个20000门1.3 μ m CMOS门阵列，工作周期为60ns。CY7601是一款完全定制的芯片，采用0.8 μ m CMOS工艺设计，工作周期为30 ns。这些处理器的基本特性，它们的异同，以及在它们的设计中使用的权衡。讨论了设计验证、测试生成和故障模拟。
{"title":"SPARC implementations: ASIC vs. custom design","authors":"M. Namjoo","doi":"10.1109/HICSS.1989.47139","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47139","url":null,"abstract":"The first two implementations of the SPARC architecture, MB86900 and CY7601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS (millions of instructions per second). MB86900 design uses a single 20000-gate 1.3- mu m CMOS gate array and operates at a cycle time of 60 ns. CY7601 is a full custom chip designed using a 0.8- mu m CMOS process and operates at a cycle time of 30 ns. The basic features of these processors, their similarities and differences, and the tradeoffs used in their design. Design verification, test generation, and fault simulation are addressed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125183375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47188
Guo‐zhen Yang, Yansong Chen, Shi-Hai Zhing, B. Dong, Dehuan Li
A coherent optical system for performing an arbitrary linear transform is described. The system consists of a holographic mask and two Fourier lenses. A set of equations for determining the amplitude-phase distribution of the mask is given, and the mask is generated by combination of a computer-generated hologram and optical holography. As an example, a Walsh-Hadamard transform of order 32 is realized.<>
{"title":"A coherent system for performing an optical transform","authors":"Guo‐zhen Yang, Yansong Chen, Shi-Hai Zhing, B. Dong, Dehuan Li","doi":"10.1109/HICSS.1989.47188","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47188","url":null,"abstract":"A coherent optical system for performing an arbitrary linear transform is described. The system consists of a holographic mask and two Fourier lenses. A set of equations for determining the amplitude-phase distribution of the mask is given, and the mask is generated by combination of a computer-generated hologram and optical holography. As an example, a Walsh-Hadamard transform of order 32 is realized.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47191
R. Forchheimer, V. Plavsic
Approaches to the optical implementation of the stored-program concept are presented. The focus is on microprogramming, which is commonly used to organize data flow at the lowest hardware level. It is shown that the traditional implementation used in electronic computers maps easily into optics in many ways. A distributed addressing approach provides a simple solution, while a centralized addressing approach becomes more space-efficient as the number of instructions increases. A main contribution is the use of holographic storage for the control instructions. It is shown that full utilization of this storage technique can be achieved within a suggested interconnection structure.<>
{"title":"Approaches to optical microprogramming","authors":"R. Forchheimer, V. Plavsic","doi":"10.1109/HICSS.1989.47191","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47191","url":null,"abstract":"Approaches to the optical implementation of the stored-program concept are presented. The focus is on microprogramming, which is commonly used to organize data flow at the lowest hardware level. It is shown that the traditional implementation used in electronic computers maps easily into optics in many ways. A distributed addressing approach provides a simple solution, while a centralized addressing approach becomes more space-efficient as the number of instructions increases. A main contribution is the use of holographic storage for the control instructions. It is shown that full utilization of this storage technique can be achieved within a suggested interconnection structure.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125882972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47181
R. Yung, A. Despain, Y. Patt
The Aquarius numeric processor (ANP) is an extended numeric instruction set architecture that is based on the Berkeley programmed logic machine (PLM) and supports integrated symbolic and numeric calculations. This extension expands the existing numeric data type to include 32- and 64-bit integers and single- and double-precision floating-point numbers conforming to the IEEE Standard P754. A class of data structure called numeric arrays has been added to represent matrices and arrays found in most scientific programming languages. Powerful numeric instructions are included to manipulate these novel data types. The authors describe the programming model and the architecture of the ANP. An experimental ANP is currently under construction using TTL (transistor-transistor logic) and ECL (emitter-coupled logic) parts. Simulated performance results indicate that the system will achieve about 10 MFLOPs (millions of floating-point operations) on the Prolog version of some Whetstone and Linpack benchmarks and close to 20 MFLOPS on some matrix operations (all in double precision).<>
{"title":"Extending a Prolog architecture for high performance numeric computations","authors":"R. Yung, A. Despain, Y. Patt","doi":"10.1109/HICSS.1989.47181","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47181","url":null,"abstract":"The Aquarius numeric processor (ANP) is an extended numeric instruction set architecture that is based on the Berkeley programmed logic machine (PLM) and supports integrated symbolic and numeric calculations. This extension expands the existing numeric data type to include 32- and 64-bit integers and single- and double-precision floating-point numbers conforming to the IEEE Standard P754. A class of data structure called numeric arrays has been added to represent matrices and arrays found in most scientific programming languages. Powerful numeric instructions are included to manipulate these novel data types. The authors describe the programming model and the architecture of the ANP. An experimental ANP is currently under construction using TTL (transistor-transistor logic) and ECL (emitter-coupled logic) parts. Simulated performance results indicate that the system will achieve about 10 MFLOPs (millions of floating-point operations) on the Prolog version of some Whetstone and Linpack benchmarks and close to 20 MFLOPS on some matrix operations (all in double precision).<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128961935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47175
J. Rosenberg, D. Koch, J. Keedy
An approach to supercomputing that is based on using a massive main memory (in the order of gigabytes) is investigated. Many of the problems currently solved on conventional supercomputers can equally be solved in similar time on such a machine, with a modest processor speed. The advantages of this approach in supporting database applications, VLSI applications and many other applications working on large volumes of date are examined. It is shown how the architecture of the MONADS-PC system, a capability-based computer developed by the authors, can be adapted to support such a large memory. The architectural design of a machine based on MONADS-PC is given, with special emphasis on the addressing and address translation issue.<>
{"title":"A massive memory supercomputer","authors":"J. Rosenberg, D. Koch, J. Keedy","doi":"10.1109/HICSS.1989.47175","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47175","url":null,"abstract":"An approach to supercomputing that is based on using a massive main memory (in the order of gigabytes) is investigated. Many of the problems currently solved on conventional supercomputers can equally be solved in similar time on such a machine, with a modest processor speed. The advantages of this approach in supporting database applications, VLSI applications and many other applications working on large volumes of date are examined. It is shown how the architecture of the MONADS-PC system, a capability-based computer developed by the authors, can be adapted to support such a large memory. The architectural design of a machine based on MONADS-PC is given, with special emphasis on the addressing and address translation issue.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47158
M. Naini
A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<>
{"title":"A dedicated data flow architecture for hardware compilation","authors":"M. Naini","doi":"10.1109/HICSS.1989.47158","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47158","url":null,"abstract":"A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131537969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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