Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47166
E. Scott
The author explores the yields and limits of a large-scale multiprocessor architecture. He shows four results. First, that there is a single resource in every multiprocessor system that limits incremental expansion. Once this resource approaches full utilization, adding processors is useless and possibly detrimental. With uniform resource access by statistically identical processors, the maximum number of effective processors is 1/X, where X is the fraction of its own productive time that one processor uses this resource. Secondly, he finds that this limiting resource can be discovered by measuring the resource usage behavior of one processor. Reducing contention for this resource will extend the limits of an architecture. Third, the author shows that approaching the 1/X upper limit, the incremental yield curve is spectacularly near linear, implying that nearly one full effective processor from each additional processor should be expected. Last, he shows that previously published formulas for incremental yield are too pessimistic and should not be applied to a general purpose multiple-instruction-multiple-data-stream (MIMD) architecture. It is shown how pessimistic these views are and why the formulas do not apply. It is demonstrated that a multiprocessor system can be extended to its limit with minimal degradation, generally with 90% or better effective yield for small numbers of shared resources.<>
{"title":"The limits of incremental multiprocessors","authors":"E. Scott","doi":"10.1109/HICSS.1989.47166","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47166","url":null,"abstract":"The author explores the yields and limits of a large-scale multiprocessor architecture. He shows four results. First, that there is a single resource in every multiprocessor system that limits incremental expansion. Once this resource approaches full utilization, adding processors is useless and possibly detrimental. With uniform resource access by statistically identical processors, the maximum number of effective processors is 1/X, where X is the fraction of its own productive time that one processor uses this resource. Secondly, he finds that this limiting resource can be discovered by measuring the resource usage behavior of one processor. Reducing contention for this resource will extend the limits of an architecture. Third, the author shows that approaching the 1/X upper limit, the incremental yield curve is spectacularly near linear, implying that nearly one full effective processor from each additional processor should be expected. Last, he shows that previously published formulas for incremental yield are too pessimistic and should not be applied to a general purpose multiple-instruction-multiple-data-stream (MIMD) architecture. It is shown how pessimistic these views are and why the formulas do not apply. It is demonstrated that a multiprocessor system can be extended to its limit with minimal degradation, generally with 90% or better effective yield for small numbers of shared resources.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47148
J. Beekman, R. Owens, M. J. Irwin
A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<>
{"title":"A rapid turn-around system for designing efficient fine grained signal processors","authors":"J. Beekman, R. Owens, M. J. Irwin","doi":"10.1109/HICSS.1989.47148","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47148","url":null,"abstract":"A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115897555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47188
Guo‐zhen Yang, Yansong Chen, Shi-Hai Zhing, B. Dong, Dehuan Li
A coherent optical system for performing an arbitrary linear transform is described. The system consists of a holographic mask and two Fourier lenses. A set of equations for determining the amplitude-phase distribution of the mask is given, and the mask is generated by combination of a computer-generated hologram and optical holography. As an example, a Walsh-Hadamard transform of order 32 is realized.<>
{"title":"A coherent system for performing an optical transform","authors":"Guo‐zhen Yang, Yansong Chen, Shi-Hai Zhing, B. Dong, Dehuan Li","doi":"10.1109/HICSS.1989.47188","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47188","url":null,"abstract":"A coherent optical system for performing an arbitrary linear transform is described. The system consists of a holographic mask and two Fourier lenses. A set of equations for determining the amplitude-phase distribution of the mask is given, and the mask is generated by combination of a computer-generated hologram and optical holography. As an example, a Walsh-Hadamard transform of order 32 is realized.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126874967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47191
R. Forchheimer, V. Plavsic
Approaches to the optical implementation of the stored-program concept are presented. The focus is on microprogramming, which is commonly used to organize data flow at the lowest hardware level. It is shown that the traditional implementation used in electronic computers maps easily into optics in many ways. A distributed addressing approach provides a simple solution, while a centralized addressing approach becomes more space-efficient as the number of instructions increases. A main contribution is the use of holographic storage for the control instructions. It is shown that full utilization of this storage technique can be achieved within a suggested interconnection structure.<>
{"title":"Approaches to optical microprogramming","authors":"R. Forchheimer, V. Plavsic","doi":"10.1109/HICSS.1989.47191","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47191","url":null,"abstract":"Approaches to the optical implementation of the stored-program concept are presented. The focus is on microprogramming, which is commonly used to organize data flow at the lowest hardware level. It is shown that the traditional implementation used in electronic computers maps easily into optics in many ways. A distributed addressing approach provides a simple solution, while a centralized addressing approach becomes more space-efficient as the number of instructions increases. A main contribution is the use of holographic storage for the control instructions. It is shown that full utilization of this storage technique can be achieved within a suggested interconnection structure.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125882972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47156
C. Gimarc, V. Milutinovic, O. Ersoy
A technique for modeling the time-domain complexity of the implementation of an algorithm is described. The model includes algorithm-, architecture-, and technology-related parameters. The model is used here to compare architectures for various Fourier-transform-oriented algorithms; however, use of the model can point to possible changes in algorithm or architecture that will increase performance. The development of the model is discussed, and an analysis of five different Fourier-transform algorithms is given.<>
{"title":"Time complexity modeling and comparison of parallel architectures for Fourier transform oriented algorithms","authors":"C. Gimarc, V. Milutinovic, O. Ersoy","doi":"10.1109/HICSS.1989.47156","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47156","url":null,"abstract":"A technique for modeling the time-domain complexity of the implementation of an algorithm is described. The model includes algorithm-, architecture-, and technology-related parameters. The model is used here to compare architectures for various Fourier-transform-oriented algorithms; however, use of the model can point to possible changes in algorithm or architecture that will increase performance. The development of the model is discussed, and an analysis of five different Fourier-transform algorithms is given.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47158
M. Naini
A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<>
{"title":"A dedicated data flow architecture for hardware compilation","authors":"M. Naini","doi":"10.1109/HICSS.1989.47158","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47158","url":null,"abstract":"A dedicated data-flow architecture that has been designed to be a part of a hardware compiler is described. This machine evaluates attribute grammars in a data-flow fashion by accepting their reverse-dependency graph, which is similar to a data-flow graph. The outputs and the results of these evaluations are sent to the other components for later use. The machine is believed to be the first dedicated data-flow architecture suggested for this purpose. It takes advantage of parallelism at two levels: first, the components of the machine are organized in a pipeline fashion and can run concurrently; second, the execution of the instructions is done in parallel as well.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131537969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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