Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47157
D. Vrsalovic, Z. Segall, D. Seiwiorek, F. Gregoretti, E. Caplan, C. E. Fineman, S. Kravitz, T. Lehr, M. Russinovitch
Multiprocessor C (MPC), a C language preprocessor that assists a programmer in building efficient parallel programs, is described. MPC provides the programmer with a virtual implementation machine, the consistent abstract shared data type implementation machine (CASDTIM). The machine is described and an analytical model for predicting performance of MPC programs using the CASDTIM is presented. The analytic model is shown to be in close agreement with the measurements of an actual MPC program executing on a commercially available multiprocessor.<>
{"title":"MPC-multiprocessor C language for consistent abstract shared data type paradigms","authors":"D. Vrsalovic, Z. Segall, D. Seiwiorek, F. Gregoretti, E. Caplan, C. E. Fineman, S. Kravitz, T. Lehr, M. Russinovitch","doi":"10.1109/HICSS.1989.47157","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47157","url":null,"abstract":"Multiprocessor C (MPC), a C language preprocessor that assists a programmer in building efficient parallel programs, is described. MPC provides the programmer with a virtual implementation machine, the consistent abstract shared data type implementation machine (CASDTIM). The machine is described and an analytical model for predicting performance of MPC programs using the CASDTIM is presented. The analytic model is shown to be in close agreement with the measurements of an actual MPC program executing on a commercially available multiprocessor.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125944098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47149
D. Cooke, G. Swan, J. Sirott, R. Kane, P. Stevens, J. Yang, D. Chen
Problems with present VLSI design management approaches are outlined, and areas for improvement are identified. A design management that will facilitate the correct and timely creation of VLSI designs is proposed, concentrating on the problems associated with designing ICs using a network of engineering workstations. The requirements for such a system are discussed from both a practical and theoretical viewpoint. The implementation is described briefly.<>
{"title":"Design management in a workstation environment","authors":"D. Cooke, G. Swan, J. Sirott, R. Kane, P. Stevens, J. Yang, D. Chen","doi":"10.1109/HICSS.1989.47149","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47149","url":null,"abstract":"Problems with present VLSI design management approaches are outlined, and areas for improvement are identified. A design management that will facilitate the correct and timely creation of VLSI designs is proposed, concentrating on the problems associated with designing ICs using a network of engineering workstations. The requirements for such a system are discussed from both a practical and theoretical viewpoint. The implementation is described briefly.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47176
F. Shih, K. Nakajima
A system design that provides efficient self-testing and optimal real-time diagnosis for multiprocessor computer networks is presented. In this design, a test is performed by running a common system task on two processors and comparing their signal signatures, obtained from the data port and the control register. A simple diagnosis structure to be derived from a given system architecture is proposed. Optimal real-time diagnosis is achieved using a hardware accelerator based on the unit-diagnosis structure. The hardware used for both the comparison testing and the fault diagnosis are simple, sufficient, and suitable for real-time implementation. It is shown that the proposed design can be applied to most fault-tolerant architectures.<>
{"title":"A system design for real-time fault-tolerant computer networks","authors":"F. Shih, K. Nakajima","doi":"10.1109/HICSS.1989.47176","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47176","url":null,"abstract":"A system design that provides efficient self-testing and optimal real-time diagnosis for multiprocessor computer networks is presented. In this design, a test is performed by running a common system task on two processors and comparing their signal signatures, obtained from the data port and the control register. A simple diagnosis structure to be derived from a given system architecture is proposed. Optimal real-time diagnosis is achieved using a hardware accelerator based on the unit-diagnosis structure. The hardware used for both the comparison testing and the fault diagnosis are simple, sufficient, and suitable for real-time implementation. It is shown that the proposed design can be applied to most fault-tolerant architectures.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47180
G. Gao, R. Tio
A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures. Work carried out on the instruction set design and machine program format is described. The implementation of long-latency operations-the structure memory operations and interprocessor communication operations-is discussed, as is the implementation of FIFO (first-in-first-out) buffers. The design of an assembler and instruction-set interpreter is outlined.<>
{"title":"Instruction set architecture of an efficient pipelined dataflow architecture","authors":"G. Gao, R. Tio","doi":"10.1109/HICSS.1989.47180","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47180","url":null,"abstract":"A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures. Work carried out on the instruction set design and machine program format is described. The implementation of long-latency operations-the structure memory operations and interprocessor communication operations-is discussed, as is the implementation of FIFO (first-in-first-out) buffers. The design of an assembler and instruction-set interpreter is outlined.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"121 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114306377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47153
D. Quammen, D.R. Miller, D. Tabak
An architecture is proposed that allows fast procedure calls, low-overhead task switches, and primitives, which assist in queue-oriented intertask communications. This is accomplished by managing the registers as noncontiguous register windows. The details of the register granularity are hidden from the applications program. The architecture is based on a VLSI CPU called the MULTIS, which is capable of handling the dynamically created data of multiple tasks in on-chip storage. This ability enables tasking systems to benefit from the use of large on-chip memories such as those found in RISC (reduced-instruction-set computer) technologies. Other features of the architecture include efficient interrupt handling and provision for register-based task local, procedure-global dynamic storage.<>
{"title":"Register window management for a real-time multitasking RISC","authors":"D. Quammen, D.R. Miller, D. Tabak","doi":"10.1109/HICSS.1989.47153","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47153","url":null,"abstract":"An architecture is proposed that allows fast procedure calls, low-overhead task switches, and primitives, which assist in queue-oriented intertask communications. This is accomplished by managing the registers as noncontiguous register windows. The details of the register granularity are hidden from the applications program. The architecture is based on a VLSI CPU called the MULTIS, which is capable of handling the dynamically created data of multiple tasks in on-chip storage. This ability enables tasking systems to benefit from the use of large on-chip memories such as those found in RISC (reduced-instruction-set computer) technologies. Other features of the architecture include efficient interrupt handling and provision for register-based task local, procedure-global dynamic storage.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47172
L. Friedman
There is a pattern to developments in new generation architectures; an application need or requirement drives an architectural definition which in turn drives technology which may or may not be able to support the requirement. Sometimes the technology provides an opportunity to realize some functionality, previously unobtainable, in the abstract application and thus drives the architecture. It can be a chicken-and-egg scenario. The underlying goal is to close, or at last, narrow the semantic gap. The paper examines various classes of new generation architectures. This division of classes is solely based on answering a fundamental question, what do we perceive as the application level for the system in question?.<>
{"title":"New generation architectures","authors":"L. Friedman","doi":"10.1109/HICSS.1989.47172","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47172","url":null,"abstract":"There is a pattern to developments in new generation architectures; an application need or requirement drives an architectural definition which in turn drives technology which may or may not be able to support the requirement. Sometimes the technology provides an opportunity to realize some functionality, previously unobtainable, in the abstract application and thus drives the architecture. It can be a chicken-and-egg scenario. The underlying goal is to close, or at last, narrow the semantic gap. The paper examines various classes of new generation architectures. This division of classes is solely based on answering a fundamental question, what do we perceive as the application level for the system in question?.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130197729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47166
E. Scott
The author explores the yields and limits of a large-scale multiprocessor architecture. He shows four results. First, that there is a single resource in every multiprocessor system that limits incremental expansion. Once this resource approaches full utilization, adding processors is useless and possibly detrimental. With uniform resource access by statistically identical processors, the maximum number of effective processors is 1/X, where X is the fraction of its own productive time that one processor uses this resource. Secondly, he finds that this limiting resource can be discovered by measuring the resource usage behavior of one processor. Reducing contention for this resource will extend the limits of an architecture. Third, the author shows that approaching the 1/X upper limit, the incremental yield curve is spectacularly near linear, implying that nearly one full effective processor from each additional processor should be expected. Last, he shows that previously published formulas for incremental yield are too pessimistic and should not be applied to a general purpose multiple-instruction-multiple-data-stream (MIMD) architecture. It is shown how pessimistic these views are and why the formulas do not apply. It is demonstrated that a multiprocessor system can be extended to its limit with minimal degradation, generally with 90% or better effective yield for small numbers of shared resources.<>
{"title":"The limits of incremental multiprocessors","authors":"E. Scott","doi":"10.1109/HICSS.1989.47166","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47166","url":null,"abstract":"The author explores the yields and limits of a large-scale multiprocessor architecture. He shows four results. First, that there is a single resource in every multiprocessor system that limits incremental expansion. Once this resource approaches full utilization, adding processors is useless and possibly detrimental. With uniform resource access by statistically identical processors, the maximum number of effective processors is 1/X, where X is the fraction of its own productive time that one processor uses this resource. Secondly, he finds that this limiting resource can be discovered by measuring the resource usage behavior of one processor. Reducing contention for this resource will extend the limits of an architecture. Third, the author shows that approaching the 1/X upper limit, the incremental yield curve is spectacularly near linear, implying that nearly one full effective processor from each additional processor should be expected. Last, he shows that previously published formulas for incremental yield are too pessimistic and should not be applied to a general purpose multiple-instruction-multiple-data-stream (MIMD) architecture. It is shown how pessimistic these views are and why the formulas do not apply. It is demonstrated that a multiprocessor system can be extended to its limit with minimal degradation, generally with 90% or better effective yield for small numbers of shared resources.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123660104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47148
J. Beekman, R. Owens, M. J. Irwin
A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<>
{"title":"A rapid turn-around system for designing efficient fine grained signal processors","authors":"J. Beekman, R. Owens, M. J. Irwin","doi":"10.1109/HICSS.1989.47148","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47148","url":null,"abstract":"A CAD (computer-aided design tool set) designed for rapid prototyping of a specific class of high-performance signal processing architectures is presented. Efficient implementation of these architectures results in systems that are very fast (<35-ns clock cycle) and can be very small in size (<500 lambda by 500 lambda ). The system is composed of five software tools that have been designed to work together. The designer inputs an algorithmic description of the application architecture, and the design system outputs the layouts of the chip set for the application architecture. While many of these tools require a large amount of run time, they allow efficient automatic production of chip sets for applications that before could only be done by hand and therefore were virtually intractable problems.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115897555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47156
C. Gimarc, V. Milutinovic, O. Ersoy
A technique for modeling the time-domain complexity of the implementation of an algorithm is described. The model includes algorithm-, architecture-, and technology-related parameters. The model is used here to compare architectures for various Fourier-transform-oriented algorithms; however, use of the model can point to possible changes in algorithm or architecture that will increase performance. The development of the model is discussed, and an analysis of five different Fourier-transform algorithms is given.<>
{"title":"Time complexity modeling and comparison of parallel architectures for Fourier transform oriented algorithms","authors":"C. Gimarc, V. Milutinovic, O. Ersoy","doi":"10.1109/HICSS.1989.47156","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47156","url":null,"abstract":"A technique for modeling the time-domain complexity of the implementation of an algorithm is described. The model includes algorithm-, architecture-, and technology-related parameters. The model is used here to compare architectures for various Fourier-transform-oriented algorithms; however, use of the model can point to possible changes in algorithm or architecture that will increase performance. The development of the model is discussed, and an analysis of five different Fourier-transform algorithms is given.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"132 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47145
S. Trimberger
The author discusses the changes in design methodology and tools that have allowed improved productivity over the last decade, identifying major problems and solutions. He follows with a discussion of coming problems in the 1990s and discusses the tools that will be needed to keep design costs down in the coming decade.<>
{"title":"Integrated circuit design productivity advancements in the 1980s and 1990s","authors":"S. Trimberger","doi":"10.1109/HICSS.1989.47145","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47145","url":null,"abstract":"The author discusses the changes in design methodology and tools that have allowed improved productivity over the last decade, identifying major problems and solutions. He follows with a discussion of coming problems in the 1990s and discusses the tools that will be needed to keep design costs down in the coming decade.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122852645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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