Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47136
R. Ashany
The stringent requirements imposed by socioeconomic forces on the computer industry and on the community of scientists and engineers is examined. The ways in which these requirements have been met, through the use of technologies, design tools, equipment, process and facility control, quality assurance and testing, and sophisticated production methodologies are discussed.<>
{"title":"Emerging design style: how does it impact the way we design?","authors":"R. Ashany","doi":"10.1109/HICSS.1989.47136","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47136","url":null,"abstract":"The stringent requirements imposed by socioeconomic forces on the computer industry and on the community of scientists and engineers is examined. The ways in which these requirements have been met, through the use of technologies, design tools, equipment, process and facility control, quality assurance and testing, and sophisticated production methodologies are discussed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127249014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47176
F. Shih, K. Nakajima
A system design that provides efficient self-testing and optimal real-time diagnosis for multiprocessor computer networks is presented. In this design, a test is performed by running a common system task on two processors and comparing their signal signatures, obtained from the data port and the control register. A simple diagnosis structure to be derived from a given system architecture is proposed. Optimal real-time diagnosis is achieved using a hardware accelerator based on the unit-diagnosis structure. The hardware used for both the comparison testing and the fault diagnosis are simple, sufficient, and suitable for real-time implementation. It is shown that the proposed design can be applied to most fault-tolerant architectures.<>
{"title":"A system design for real-time fault-tolerant computer networks","authors":"F. Shih, K. Nakajima","doi":"10.1109/HICSS.1989.47176","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47176","url":null,"abstract":"A system design that provides efficient self-testing and optimal real-time diagnosis for multiprocessor computer networks is presented. In this design, a test is performed by running a common system task on two processors and comparing their signal signatures, obtained from the data port and the control register. A simple diagnosis structure to be derived from a given system architecture is proposed. Optimal real-time diagnosis is achieved using a hardware accelerator based on the unit-diagnosis structure. The hardware used for both the comparison testing and the fault diagnosis are simple, sufficient, and suitable for real-time implementation. It is shown that the proposed design can be applied to most fault-tolerant architectures.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47149
D. Cooke, G. Swan, J. Sirott, R. Kane, P. Stevens, J. Yang, D. Chen
Problems with present VLSI design management approaches are outlined, and areas for improvement are identified. A design management that will facilitate the correct and timely creation of VLSI designs is proposed, concentrating on the problems associated with designing ICs using a network of engineering workstations. The requirements for such a system are discussed from both a practical and theoretical viewpoint. The implementation is described briefly.<>
{"title":"Design management in a workstation environment","authors":"D. Cooke, G. Swan, J. Sirott, R. Kane, P. Stevens, J. Yang, D. Chen","doi":"10.1109/HICSS.1989.47149","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47149","url":null,"abstract":"Problems with present VLSI design management approaches are outlined, and areas for improvement are identified. A design management that will facilitate the correct and timely creation of VLSI designs is proposed, concentrating on the problems associated with designing ICs using a network of engineering workstations. The requirements for such a system are discussed from both a practical and theoretical viewpoint. The implementation is described briefly.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129621612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47153
D. Quammen, D.R. Miller, D. Tabak
An architecture is proposed that allows fast procedure calls, low-overhead task switches, and primitives, which assist in queue-oriented intertask communications. This is accomplished by managing the registers as noncontiguous register windows. The details of the register granularity are hidden from the applications program. The architecture is based on a VLSI CPU called the MULTIS, which is capable of handling the dynamically created data of multiple tasks in on-chip storage. This ability enables tasking systems to benefit from the use of large on-chip memories such as those found in RISC (reduced-instruction-set computer) technologies. Other features of the architecture include efficient interrupt handling and provision for register-based task local, procedure-global dynamic storage.<>
{"title":"Register window management for a real-time multitasking RISC","authors":"D. Quammen, D.R. Miller, D. Tabak","doi":"10.1109/HICSS.1989.47153","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47153","url":null,"abstract":"An architecture is proposed that allows fast procedure calls, low-overhead task switches, and primitives, which assist in queue-oriented intertask communications. This is accomplished by managing the registers as noncontiguous register windows. The details of the register granularity are hidden from the applications program. The architecture is based on a VLSI CPU called the MULTIS, which is capable of handling the dynamically created data of multiple tasks in on-chip storage. This ability enables tasking systems to benefit from the use of large on-chip memories such as those found in RISC (reduced-instruction-set computer) technologies. Other features of the architecture include efficient interrupt handling and provision for register-based task local, procedure-global dynamic storage.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"353 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47180
G. Gao, R. Tio
A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures. Work carried out on the instruction set design and machine program format is described. The implementation of long-latency operations-the structure memory operations and interprocessor communication operations-is discussed, as is the implementation of FIFO (first-in-first-out) buffers. The design of an assembler and instruction-set interpreter is outlined.<>
{"title":"Instruction set architecture of an efficient pipelined dataflow architecture","authors":"G. Gao, R. Tio","doi":"10.1109/HICSS.1989.47180","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47180","url":null,"abstract":"A highly pipelined static dataflow architecture based on an argument-fetching data-driven principle has recently been proposed. It separates the data-driven instruction scheduling mechanism from the actual instruction execution unit, avoiding the unnecessary overhead of data token movement that exists in other proposals of dataflow architectures. Work carried out on the instruction set design and machine program format is described. The implementation of long-latency operations-the structure memory operations and interprocessor communication operations-is discussed, as is the implementation of FIFO (first-in-first-out) buffers. The design of an assembler and instruction-set interpreter is outlined.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"121 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114306377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47172
L. Friedman
There is a pattern to developments in new generation architectures; an application need or requirement drives an architectural definition which in turn drives technology which may or may not be able to support the requirement. Sometimes the technology provides an opportunity to realize some functionality, previously unobtainable, in the abstract application and thus drives the architecture. It can be a chicken-and-egg scenario. The underlying goal is to close, or at last, narrow the semantic gap. The paper examines various classes of new generation architectures. This division of classes is solely based on answering a fundamental question, what do we perceive as the application level for the system in question?.<>
{"title":"New generation architectures","authors":"L. Friedman","doi":"10.1109/HICSS.1989.47172","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47172","url":null,"abstract":"There is a pattern to developments in new generation architectures; an application need or requirement drives an architectural definition which in turn drives technology which may or may not be able to support the requirement. Sometimes the technology provides an opportunity to realize some functionality, previously unobtainable, in the abstract application and thus drives the architecture. It can be a chicken-and-egg scenario. The underlying goal is to close, or at last, narrow the semantic gap. The paper examines various classes of new generation architectures. This division of classes is solely based on answering a fundamental question, what do we perceive as the application level for the system in question?.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130197729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47175
J. Rosenberg, D. Koch, J. Keedy
An approach to supercomputing that is based on using a massive main memory (in the order of gigabytes) is investigated. Many of the problems currently solved on conventional supercomputers can equally be solved in similar time on such a machine, with a modest processor speed. The advantages of this approach in supporting database applications, VLSI applications and many other applications working on large volumes of date are examined. It is shown how the architecture of the MONADS-PC system, a capability-based computer developed by the authors, can be adapted to support such a large memory. The architectural design of a machine based on MONADS-PC is given, with special emphasis on the addressing and address translation issue.<>
{"title":"A massive memory supercomputer","authors":"J. Rosenberg, D. Koch, J. Keedy","doi":"10.1109/HICSS.1989.47175","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47175","url":null,"abstract":"An approach to supercomputing that is based on using a massive main memory (in the order of gigabytes) is investigated. Many of the problems currently solved on conventional supercomputers can equally be solved in similar time on such a machine, with a modest processor speed. The advantages of this approach in supporting database applications, VLSI applications and many other applications working on large volumes of date are examined. It is shown how the architecture of the MONADS-PC system, a capability-based computer developed by the authors, can be adapted to support such a large memory. The architectural design of a machine based on MONADS-PC is given, with special emphasis on the addressing and address translation issue.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114995335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47139
M. Namjoo
The first two implementations of the SPARC architecture, MB86900 and CY7601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS (millions of instructions per second). MB86900 design uses a single 20000-gate 1.3- mu m CMOS gate array and operates at a cycle time of 60 ns. CY7601 is a full custom chip designed using a 0.8- mu m CMOS process and operates at a cycle time of 30 ns. The basic features of these processors, their similarities and differences, and the tradeoffs used in their design. Design verification, test generation, and fault simulation are addressed.<>
SPARC架构的前两种实现MB86900和CY7601采用高速CMOS技术设计，处理器时钟速度在16.6至33 MHz范围内。在具有合理大小的外部缓存的系统中，这些处理器以每条指令大约1.5个时钟周期的速率执行整数操作，从而获得10到20 MIPS(每秒数百万条指令)的持续性能。MB86900设计采用单个20000门1.3 μ m CMOS门阵列，工作周期为60ns。CY7601是一款完全定制的芯片，采用0.8 μ m CMOS工艺设计，工作周期为30 ns。这些处理器的基本特性，它们的异同，以及在它们的设计中使用的权衡。讨论了设计验证、测试生成和故障模拟。
{"title":"SPARC implementations: ASIC vs. custom design","authors":"M. Namjoo","doi":"10.1109/HICSS.1989.47139","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47139","url":null,"abstract":"The first two implementations of the SPARC architecture, MB86900 and CY7601, were designed using high-speed CMOS technology with processor clock speed in the range of 16.6 to 33 MHz. In a system with a reasonable size external cache, these processors execute integer operations at a rate of approximately 1.5 clock cycles per instruction, resulting in a sustained performance in the range of 10 to 20 MIPS (millions of instructions per second). MB86900 design uses a single 20000-gate 1.3- mu m CMOS gate array and operates at a cycle time of 60 ns. CY7601 is a full custom chip designed using a 0.8- mu m CMOS process and operates at a cycle time of 30 ns. The basic features of these processors, their similarities and differences, and the tradeoffs used in their design. Design verification, test generation, and fault simulation are addressed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125183375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47145
S. Trimberger
The author discusses the changes in design methodology and tools that have allowed improved productivity over the last decade, identifying major problems and solutions. He follows with a discussion of coming problems in the 1990s and discusses the tools that will be needed to keep design costs down in the coming decade.<>
{"title":"Integrated circuit design productivity advancements in the 1980s and 1990s","authors":"S. Trimberger","doi":"10.1109/HICSS.1989.47145","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47145","url":null,"abstract":"The author discusses the changes in design methodology and tools that have allowed improved productivity over the last decade, identifying major problems and solutions. He follows with a discussion of coming problems in the 1990s and discusses the tools that will be needed to keep design costs down in the coming decade.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122852645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47181
R. Yung, A. Despain, Y. Patt
The Aquarius numeric processor (ANP) is an extended numeric instruction set architecture that is based on the Berkeley programmed logic machine (PLM) and supports integrated symbolic and numeric calculations. This extension expands the existing numeric data type to include 32- and 64-bit integers and single- and double-precision floating-point numbers conforming to the IEEE Standard P754. A class of data structure called numeric arrays has been added to represent matrices and arrays found in most scientific programming languages. Powerful numeric instructions are included to manipulate these novel data types. The authors describe the programming model and the architecture of the ANP. An experimental ANP is currently under construction using TTL (transistor-transistor logic) and ECL (emitter-coupled logic) parts. Simulated performance results indicate that the system will achieve about 10 MFLOPs (millions of floating-point operations) on the Prolog version of some Whetstone and Linpack benchmarks and close to 20 MFLOPS on some matrix operations (all in double precision).<>
{"title":"Extending a Prolog architecture for high performance numeric computations","authors":"R. Yung, A. Despain, Y. Patt","doi":"10.1109/HICSS.1989.47181","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47181","url":null,"abstract":"The Aquarius numeric processor (ANP) is an extended numeric instruction set architecture that is based on the Berkeley programmed logic machine (PLM) and supports integrated symbolic and numeric calculations. This extension expands the existing numeric data type to include 32- and 64-bit integers and single- and double-precision floating-point numbers conforming to the IEEE Standard P754. A class of data structure called numeric arrays has been added to represent matrices and arrays found in most scientific programming languages. Powerful numeric instructions are included to manipulate these novel data types. The authors describe the programming model and the architecture of the ANP. An experimental ANP is currently under construction using TTL (transistor-transistor logic) and ECL (emitter-coupled logic) parts. Simulated performance results indicate that the system will achieve about 10 MFLOPs (millions of floating-point operations) on the Prolog version of some Whetstone and Linpack benchmarks and close to 20 MFLOPS on some matrix operations (all in double precision).<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128961935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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