Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47182
Y. Chu, K. Itano
The architecture of a top-down parsing coprocessor is presented. This processor aims at fast compilation for programming languages in LL(1) grammar. It accepts a stream of tokens from the lexical coprocessor and produces a stream of codes representing semantic action to be taken by the CPU. The coprocessor organization has a pipeline and two register stacks. The pipeline has four stages during which the production rule for each input token is checked and the semantic rules are selected. One register stack handles the production rules, while the other register stack handles the semantic rules. Only a small set of coprocessor instructions is needed for writing the parsing code and the size of the code is less than ten coprocessor instructions. It is estimated that the parsing coprocessor could produce the codes for possible semantic action at an average rate of 2 million codes per second.<>
{"title":"A top-down parsing co-processor for compilation","authors":"Y. Chu, K. Itano","doi":"10.1109/HICSS.1989.47182","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47182","url":null,"abstract":"The architecture of a top-down parsing coprocessor is presented. This processor aims at fast compilation for programming languages in LL(1) grammar. It accepts a stream of tokens from the lexical coprocessor and produces a stream of codes representing semantic action to be taken by the CPU. The coprocessor organization has a pipeline and two register stacks. The pipeline has four stages during which the production rule for each input token is checked and the semantic rules are selected. One register stack handles the production rules, while the other register stack handles the semantic rules. Only a small set of coprocessor instructions is needed for writing the parsing code and the size of the code is less than ten coprocessor instructions. It is estimated that the parsing coprocessor could produce the codes for possible semantic action at an average rate of 2 million codes per second.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117321698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47184
U. Efron
A review of spatial light modulator (SLM) technologies is presented, including the description and performance parameters of the principal devices and their main applications for optical information processing. The various performance tradeoffs and their impact on emerging technologies and future trends of spatial light modulators are discussed. Three recently introduced SLM devices are briefly described: a multiple-quantum-well-based CCD-addressed SLM; a silicon PLZT SLM; and a deformable-surface SLM.<>
{"title":"Spatial light modulators for optical computing and information processing","authors":"U. Efron","doi":"10.1109/HICSS.1989.47184","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47184","url":null,"abstract":"A review of spatial light modulator (SLM) technologies is presented, including the description and performance parameters of the principal devices and their main applications for optical information processing. The various performance tradeoffs and their impact on emerging technologies and future trends of spatial light modulators are discussed. Three recently introduced SLM devices are briefly described: a multiple-quantum-well-based CCD-addressed SLM; a silicon PLZT SLM; and a deformable-surface SLM.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123569828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47190
T. Yatagai, Y. Suzaki
A general approach is described for optically implementing massively parallel logic. A space-variant logic related to the MIMD (multiple-instruction-multiple-data) logic operation technique is proposed and extended to a ternary logic. A cellular array based on the ternary logic is proposed, and its application to a dynamic interconnection architecture in which optical data flow is changed by an optical control signal is discussed.<>
{"title":"Space-variant optical parallel logic gate technique and its application to cellular logic architectures","authors":"T. Yatagai, Y. Suzaki","doi":"10.1109/HICSS.1989.47190","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47190","url":null,"abstract":"A general approach is described for optically implementing massively parallel logic. A space-variant logic related to the MIMD (multiple-instruction-multiple-data) logic operation technique is proposed and extended to a ternary logic. A cellular array based on the ternary logic is proposed, and its application to a dynamic interconnection architecture in which optical data flow is changed by an optical control signal is discussed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122019200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47135
V. Oklobdzija
A very short turnaround cycle for VLSI is possible due to advances in the integration and fabrication process and supporting CAD (computer-aided design) tools. The ways in which this development affects the design, planning, and architecture of future products are examined.<>
{"title":"Rapid turn-around design style and technology: impact on computer architecture","authors":"V. Oklobdzija","doi":"10.1109/HICSS.1989.47135","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47135","url":null,"abstract":"A very short turnaround cycle for VLSI is possible due to advances in the integration and fabrication process and supporting CAD (computer-aided design) tools. The ways in which this development affects the design, planning, and architecture of future products are examined.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"29 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121232057","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47171
P. Emrath, D. Padua, P. Yew
The Cedar system is clustered shared-memory multiprocessor system. The architecture and the main system features of the Cedar system were designed to meet the following goals: (1) to be a general-purpose high-performance machine for parallel processing; (2) to be scalable both architecturally and physically to a very large system; and (3) to be easy to program with a good environment for user support. To achieve these design goals, software on the Cedar system plays a very important role. The authors describe the relations between the software and the underlying hardware, including the architecture, on the Cedar system.<>
{"title":"Cedar architecture and its software","authors":"P. Emrath, D. Padua, P. Yew","doi":"10.1109/HICSS.1989.47171","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47171","url":null,"abstract":"The Cedar system is clustered shared-memory multiprocessor system. The architecture and the main system features of the Cedar system were designed to meet the following goals: (1) to be a general-purpose high-performance machine for parallel processing; (2) to be scalable both architecturally and physically to a very large system; and (3) to be easy to program with a good environment for user support. To achieve these design goals, software on the Cedar system plays a very important role. The authors describe the relations between the software and the underlying hardware, including the architecture, on the Cedar system.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125673014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47189
J.N. Lee
Analog optical modules must be part of a larger signal-processing system, and it is difficult to pass information from an optical module operating near maximum throughput to the other parts of a signal-processing system. The basis for this difficulty is often thought to be the high bandwidth and large number of channels of the optical module, but more quantitatively, optical modules do not yet have the capability to perform nonlinear operations on partially processed data that would greatly reduce the module output rates. Moreover, they require additional processing for equalization of channel response rather than for representation of useful information, and this processing is often left to the digital postprocessor. Recent work carried out to address the interface difficulty is reported. One avenue is the use of additional optical processing operations at the output of existing optical-processing modules, such as data compression adaptive data thresholding, and various multiplexed readout schemes. Another avenue is to reduce precision requirements by using various adaptive learning techniques inherent in some parallel models of computation, such as neural-net models. A third effort involves development of 2-D, three-terminal, spatial light modulator devices that can provide the needed nonlinear transfer functions, the capability to cascade optical-processing operations, and throughputs greater than those attainable with all-electronic approaches.<>
{"title":"Optical modules for future signal processing systems","authors":"J.N. Lee","doi":"10.1109/HICSS.1989.47189","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47189","url":null,"abstract":"Analog optical modules must be part of a larger signal-processing system, and it is difficult to pass information from an optical module operating near maximum throughput to the other parts of a signal-processing system. The basis for this difficulty is often thought to be the high bandwidth and large number of channels of the optical module, but more quantitatively, optical modules do not yet have the capability to perform nonlinear operations on partially processed data that would greatly reduce the module output rates. Moreover, they require additional processing for equalization of channel response rather than for representation of useful information, and this processing is often left to the digital postprocessor. Recent work carried out to address the interface difficulty is reported. One avenue is the use of additional optical processing operations at the output of existing optical-processing modules, such as data compression adaptive data thresholding, and various multiplexed readout schemes. Another avenue is to reduce precision requirements by using various adaptive learning techniques inherent in some parallel models of computation, such as neural-net models. A third effort involves development of 2-D, three-terminal, spatial light modulator devices that can provide the needed nonlinear transfer functions, the capability to cascade optical-processing operations, and throughputs greater than those attainable with all-electronic approaches.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126261134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47179
A. Singhal, Y. Patt
A description is given of PLUM, a Prolog machine with multiple specialized functional units and memory ports that operate in parallel using data-driven control. Unification parallelism is utilized by multiple unification units. Bookkeeping operations, such as choicepoint and environment manipulation, are executed by special functional units in parallel with unification. The performance of the system is limited mainly by the time spent on unification operations. By using the parallelism among bookkeeping and unification operations, it is estimated that PLUM can achieve a speedup of at least a factor of 4 over the Berkeley PLM, assuming the same cycle time.<>
{"title":"Tailoring functional units and memory in a high performance Prolog architecture","authors":"A. Singhal, Y. Patt","doi":"10.1109/HICSS.1989.47179","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47179","url":null,"abstract":"A description is given of PLUM, a Prolog machine with multiple specialized functional units and memory ports that operate in parallel using data-driven control. Unification parallelism is utilized by multiple unification units. Bookkeeping operations, such as choicepoint and environment manipulation, are executed by special functional units in parallel with unification. The performance of the system is limited mainly by the time spent on unification operations. By using the parallelism among bookkeeping and unification operations, it is estimated that PLUM can achieve a speedup of at least a factor of 4 over the Berkeley PLM, assuming the same cycle time.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132869180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47165
B. Appelbe
The author discusses the following architectures: mini-supercomputers; super-minicomputers; and high performance workstations. Such systems are becoming increasingly important in applications ranging from transaction processing to modeling physical systems, and are blurring the traditional performance/price hierarchy of minicomputers, mainframes, and traditional supercomputers.<>
{"title":"High-performance architectures","authors":"B. Appelbe","doi":"10.1109/HICSS.1989.47165","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47165","url":null,"abstract":"The author discusses the following architectures: mini-supercomputers; super-minicomputers; and high performance workstations. Such systems are becoming increasingly important in applications ranging from transaction processing to modeling physical systems, and are blurring the traditional performance/price hierarchy of minicomputers, mainframes, and traditional supercomputers.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133270585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47147
D. G. Boyer, R. Cordell
The MULGA symbolic design system, which has been in use at Bellcore for design of research VLSI chips, and Bellcore's experience with symbolic design of high-performance VLSI are described. Bellcore's research on a new symbolic design system, DASL, is discussed. The use of symbolic layout in cell-based systems and silicon compilers, and its use in these areas is covered.<>
{"title":"Symbolic layout for rapid full-custom prototyping of high-speed telecommunications chips","authors":"D. G. Boyer, R. Cordell","doi":"10.1109/HICSS.1989.47147","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47147","url":null,"abstract":"The MULGA symbolic design system, which has been in use at Bellcore for design of research VLSI chips, and Bellcore's experience with symbolic design of high-performance VLSI are described. Bellcore's research on a new symbolic design system, DASL, is discussed. The use of symbolic layout in cell-based systems and silicon compilers, and its use in these areas is covered.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127708978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1989-01-03DOI: 10.1109/HICSS.1989.47163
B. Maytal, S. Iacobovici, D. Alpert, D. Biran, J. Levy, Y. Sidi
The NS32532, a third-generation 32-bit microprocessor, is used to examine the effect of the constraints of VLSI semiconductor and packaging technologies, as well as those stemming from the wide variety of systems to which the processor will be applied, on design. Its microarchitecture, fabrication technology, system interface, and design methodology are discussed. The design tradeoffs are considered in the context of system environments that include embedded controllers, personal computers, and multiuser multiprocessors. The problem of partitioning functions to be integrated on chip from those that remain external to the microprocessor is addressed.<>
{"title":"NS32532: case study in general-purpose microprocessor design tradeoffs","authors":"B. Maytal, S. Iacobovici, D. Alpert, D. Biran, J. Levy, Y. Sidi","doi":"10.1109/HICSS.1989.47163","DOIUrl":"https://doi.org/10.1109/HICSS.1989.47163","url":null,"abstract":"The NS32532, a third-generation 32-bit microprocessor, is used to examine the effect of the constraints of VLSI semiconductor and packaging technologies, as well as those stemming from the wide variety of systems to which the processor will be applied, on design. Its microarchitecture, fabrication technology, system interface, and design methodology are discussed. The design tradeoffs are considered in the context of system environments that include embedded controllers, personal computers, and multiuser multiprocessors. The problem of partitioning functions to be integrated on chip from those that remain external to the microprocessor is addressed.<<ETX>>","PeriodicalId":300182,"journal":{"name":"[1989] Proceedings of the Twenty-Second Annual Hawaii International Conference on System Sciences. Volume 1: Architecture Track","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-01-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115621474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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