Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398051
Younsun Kim, Hong-Sik Kim, R. Lee, Sungho Kang
This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor. To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards — the sensor board, the USB board and the switch board — are used. As a verification method, 4-step verification strategy comprised of ARM-core based platform verification, system verification, algorithm verification and performance verification is used. Through this method, the 2M-pixel/3M-pixel ARM-based ISP of CMOS image sensor is verified very effectively before tape-out.
{"title":"FPGA-based verification methodology of SoC-type CMOS image signal processor","authors":"Younsun Kim, Hong-Sik Kim, R. Lee, Sungho Kang","doi":"10.1109/SOCCON.2009.5398051","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398051","url":null,"abstract":"This paper describes a FPGA-based verification methodology for the image signal processor (ISP) of system-on-chip (SoC) type CMOS image sensor. To make a verification environment, the complete ASIC prototyping system, the ARM7 TDMI CoreTile board and external interface boards — the sensor board, the USB board and the switch board — are used. As a verification method, 4-step verification strategy comprised of ARM-core based platform verification, system verification, algorithm verification and performance verification is used. Through this method, the 2M-pixel/3M-pixel ARM-based ISP of CMOS image sensor is verified very effectively before tape-out.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122594002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5397994
K. Einwich, C. Grimm, M. Barnasconi, A. Vachoux
Embedded HW/SW systems interact more and more tightly with their analog physical environment. This leads to systems in which digital HW/SW is functionally interwoven with analog and mixed -signal blocks such as RF interfaces, power electronics, or sensors and actuators. We call such systems Embedded Analog/Mixed-Signal (E-AMS) systems. A challenge for the development of E -AMS systems is to understand the interaction between HW/SW and the analog and mixed-signal subsystems (e.g. power drivers, sensors, RF circuits) at architecture level. This requires means for modeling and simulating the interacting analog/mixed-signal systems and HW/SW systems at functional and architecture level. SystemC supports modeling of HW/SW systems from the abstract algorithm levevel down to RTL by providing a discrete event (DE) simulation framework. Transaction Level Modeling (TLM) allows designers to perform abstract modeling, simulation and design of HW/SW system architectures. However, the SystemC simulation kernel has not been designed for the modeling and simulation of analog, continuous-time systems.
{"title":"Introduction to the SystemC AMS DRAFT standard","authors":"K. Einwich, C. Grimm, M. Barnasconi, A. Vachoux","doi":"10.1109/SOCCON.2009.5397994","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5397994","url":null,"abstract":"Embedded HW/SW systems interact more and more tightly with their analog physical environment. This leads to systems in which digital HW/SW is functionally interwoven with analog and mixed -signal blocks such as RF interfaces, power electronics, or sensors and actuators. We call such systems Embedded Analog/Mixed-Signal (E-AMS) systems. A challenge for the development of E -AMS systems is to understand the interaction between HW/SW and the analog and mixed-signal subsystems (e.g. power drivers, sensors, RF circuits) at architecture level. This requires means for modeling and simulating the interacting analog/mixed-signal systems and HW/SW systems at functional and architecture level. SystemC supports modeling of HW/SW systems from the abstract algorithm levevel down to RTL by providing a discrete event (DE) simulation framework. Transaction Level Modeling (TLM) allows designers to perform abstract modeling, simulation and design of HW/SW system architectures. However, the SystemC simulation kernel has not been designed for the modeling and simulation of analog, continuous-time systems.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122877290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398075
T. Koivisto, E. Tiiliharju
In this paper, we propose a current bleeding oscillator-mixer. This circuit reuses the bleeding current, which relaxes mixer design trade-offs noise, linearity and gain at low supply voltages, by replacing the bleed current source as an oscillator. The linearized merged oscillator-mixer achieves a 8 dB gain, −3 dBV IIP3 and 6.2 dB white noise figure at the 7 GHz frequency. The phase-noise of the oscillator is −98 dBc/Hz at the 1 MHz offset from the 7Ghz LO frequency. The combined circuit consumes 5 mA from a 1.2 V supply.
{"title":"A linearized low-voltage oscillator-mixer","authors":"T. Koivisto, E. Tiiliharju","doi":"10.1109/SOCCON.2009.5398075","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398075","url":null,"abstract":"In this paper, we propose a current bleeding oscillator-mixer. This circuit reuses the bleeding current, which relaxes mixer design trade-offs noise, linearity and gain at low supply voltages, by replacing the bleed current source as an oscillator. The linearized merged oscillator-mixer achieves a 8 dB gain, −3 dBV IIP3 and 6.2 dB white noise figure at the 7 GHz frequency. The phase-noise of the oscillator is −98 dBc/Hz at the 1 MHz offset from the 7Ghz LO frequency. The combined circuit consumes 5 mA from a 1.2 V supply.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398106
J. Lancaster, J. Buhler, R. Chamberlain
Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These specialized architectures can offer higher performance potential in a smaller space, higher power efficiency, and competitive costs. A price is paid, however, in development difficulty in determining functional correctness and understanding the performance of such a system. In this paper we focus on improving the task of performance debugging streaming applications deployed on FPGAs. We describe our runtime performance monitoring infrastructure, its capabilities and overheads on several different configurations of the monitor. We then employ the monitoring system to study the performance effects of provisioning resources for Mercury BLASTN, an implementation of the BLASTN sequence comparison application on an FPGA-accelerated system.
{"title":"Efficient runtime performance monitoring of FPGA-based applications","authors":"J. Lancaster, J. Buhler, R. Chamberlain","doi":"10.1109/SOCCON.2009.5398106","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398106","url":null,"abstract":"Embedded computing platforms have long incorporated non-traditional architectures (e.g., FPGAs, ASICs) to combat the diminishing returns of Moore's Law as applied to traditional processors. These specialized architectures can offer higher performance potential in a smaller space, higher power efficiency, and competitive costs. A price is paid, however, in development difficulty in determining functional correctness and understanding the performance of such a system. In this paper we focus on improving the task of performance debugging streaming applications deployed on FPGAs. We describe our runtime performance monitoring infrastructure, its capabilities and overheads on several different configurations of the monitor. We then employ the monitoring system to study the performance effects of provisioning resources for Mercury BLASTN, an implementation of the BLASTN sequence comparison application on an FPGA-accelerated system.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"2 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132468380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398034
Y. Berg, O. Mirmotahari
In this paper we present a low voltage symmetric and bidirectional current mirror based on clocked semi-floating-gate (CSFG) transistors used in low-voltage digital CMOS circuits [1]. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 200mV. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.
{"title":"Clocked semi-floating-gate ultra low-voltage symmetric and bidirectional current mirror","authors":"Y. Berg, O. Mirmotahari","doi":"10.1109/SOCCON.2009.5398034","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398034","url":null,"abstract":"In this paper we present a low voltage symmetric and bidirectional current mirror based on clocked semi-floating-gate (CSFG) transistors used in low-voltage digital CMOS circuits [1]. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offset voltages are used to shift the effective threshold voltage of the evaluating transistors. The proposed current mirror can operate at supply voltages below 200mV. The simulated data presented are obtained using the Spectre simulator provided by Cadence and valid for a 90nm CMOS process.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116863802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398014
Liang Lu, Máire O’Neill, E. Swartzlander
The ECHO hash function was developed for the NIST cryptographic SHA-3 hash function competition. To evaluate ECHO's performance, high-speed and low-cost ASIC architectures have been designed. The results show that the highperformance architecture can achieve a fastest throughput among AES-based hash function design reported to date among the SHA-3 candidates.
{"title":"ASIC evaluation of ECHO hash function","authors":"Liang Lu, Máire O’Neill, E. Swartzlander","doi":"10.1109/SOCCON.2009.5398014","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398014","url":null,"abstract":"The ECHO hash function was developed for the NIST cryptographic SHA-3 hash function competition. To evaluate ECHO's performance, high-speed and low-cost ASIC architectures have been designed. The results show that the highperformance architecture can achieve a fastest throughput among AES-based hash function design reported to date among the SHA-3 candidates.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114880685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5397995
L. Devlin
Broadband ICs find application in defence, instrumentation and communication applications. This paper details the design, realisation and measured performance of five different MMICs developed for broadband receiver applications. The five MMICs described are: A 0.5 to 20GHz dual channel limiter, a 2 to 18GHz dual channel Low Noise Amplifier (LNA), a DC to 20GHz dual channel Single Pole Double Throw (SPDT) switch, a 2 to 18GHz upconverter and a companion downconverter. Photographs of the ICs are shown in. The MMICs can be used to implement a compact, dual channel 2–18GHz receiver and an example of this is also described.
{"title":"Microwave IC design for broadband receivers","authors":"L. Devlin","doi":"10.1109/SOCCON.2009.5397995","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5397995","url":null,"abstract":"Broadband ICs find application in defence, instrumentation and communication applications. This paper details the design, realisation and measured performance of five different MMICs developed for broadband receiver applications. The five MMICs described are: A 0.5 to 20GHz dual channel limiter, a 2 to 18GHz dual channel Low Noise Amplifier (LNA), a DC to 20GHz dual channel Single Pole Double Throw (SPDT) switch, a 2 to 18GHz upconverter and a companion downconverter. Photographs of the ICs are shown in. The MMICs can be used to implement a compact, dual channel 2–18GHz receiver and an example of this is also described.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116243015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398072
Zhonghai Lu, Dimitris Brachos, A. Jantsch
We have proposed (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where σ bounds the traffic burstiness and ρ the traffic rate. In this paper, we present a hardware implementation of the regulator. We discuss its microarchitecture. Based on this microarchitecture, we design, implement and synthesize a multi-flow regulator for AXI. Our experiments show the effectiveness of such a regulation device on the control of delay, jitter and buffer requirements.
{"title":"A flow regulator for On-Chip Communication","authors":"Zhonghai Lu, Dimitris Brachos, A. Jantsch","doi":"10.1109/SOCCON.2009.5398072","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398072","url":null,"abstract":"We have proposed (σ, ρ)-based flow regulation as a design instrument for System-on-Chip (SoC) architects to control quality-of-service and achieve cost-effective communication, where σ bounds the traffic burstiness and ρ the traffic rate. In this paper, we present a hardware implementation of the regulator. We discuss its microarchitecture. Based on this microarchitecture, we design, implement and synthesize a multi-flow regulator for AXI. Our experiments show the effectiveness of such a regulation device on the control of delay, jitter and buffer requirements.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121921163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398001
Norman Nolte, S. Moch, Markus Kock, P. Pirsch
Decoding of high bitrate video bitstreams is an application field traditionally claimed by dedicated hardware architectures, since embedded general purpose processors are not able to satisfy the high performance requirements of entropy decoding. We present a fully programmable multi-standard bitstream processor. The proposed bit granular memory and data path architecture provides efficient processing and storage capabilities for data words of arbitrary length. Running at a 300 MHz clock frequency, the processor is able to decode, e.g., MPEG-2 and VC-1 1080p HDTV bitstreams with a maximum bitrate of 100 Mbit/s.
{"title":"Memory efficient programmable processor for bitstream processing and entropy decoding of multiple-standard high-bitrate HDTV video bitstreams","authors":"Norman Nolte, S. Moch, Markus Kock, P. Pirsch","doi":"10.1109/SOCCON.2009.5398001","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398001","url":null,"abstract":"Decoding of high bitrate video bitstreams is an application field traditionally claimed by dedicated hardware architectures, since embedded general purpose processors are not able to satisfy the high performance requirements of entropy decoding. We present a fully programmable multi-standard bitstream processor. The proposed bit granular memory and data path architecture provides efficient processing and storage capabilities for data words of arbitrary length. Running at a 300 MHz clock frequency, the processor is able to decode, e.g., MPEG-2 and VC-1 1080p HDTV bitstreams with a maximum bitrate of 100 Mbit/s.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123859489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398041
S. F. Fard, A. Alimohammad, B. Cockburn, C. Schlegel
In this paper, we present a single-chip design for the accelerated verification of multiple-input multiple-output (MIMO) wireless communication systems. Our design integrates the data source, MIMO transmitter, multipath fading channel, MIMO receiver, data sink and error performance measurement on a single chip for prototyping and verification at hardware speeds. The implemented baseband fading channel simulator can be reconfigured interactively to simulate a fading channel using different channel models. The size and performance of our design is illustrated by hardware implementation. Our design methodology can be used to speed up design verification of a wide variety of wireless communication systems.
{"title":"A versatile fading simulator for on-chip verification of MIMO communication systems","authors":"S. F. Fard, A. Alimohammad, B. Cockburn, C. Schlegel","doi":"10.1109/SOCCON.2009.5398041","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398041","url":null,"abstract":"In this paper, we present a single-chip design for the accelerated verification of multiple-input multiple-output (MIMO) wireless communication systems. Our design integrates the data source, MIMO transmitter, multipath fading channel, MIMO receiver, data sink and error performance measurement on a single chip for prototyping and verification at hardware speeds. The implemented baseband fading channel simulator can be reconfigured interactively to simulate a fading channel using different channel models. The size and performance of our design is illustrated by hardware implementation. Our design methodology can be used to speed up design verification of a wide variety of wireless communication systems.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123529037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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