Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398016
M. R. Kakoee, F. Angiolini, S. Murali, A. Pullini, Ciprian Seiculescu, L. Benini
In this paper we present a floorplan-aware toolchain for NoC design and synthesis integrated with a graphical front-end. The resulting design methodology is highly automated yet entails rich interaction with the user, spanning across traffic flow specification, topology synthesis and physical floorplanning, with back-annotation capabilities and opportunities for incremental design. We exploit the proposed tool to implement some NoC-based case studies. We show that not only a great amount of time and effort can be saved thanks to the easy-to-use proposed environment, but also that the quality of the final netlist improves due to the optimizations unlocked by the early-stage interaction among the designer and the proposed toolchain.
{"title":"A floorplan-aware interactive tool flow for NoC design and synthesis","authors":"M. R. Kakoee, F. Angiolini, S. Murali, A. Pullini, Ciprian Seiculescu, L. Benini","doi":"10.1109/SOCCON.2009.5398016","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398016","url":null,"abstract":"In this paper we present a floorplan-aware toolchain for NoC design and synthesis integrated with a graphical front-end. The resulting design methodology is highly automated yet entails rich interaction with the user, spanning across traffic flow specification, topology synthesis and physical floorplanning, with back-annotation capabilities and opportunities for incremental design. We exploit the proposed tool to implement some NoC-based case studies. We show that not only a great amount of time and effort can be saved thanks to the easy-to-use proposed environment, but also that the quality of the final netlist improves due to the optimizations unlocked by the early-stage interaction among the designer and the proposed toolchain.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"13 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134071969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398074
S. Hollis, C. Jackson
Networks-on-Chip (NoCs) are becoming widespread in contemporary multi-core and many-core designs. Amongst their appeals are regularity of layout and flexibility of topology. However, the energy consumed by routing nodes is now vastly more than that of an ALU operation in one of the processing cores they service. We present an evaluation of bypassing, a technique where selected traffic can avoid the full routing functionality of selected nodes in a NoC. When implemented correctly, bypassing can dramatically reduce the overall energy consumption of data flowing through the network. We address the questions of when bypassing should be deployed at a given node, how much energy will be saved by doing so, and present some equations to quantify and answer these questions. We show that if 74–80% of data, depending on router implementation, is destined for a node further away than that employing bypassing, then bypassing is energy-effective. Using these figures, we define guidelines for the use of bypassing for a wide variety of NoC designs.
{"title":"When does Network-on-Chip bypassing make sense?","authors":"S. Hollis, C. Jackson","doi":"10.1109/SOCCON.2009.5398074","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398074","url":null,"abstract":"Networks-on-Chip (NoCs) are becoming widespread in contemporary multi-core and many-core designs. Amongst their appeals are regularity of layout and flexibility of topology. However, the energy consumed by routing nodes is now vastly more than that of an ALU operation in one of the processing cores they service. We present an evaluation of bypassing, a technique where selected traffic can avoid the full routing functionality of selected nodes in a NoC. When implemented correctly, bypassing can dramatically reduce the overall energy consumption of data flowing through the network. We address the questions of when bypassing should be deployed at a given node, how much energy will be saved by doing so, and present some equations to quantify and answer these questions. We show that if 74–80% of data, depending on router implementation, is destined for a node further away than that employing bypassing, then bypassing is energy-effective. Using these figures, we define guidelines for the use of bypassing for a wide variety of NoC designs.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133171183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398082
Yi-Ming Chang, Ming-Hung Chang, W. Hwang
This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range of the ADMDLL, we proposed the self-estimated successive approximation register-controlled (SESAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakage-reduced delay unit can save 12% leakage power consumption. After locking, the dynamic frequency monitor window is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520μW at 1.25GHz/1.0V, and 2.1 μW at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.
{"title":"A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm","authors":"Yi-Ming Chang, Ming-Hung Chang, W. Hwang","doi":"10.1109/SOCCON.2009.5398082","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398082","url":null,"abstract":"This paper presents an all-digital multiphase delay-locked loop (ADMDLL) for wide-locking range and micro-power applications. To enhance locking range of the ADMDLL, we proposed the self-estimated successive approximation register-controlled (SESAR) algorithm, which uses the frequency-estimation selector (FES) to avoid harmonic lock issue. In addition, the FES can reuse the delay line to reduce circuit area and power dissipation significantly. By using the stack effect, the proposed leakage-reduced delay unit can save 12% leakage power consumption. After locking, the dynamic frequency monitor window is proposed to compensation phase error caused by PVT variations. The proposed ADMDLL is capable of operating in wide supply voltage range from 0.3V to 1.0V. The power dissipation is only 520μW at 1.25GHz/1.0V, and 2.1 μW at 13MHz/0.3V, respectively. This work is based on UMC 90nm standard CMOS technology.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"248 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398027
Frank Rogin, R. Drechsler, Steffen Rülke
Designing system-on-a-chip (SoC) using system-level languages is becoming a standard in industry. However, the non-deterministic semantics of such parallel languages could yield failures that are hard to debug. In this paper, we present a new approach that supports automatic debugging of SoC designs written in SystemC using a method that isolates failure-inducing process schedules.
{"title":"Automatic debugging of System-on-a-Chip designs","authors":"Frank Rogin, R. Drechsler, Steffen Rülke","doi":"10.1109/SOCCON.2009.5398027","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398027","url":null,"abstract":"Designing system-on-a-chip (SoC) using system-level languages is becoming a standard in industry. However, the non-deterministic semantics of such parallel languages could yield failures that are hard to debug. In this paper, we present a new approach that supports automatic debugging of SoC designs written in SystemC using a method that isolates failure-inducing process schedules.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124192119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398022
S. Majzoub, R. Saleh, S. Wilton, R. Ward
In this paper, we present a novel solution to the Voltage Selection Problem for large multi-core architectures. Compared to previous algorithms, ours provides similar results, but is more than 10x faster. This run-time improvement is important, especially for large multi-core platforms with hundreds of cores. We evaluate our algorithm in the context of a process, voltage, and temperature (PVT) variation-aware energy optimization framework.
{"title":"Removal-Cost Method: An efficient voltage selection algorithm for multi-core platforms under PVT","authors":"S. Majzoub, R. Saleh, S. Wilton, R. Ward","doi":"10.1109/SOCCON.2009.5398022","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398022","url":null,"abstract":"In this paper, we present a novel solution to the Voltage Selection Problem for large multi-core architectures. Compared to previous algorithms, ours provides similar results, but is more than 10x faster. This run-time improvement is important, especially for large multi-core platforms with hundreds of cores. We evaluate our algorithm in the context of a process, voltage, and temperature (PVT) variation-aware energy optimization framework.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124366616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398043
Philipp A. Hartmann, Philipp Reinkemeier, A. Rettberg, W. Nebel
In this paper the modelling of a physical control system with SystemC AMS is described. The presented example, a crane controller, is compared with a Matlab/Simulink model in terms of simulation performance and accuracy. Due to numerical stability issues of the canonical implementation of the physical model, an external solver is integrated into the simulation.
{"title":"Modelling control systems in SystemC AMS — Benefits and limitations","authors":"Philipp A. Hartmann, Philipp Reinkemeier, A. Rettberg, W. Nebel","doi":"10.1109/SOCCON.2009.5398043","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398043","url":null,"abstract":"In this paper the modelling of a physical control system with SystemC AMS is described. The presented example, a crane controller, is compared with a Matlab/Simulink model in terms of simulation performance and accuracy. Due to numerical stability issues of the canonical implementation of the physical model, an external solver is integrated into the simulation.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124401103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398052
H. Geng, Weiqian Liang, Ming Dong
Most of the present high-performance speech recognition systems are based on CHMM (Continuous Hidden Markov Model) algorithm, however, for embedded systems, it involves much computational cost. This paper solves this problem by proposing a SoC composed of ARM7TDMI, and a co-processor MSAC (Multiplier Square Accumulate Calculation) used to calculate the Mahalanobis distance. Testing with 358-state 3-mixture 27-feature HMM model on Actel ProASIC series FPGA M7A3P1000, the SoC at 24MHZ reaches 1.54 times real-time, and its power consumption is 0.56 mW/MHz.
{"title":"A speech recognition SoC based on ARM7-TDMI core and a MSAC co-processor","authors":"H. Geng, Weiqian Liang, Ming Dong","doi":"10.1109/SOCCON.2009.5398052","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398052","url":null,"abstract":"Most of the present high-performance speech recognition systems are based on CHMM (Continuous Hidden Markov Model) algorithm, however, for embedded systems, it involves much computational cost. This paper solves this problem by proposing a SoC composed of ARM7TDMI, and a co-processor MSAC (Multiplier Square Accumulate Calculation) used to calculate the Mahalanobis distance. Testing with 358-state 3-mixture 27-feature HMM model on Actel ProASIC series FPGA M7A3P1000, the SoC at 24MHZ reaches 1.54 times real-time, and its power consumption is 0.56 mW/MHz.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117284617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398023
Yongping Liu, S. Sezer, J. McCanny
This work presents a novel algorithm for decomposing NFA automata into one-state-active modules for parallel execution on Multiprocessor Systems on Chip (MP-SoC). Furthermore, performance related studies based on a 16-PE system for Snort, Bro and Linux-L7 regular expressions are presented.
{"title":"NFA decomposition and multiprocessing architecture for parallel regular expression processing","authors":"Yongping Liu, S. Sezer, J. McCanny","doi":"10.1109/SOCCON.2009.5398023","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398023","url":null,"abstract":"This work presents a novel algorithm for decomposing NFA automata into one-state-active modules for parallel execution on Multiprocessor Systems on Chip (MP-SoC). Furthermore, performance related studies based on a 16-PE system for Snort, Bro and Linux-L7 regular expressions are presented.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121955530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398054
Jin-Tai Yan, Zhi-Wei Chen
Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2-dimensional bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the power dissipation with only 15% hardware overhead on the average for 4×4, 8×8 and 16×16 multipliers.
{"title":"Low-power multiplier design with row and column bypassing","authors":"Jin-Tai Yan, Zhi-Wei Chen","doi":"10.1109/SOCCON.2009.5398054","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398054","url":null,"abstract":"Based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier, a low-power multiplier design with row and column bypassing is proposed. Compared with the row-bypassing multiplier, the column-bypassing multipliers and the 2-dimensional bypass multiplier for 20 tested examples, the experimental results show that our proposed multiplier reduces 25.7% of the power dissipation with only 15% hardware overhead on the average for 4×4, 8×8 and 16×16 multipliers.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128835631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398091
Yan Wang, G. Temes
A new double-sampling architecture is proposed for wideband low-power ΔΣ ADC design. A direct-charge-transfer adder is used to reduce the bandwidth requirements for the adder, and the loop filter's linearity requirement is relaxed by using a low-distortion topology. To verify the proposed design methodology, a 2nd order double-sampling delta-sigma ADC using the proposed scheme has been designed and simulated.
{"title":"Low-distortion double-sampling ΔΣ ADC using a direct-charge-transfer adder","authors":"Yan Wang, G. Temes","doi":"10.1109/SOCCON.2009.5398091","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398091","url":null,"abstract":"A new double-sampling architecture is proposed for wideband low-power ΔΣ ADC design. A direct-charge-transfer adder is used to reduce the bandwidth requirements for the adder, and the loop filter's linearity requirement is relaxed by using a low-distortion topology. To verify the proposed design methodology, a 2nd order double-sampling delta-sigma ADC using the proposed scheme has been designed and simulated.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"46 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114032400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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