Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398032
Wan-Yu Lee, I. Jiang, Tsung-Wan Mei
The success of 3D ICs requires novel EDA techniques. Among them, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. We first derive logical formulations for 3D IC partitioning problems and then transform the formulations into integer linear programs (ILPs). The ILPs can minimize the footprint and the usage of vertical interconnects simultaneously. Our results conducted on the GSRC benchmark show that our approach outperforms the extended multi-way partitioning method in the usage of vertical interconnects under the same footprint settings. More importantly, our approach is very flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstract levels, e.g., from the architectural level down to the physical level. This flexibility makes the ILP formulations superior alternatives to the 3D IC partitioning problems.
{"title":"Generic integer linear programming formulation for 3D IC partitioning","authors":"Wan-Yu Lee, I. Jiang, Tsung-Wan Mei","doi":"10.1109/SOCCON.2009.5398032","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398032","url":null,"abstract":"The success of 3D ICs requires novel EDA techniques. Among them, this paper focuses on 3D IC partitioning, especially at the architectural level to maximize its benefits. We first derive logical formulations for 3D IC partitioning problems and then transform the formulations into integer linear programs (ILPs). The ILPs can minimize the footprint and the usage of vertical interconnects simultaneously. Our results conducted on the GSRC benchmark show that our approach outperforms the extended multi-way partitioning method in the usage of vertical interconnects under the same footprint settings. More importantly, our approach is very flexible and can readily extend to the partitioning problems with variant objectives and constraints, and with different abstract levels, e.g., from the architectural level down to the physical level. This flexibility makes the ILP formulations superior alternatives to the 3D IC partitioning problems.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122987904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398092
Dongheon Lee, Seunghun Kim, Jooho Hwang, Junho Moon, Minkyu Song
In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply.
{"title":"Design of a 1.8V 8-bit 1GSPS cascaded-folding CMOS A/D converter based on a folder averaging technique","authors":"Dongheon Lee, Seunghun Kim, Jooho Hwang, Junho Moon, Minkyu Song","doi":"10.1109/SOCCON.2009.5398092","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398092","url":null,"abstract":"In this paper, a CMOS analog-to-digital converter (ADC) with an 8-bit 1GSPS at 1.8V is designed. The architecture of the proposed ADC is based on a folding ADC with a cascaded-folding and an interpolation structure. A self-linearized preamplifier with source degeneration technique and a folder averaging technique for the high-performance are introduced. Further, a novel auto-switching encoder is also proposed. The chip has been fabricated with 0.18μm 1-poly 5-metal CMOS technology. The active chip area is 0.72mm2 and it consumes about 200mW at 1.8V power supply.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126346409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398053
F. Moradi, D. Wisland, H. Mahmoodi, T. Cao
In this paper a new technique to increase the write margin of 6T-SRAM cell is proposed. Using this technique the area of subthreshold SRAM cell is reduced and also the Write cycle is improved significantly with a lower area overhead. In this technique, PMOS stacked network is used to evaluate the write cycle. Based on behavior of devices in 65nm for weak inversion operation, this technique is proposed to decrease area overhead of 6T-SRAM in subthreshold region.
{"title":"Improved write margin 6T-SRAM for low supply voltage applications","authors":"F. Moradi, D. Wisland, H. Mahmoodi, T. Cao","doi":"10.1109/SOCCON.2009.5398053","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398053","url":null,"abstract":"In this paper a new technique to increase the write margin of 6T-SRAM cell is proposed. Using this technique the area of subthreshold SRAM cell is reduced and also the Write cycle is improved significantly with a lower area overhead. In this technique, PMOS stacked network is used to evaluate the write cycle. Based on behavior of devices in 65nm for weak inversion operation, this technique is proposed to decrease area overhead of 6T-SRAM in subthreshold region.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125850155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398067
Kuen-Jong Lee, Si-Yuan Liang, A. Su
While the complexity of System-on-a-Chip (SoC) design keeps growing rapidly today the need for an efficient approach to catch design errors at silicon stage has become an urgent issue. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi-core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also developed to cooperate with the debug platform. Together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.
{"title":"A low-cost SOC debug platform based on on-chip test architectures","authors":"Kuen-Jong Lee, Si-Yuan Liang, A. Su","doi":"10.1109/SOCCON.2009.5398067","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398067","url":null,"abstract":"While the complexity of System-on-a-Chip (SoC) design keeps growing rapidly today the need for an efficient approach to catch design errors at silicon stage has become an urgent issue. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi-core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also developed to cooperate with the debug platform. Together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117081695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398066
M. Graziano, M. Vittori
Power Supply Noise (PSN) is one of the main concerns in scaled technology circuits, both if performance reliability must be assured and if power supply is to be dynamically reduced for dissipation regulation. In this paper we propose a new system for digitally sensing Power Supply and Ground levels that can be both transferred to the output for verification purposes and used by a control block within the circuit under test (CUT) for the activation of power aware policies. The sensor system shows very low overhead in terms of power and area, and works at the nominal CUT frequency. It allows to change on-site the Power Supply and Ground ranges to be sensed and, after a fine tuning, can be arranged for a process variation aware measures. This sensor is fully digital and standard cell based and can be used for every type of architecture on a systematic basis for PSN measure as scan chains are for fault verification. It thus represents a change of paradigm in the way in which PSN measure systems are thought nowadays.
{"title":"A fully digital power supply noise thermometer","authors":"M. Graziano, M. Vittori","doi":"10.1109/SOCCON.2009.5398066","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398066","url":null,"abstract":"Power Supply Noise (PSN) is one of the main concerns in scaled technology circuits, both if performance reliability must be assured and if power supply is to be dynamically reduced for dissipation regulation. In this paper we propose a new system for digitally sensing Power Supply and Ground levels that can be both transferred to the output for verification purposes and used by a control block within the circuit under test (CUT) for the activation of power aware policies. The sensor system shows very low overhead in terms of power and area, and works at the nominal CUT frequency. It allows to change on-site the Power Supply and Ground ranges to be sensed and, after a fine tuning, can be arranged for a process variation aware measures. This sensor is fully digital and standard cell based and can be used for every type of architecture on a systematic basis for PSN measure as scan chains are for fault verification. It thus represents a change of paradigm in the way in which PSN measure systems are thought nowadays.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114631777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398108
W. Luk, J. Coutinho, T. Todman, Y. Lam, W. Osborne, Kong Woei Susanto, Qiang Liu, W. Wong
This paper describes Harmonic, a toolchain that targets multiprocessor heterogeneous systems comprising different types of processing elements such as general-purposed processors (GPPs), digital signal processors (DSP), and field-programmable gate arrays (FPGAs) from a high-level C program. The main goal of Harmonic is to improve an application by partitioning and optimising each part of the program, and selecting the most appropriate processing element in the system to execute each part. The core tools include a task transformation engine, a mapping selector, a data representation optimiser, and a hardware synthesiser. We also use the C language with source-annotations as intermediate representation for the toolchain, making it easier for users to understand and to control the compilation process.
{"title":"A high-level compilation toolchain for heterogeneous systems","authors":"W. Luk, J. Coutinho, T. Todman, Y. Lam, W. Osborne, Kong Woei Susanto, Qiang Liu, W. Wong","doi":"10.1109/SOCCON.2009.5398108","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398108","url":null,"abstract":"This paper describes Harmonic, a toolchain that targets multiprocessor heterogeneous systems comprising different types of processing elements such as general-purposed processors (GPPs), digital signal processors (DSP), and field-programmable gate arrays (FPGAs) from a high-level C program. The main goal of Harmonic is to improve an application by partitioning and optimising each part of the program, and selecting the most appropriate processing element in the system to execute each part. The core tools include a task transformation engine, a mapping selector, a data representation optimiser, and a hardware synthesiser. We also use the C language with source-annotations as intermediate representation for the toolchain, making it easier for users to understand and to control the compilation process.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114721070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398007
Hari Kannan, M. Budiu, John D. Davis, Girish Venkataramani
We propose using a profiling-based technique (Dynamic Critical Path) to guide SoC optimization. Optimizing SoCs composed of many modules involves exploring a large space of possible configurations (exponential in the number of component modules). We present this optimization technique applied to a Globally Asynchronous Locally Synchronous (GALS) RTL design. Furthermore, we investigate the loss of precision when abstract versions of hardware modules are used for the critical path computation. Using the critical path provides very fast convergence towards optimal or near-optimal solutions when analyzing large configuration spaces by optimizing the design for composite optimization metrics, such as energy-delay.
{"title":"Tuning SoCs using the global dynamic critical path","authors":"Hari Kannan, M. Budiu, John D. Davis, Girish Venkataramani","doi":"10.1109/SOCCON.2009.5398007","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398007","url":null,"abstract":"We propose using a profiling-based technique (Dynamic Critical Path) to guide SoC optimization. Optimizing SoCs composed of many modules involves exploring a large space of possible configurations (exponential in the number of component modules). We present this optimization technique applied to a Globally Asynchronous Locally Synchronous (GALS) RTL design. Furthermore, we investigate the loss of precision when abstract versions of hardware modules are used for the critical path computation. Using the critical path provides very fast convergence towards optimal or near-optimal solutions when analyzing large configuration spaces by optimizing the design for composite optimization metrics, such as energy-delay.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126761822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398002
Yongseok Jin, Hyuk-Jae Lee
This paper proposes a novel frame memory compression algorithm, called Pixel-Parallel SPIHT (PPS) that processes image data in parallel to increase the encoding throughput. The throughput of a PPS coder is an average of 4.48 bits per cycle which is 48.7 times larger than that of No List SPIHT.
{"title":"Pixel-Parallel SPIHT for frame memory compression","authors":"Yongseok Jin, Hyuk-Jae Lee","doi":"10.1109/SOCCON.2009.5398002","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398002","url":null,"abstract":"This paper proposes a novel frame memory compression algorithm, called Pixel-Parallel SPIHT (PPS) that processes image data in parallel to increase the encoding throughput. The throughput of a PPS coder is an average of 4.48 bits per cycle which is 48.7 times larger than that of No List SPIHT.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130214684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398039
A. Ghani, L. McDaid, A. Belatreche, Waqar Ahmed
In neuro-inspired computing, cortical columns or microcircuits appear to be the basic unit of computation for recognition related tasks. This paper proposes an integrated framework for an efficient implementation of a cortical column on reconfigurable platform (FPGAs). A novel hardware/software co-design implementation strategy is devised and the functionality is tested in the context of speech recognition application. An overall accuracy of 98% was achieved with the fixed-point hardware/software co-design technique in comparison to the 100% with the floating-point software implementation.
{"title":"Neuro inspired reconfigurable architecture for hardware/software co-design","authors":"A. Ghani, L. McDaid, A. Belatreche, Waqar Ahmed","doi":"10.1109/SOCCON.2009.5398039","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398039","url":null,"abstract":"In neuro-inspired computing, cortical columns or microcircuits appear to be the basic unit of computation for recognition related tasks. This paper proposes an integrated framework for an efficient implementation of a cortical column on reconfigurable platform (FPGAs). A novel hardware/software co-design implementation strategy is devised and the functionality is tested in the context of speech recognition application. An overall accuracy of 98% was achieved with the fixed-point hardware/software co-design technique in comparison to the 100% with the floating-point software implementation.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129531932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-01DOI: 10.1109/SOCCON.2009.5398037
Ambarish Roy, B. Barber, K. Prasad
A unique methodology involving Bulk Acoustic Wave (BAW) Solidly Mounted Resonators (SMRs) is presented in this paper which can be used to extract precise materials information that is vital to designing high performance RF filters. The novel approach allows simultaneous extraction of multiple parameters for multiple materials. Changes in materials properties over temperature can also be extracted.
{"title":"RF-MEMS resonator design for parameter characterization","authors":"Ambarish Roy, B. Barber, K. Prasad","doi":"10.1109/SOCCON.2009.5398037","DOIUrl":"https://doi.org/10.1109/SOCCON.2009.5398037","url":null,"abstract":"A unique methodology involving Bulk Acoustic Wave (BAW) Solidly Mounted Resonators (SMRs) is presented in this paper which can be used to extract precise materials information that is vital to designing high performance RF filters. The novel approach allows simultaneous extraction of multiple parameters for multiple materials. Changes in materials properties over temperature can also be extracted.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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