Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841914
S. Weidling, M. Gössel
In this paper, a new method for the design of fault-tolerant linear state machines with initial state 0 and one-dimensional input and one-dimensional output is proposed. It is shown that the LFSR-implementation of the transfer function of a linear automaton can be utilized to correct transient errors in the memory elements. Since the state vector of a linear automaton is uniquely determined by the last n inputs and outputs, a transient error in a memory element can be corrected within n clock cycles by use of the corrected output symbols, where n is the number of components of the state vector. Experimental results have shown that the lowest area overhead can be obtained if the linear state machine is duplicated and a single parity bit is used to distinguish which of the duplicated machines is correct. In this case, an area overhead of 177 % for an 8-bit state vector and 160% for a 256-bit state vector is achieved.
{"title":"Fault tolerant linear state machines","authors":"S. Weidling, M. Gössel","doi":"10.1109/LATW.2014.6841914","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841914","url":null,"abstract":"In this paper, a new method for the design of fault-tolerant linear state machines with initial state 0 and one-dimensional input and one-dimensional output is proposed. It is shown that the LFSR-implementation of the transfer function of a linear automaton can be utilized to correct transient errors in the memory elements. Since the state vector of a linear automaton is uniquely determined by the last n inputs and outputs, a transient error in a memory element can be corrected within n clock cycles by use of the corrected output symbols, where n is the number of components of the state vector. Experimental results have shown that the lowest area overhead can be obtained if the linear state machine is duplicated and a single parity bit is used to distinguish which of the duplicated machines is correct. In this case, an area overhead of 177 % for an 8-bit state vector and 160% for a 256-bit state vector is achieved.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130037033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841926
S. Kostin, J. Raik, R. Ubar, M. Jenihhin, F. Vargas, L. Bolzani, T. Copetti
One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical gates in nanoscale logic. The method is based on static timing analysis that provides delay critical paths under NBTI-induced delay degradation. An analysis on these critical paths is performed in order to select the set of gates that have the highest influence on circuit aging. These gates are to be hardened against NBTI aging effects guaranteeing correct circuit behavior under the given timing and circuit lifetime constraints. The proposed approach is demonstrated on an industrial ALU circuit design.
{"title":"Hierarchical identification of NBTI-critical gates in nanoscale logic","authors":"S. Kostin, J. Raik, R. Ubar, M. Jenihhin, F. Vargas, L. Bolzani, T. Copetti","doi":"10.1109/LATW.2014.6841926","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841926","url":null,"abstract":"One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the switching threshold voltage of pMOS transistors and as a result slows down signal propagation along the paths between flip-flops, thus causing functional failures in the circuit. In this paper we propose an approach to identify NBTI-critical gates in nanoscale logic. The method is based on static timing analysis that provides delay critical paths under NBTI-induced delay degradation. An analysis on these critical paths is performed in order to select the set of gates that have the highest influence on circuit aging. These gates are to be hardened against NBTI aging effects guaranteeing correct circuit behavior under the given timing and circuit lifetime constraints. The proposed approach is demonstrated on an industrial ALU circuit design.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134619353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841922
Felipe Restrepo-Calle, S. Cuenca-Asensi, A. Martínez-Álvarez, E. Chielle, F. Kastensmidt
This paper presents a metric to estimate the register file criticality in processor-based systems. Due to project constrains, it is mandatory to identify and prioritize the most critical registers to protect when a selective fault mitigation approach is needed. The metric is based on the combination of three different criteria, which are computed dynamically during run-time. The applicability and accuracy of the metric have been evaluated in a set of applications running in the miniMIPS and PicoBlaze microprocessors.
{"title":"Efficient metric for register file criticality in processor-based systems","authors":"Felipe Restrepo-Calle, S. Cuenca-Asensi, A. Martínez-Álvarez, E. Chielle, F. Kastensmidt","doi":"10.1109/LATW.2014.6841922","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841922","url":null,"abstract":"This paper presents a metric to estimate the register file criticality in processor-based systems. Due to project constrains, it is mandatory to identify and prioritize the most critical registers to protect when a selective fault mitigation approach is needed. The metric is based on the combination of three different criteria, which are computed dynamically during run-time. The applicability and accuracy of the metric have been evaluated in a set of applications running in the miniMIPS and PicoBlaze microprocessors.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121733887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841904
Luca Piccolboni, G. Pravadelli
Simulation-based approaches that require to drive the design under verification (DUV) to specific conditions, like for example, scenario-based testing and dynamic assertion-based verification (ABV), cannot rely on generic coverage-driven stimuli generators. On the contrary, constraint-based generation must be adopted. In this context, among several solutions, the Universal Verification Methodology (UVM) and the SystemC Verification Library (SCV) represent the main alternatives. However, their powerfulness is paid in term of easiness of use. In fact, their application generally requires to write complex pieces of code to specify the constraints that must be satisfied by the stimuli generator to produce the desired sequences of values. More is the complexity of setting up an effective stimuli generator, more is the risk of failing to capture the right behaviour and/or having a longer verification time. To overcome these problems, the paper presents a framework and a corresponding language for the automatic generation of stimuli that requires to write intuitive and compact directives representing the desired constraints. The approach is independent from the language adopted for the DUV implementation and it works for both embedded hardware as well as embedded software.
{"title":"Simplified stimuli generation for scenario and assertion based verification","authors":"Luca Piccolboni, G. Pravadelli","doi":"10.1109/LATW.2014.6841904","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841904","url":null,"abstract":"Simulation-based approaches that require to drive the design under verification (DUV) to specific conditions, like for example, scenario-based testing and dynamic assertion-based verification (ABV), cannot rely on generic coverage-driven stimuli generators. On the contrary, constraint-based generation must be adopted. In this context, among several solutions, the Universal Verification Methodology (UVM) and the SystemC Verification Library (SCV) represent the main alternatives. However, their powerfulness is paid in term of easiness of use. In fact, their application generally requires to write complex pieces of code to specify the constraints that must be satisfied by the stimuli generator to produce the desired sequences of values. More is the complexity of setting up an effective stimuli generator, more is the risk of failing to capture the right behaviour and/or having a longer verification time. To overcome these problems, the paper presents a framework and a corresponding language for the automatic generation of stimuli that requires to write intuitive and compact directives representing the desired constraints. The approach is independent from the language adopted for the DUV implementation and it works for both embedded hardware as well as embedded software.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126861768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841907
W. Mansour, P. Ramos, R. Ayoubi, R. Velazco
An approach to study the effects of single event upsets (SEU) by fault injection performed at system-level is presented. It is illustrated by results obtained on two different versions of a matrix multiplication algorithm, one standard and the second with fault tolerance capabilities. The final goal of this work is to validate fault tolerance techniques implemented at software level and provide a feedback about the weakest variables, improving thus their capabilities to tolerate faults.
{"title":"SEU fault-injection at system level: Method, tools and preliminary results","authors":"W. Mansour, P. Ramos, R. Ayoubi, R. Velazco","doi":"10.1109/LATW.2014.6841907","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841907","url":null,"abstract":"An approach to study the effects of single event upsets (SEU) by fault injection performed at system-level is presented. It is illustrated by results obtained on two different versions of a matrix multiplication algorithm, one standard and the second with fault tolerance capabilities. The final goal of this work is to validate fault tolerance techniques implemented at software level and provide a feedback about the weakest variables, improving thus their capabilities to tolerate faults.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127515467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841930
S. Larguech, F. Azaïs, S. Bernard, V. Kerzérho, M. Comte, M. Renovell
This paper is in the field of Analog or RF integrated circuit testing. The conventional practice for testing those circuits relies on the measurement of the device-under-test (DUT) specifications. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring directly them. The objective of this paper is to perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is discussed in terms of model accuracy and predictions robustness. Results are illustrated on a Power Amplifier (PA) test vehicle for which we have experimental test data on 10,000 circuits.
{"title":"Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing","authors":"S. Larguech, F. Azaïs, S. Bernard, V. Kerzérho, M. Comte, M. Renovell","doi":"10.1109/LATW.2014.6841930","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841930","url":null,"abstract":"This paper is in the field of Analog or RF integrated circuit testing. The conventional practice for testing those circuits relies on the measurement of the device-under-test (DUT) specifications. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring directly them. The objective of this paper is to perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is discussed in terms of model accuracy and predictions robustness. Results are illustrated on a Power Amplifier (PA) test vehicle for which we have experimental test data on 10,000 circuits.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"57 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841902
Omar Abdelmalek, D. Hély, V. Beroulle
In order to increase the robustness of a RFID digital circuit against SEUs, fault injection is commonly used to locate weak areas. In circuit-emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to the digital baseband of an UHF RFID tag during the communication with a RFID reader. A large number of fault campaigns have been performed in order to identify the most sensitive parts in the digital baseband. Following this analysis, a first low cost countermeasure is introduced and validated.
{"title":"Fault tolerance evaluation of RFID tags","authors":"Omar Abdelmalek, D. Hély, V. Beroulle","doi":"10.1109/LATW.2014.6841902","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841902","url":null,"abstract":"In order to increase the robustness of a RFID digital circuit against SEUs, fault injection is commonly used to locate weak areas. In circuit-emulation is a very powerful tool to locate these areas by executing huge fault injection campaigns. In this work, fault injection has been extensively applied to the digital baseband of an UHF RFID tag during the communication with a RFID reader. A large number of fault campaigns have been performed in order to identify the most sensitive parts in the digital baseband. Following this analysis, a first low cost countermeasure is introduced and validated.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"74 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126270210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841913
Werner Nedel, F. Kastensmidt, J. Azambuja
Graphic Processing Units have become popular in a broad range of applications due to their high computational power and low prices. Among the applications are the safety critical ones, where fault tolerance is mandatory. This paper presents the implementation of a CUDA core, the main processing core of a GPU and its evaluation under Single Event Transients. Results will be able to help designers to develop the required fault tolerant techniques in an effective fashion.
{"title":"Implementation and experimental evaluation of a CUDA core under single event effects","authors":"Werner Nedel, F. Kastensmidt, J. Azambuja","doi":"10.1109/LATW.2014.6841913","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841913","url":null,"abstract":"Graphic Processing Units have become popular in a broad range of applications due to their high computational power and low prices. Among the applications are the safety critical ones, where fault tolerance is mandatory. This paper presents the implementation of a CUDA core, the main processing core of a GPU and its evaluation under Single Event Transients. Results will be able to help designers to develop the required fault tolerant techniques in an effective fashion.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128265880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841925
R. Guazzelli, G. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans
Interest in asynchronous circuits has increased in the VLSI research community due to the growing limitations faced during the design of synchronous circuits, which often result in over constrained design and operation. Albeit a wide variety of techniques for designing asynchronous circuits are available, quasi-delay-insensitive approaches are often preferable due to their simple timing analysis and closure. Null Convention Logic is a style that supports quasi-delay-insensitive design and enables power-, area- and speed-efficient circuits using a standard-cell methodology. However, the correct functionality of such circuits can be jeopardized by transients caused by single event effects, which can generate single event upsets. This work evaluates how Schmitt triggers on output inverters can help mitigating such problems in Null Convention Logic gates and if this approach is sufficient.
{"title":"Schmitt trigger on output inverters of NCL gates for soft error hardening: Is it enough?","authors":"R. Guazzelli, G. Heck, Matheus T. Moreira, Ney Laert Vilar Calazans","doi":"10.1109/LATW.2014.6841925","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841925","url":null,"abstract":"Interest in asynchronous circuits has increased in the VLSI research community due to the growing limitations faced during the design of synchronous circuits, which often result in over constrained design and operation. Albeit a wide variety of techniques for designing asynchronous circuits are available, quasi-delay-insensitive approaches are often preferable due to their simple timing analysis and closure. Null Convention Logic is a style that supports quasi-delay-insensitive design and enables power-, area- and speed-efficient circuits using a standard-cell methodology. However, the correct functionality of such circuits can be jeopardized by transients caused by single event effects, which can generate single event upsets. This work evaluates how Schmitt triggers on output inverters can help mitigating such problems in Null Convention Logic gates and if this approach is sufficient.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132138044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841928
Hsun-Cheng Lee, J. Abraham
Harmonic distortion correction (HDC) is an effective digital calibration technique to estimate and correct errors and distortions in an analog circuit. However, the convergence time is still a concern. In this paper, we propose the injection of a periodic 3-bit gray code sequence for HDC to digitally calibrate an 8-bit delay line ADC. In our simulation results, digital calibration with the gray code injection improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB, with a 13.5 milliseconds calibration time, which is 64X faster than with injection of pseudorandom numbers (860 milliseconds). Also the SNDR converges to 41.6 dB after averaging 224 samples, while the SNDR with injection of pseudorandom numbers converges to 41.5 dB after 237 samples.
{"title":"Harmonic distortion correction for 8-bit delay line ADC using gray code","authors":"Hsun-Cheng Lee, J. Abraham","doi":"10.1109/LATW.2014.6841928","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841928","url":null,"abstract":"Harmonic distortion correction (HDC) is an effective digital calibration technique to estimate and correct errors and distortions in an analog circuit. However, the convergence time is still a concern. In this paper, we propose the injection of a periodic 3-bit gray code sequence for HDC to digitally calibrate an 8-bit delay line ADC. In our simulation results, digital calibration with the gray code injection improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB, with a 13.5 milliseconds calibration time, which is 64X faster than with injection of pseudorandom numbers (860 milliseconds). Also the SNDR converges to 41.6 dB after averaging 224 samples, while the SNDR with injection of pseudorandom numbers converges to 41.5 dB after 237 samples.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122342942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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