Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841917
P. Pfeifer, Z. Plíva, P. Weckx, B. Kaczer
Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems.
{"title":"On reliability enhancement using adaptive core voltage scaling and variations on nanoscale FPGAs","authors":"P. Pfeifer, Z. Plíva, P. Weckx, B. Kaczer","doi":"10.1109/LATW.2014.6841917","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841917","url":null,"abstract":"Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126188625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841906
J. Behrend, Alexander Grünhage, Douglas Schroeder, D. Lettnin, Jürgen Ruf, T. Kropf, W. Rosenstiel
The verification of embedded software has become an important subject over the last years. However, neither standalone verification approaches, like simulation-based or formal verification, nor state-of-the-art hybrid/semiformal verification approaches are able to verify large and complex embedded software with hardware dependencies. This work presents an optimized scalable hybrid verification approach for the verification of embedded software with hardware dependencies using a mixed bottom-up/top-down algorithm with optimized static parameter assignment (SPA). These algorithms and methodologies like SPA and counterexample guided simulation are used to combine simulation-based and formal verification in a new way. SPA offers a way to interact between dynamic and static verification approaches based on an automated ranking heuristic of possible function parameters according to the impact on the model size. Furthermore, SPA inserts initialization code for specific function parameters into the source code under test and supports model building and optimization algorithms to reduce the state space. We have successfully applied this optimized hybrid verification methodology to an embedded software application: Motorola's Powerstone Benchmark suite. The results show that our approach scales better than stand-alone software model checkers to reach deep state spaces.
{"title":"Optimized hybrid verification of embedded software","authors":"J. Behrend, Alexander Grünhage, Douglas Schroeder, D. Lettnin, Jürgen Ruf, T. Kropf, W. Rosenstiel","doi":"10.1109/LATW.2014.6841906","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841906","url":null,"abstract":"The verification of embedded software has become an important subject over the last years. However, neither standalone verification approaches, like simulation-based or formal verification, nor state-of-the-art hybrid/semiformal verification approaches are able to verify large and complex embedded software with hardware dependencies. This work presents an optimized scalable hybrid verification approach for the verification of embedded software with hardware dependencies using a mixed bottom-up/top-down algorithm with optimized static parameter assignment (SPA). These algorithms and methodologies like SPA and counterexample guided simulation are used to combine simulation-based and formal verification in a new way. SPA offers a way to interact between dynamic and static verification approaches based on an automated ranking heuristic of possible function parameters according to the impact on the model size. Furthermore, SPA inserts initialization code for specific function parameters into the source code under test and supports model building and optimization algorithms to reduce the state space. We have successfully applied this optimized hybrid verification methodology to an embedded software application: Motorola's Powerstone Benchmark suite. The results show that our approach scales better than stand-alone software model checkers to reach deep state spaces.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122650018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841915
S. Bergaoui, P. Vanhauwaert, R. Leveugle
Soft errors with multiple erroneous bits have become a significant threat in embedded systems. New approaches must therefore be proposed to detect errors in a system without assumptions on the error multiplicity. Behavioral checking is in that case appealing. This paper presents a new extended and flexible control flow error detection approach, able to also cover errors in the critical variables of processor-based systems. The approach does not modify the initial system and is compatible with standards such as IEC 61508. Results on a Leon 3-based system are presented.
{"title":"IDSM: An improved disjoint signature monitoring scheme for processor behavioral checking","authors":"S. Bergaoui, P. Vanhauwaert, R. Leveugle","doi":"10.1109/LATW.2014.6841915","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841915","url":null,"abstract":"Soft errors with multiple erroneous bits have become a significant threat in embedded systems. New approaches must therefore be proposed to detect errors in a system without assumptions on the error multiplicity. Behavioral checking is in that case appealing. This paper presents a new extended and flexible control flow error detection approach, able to also cover errors in the critical variables of processor-based systems. The approach does not modify the initial system and is compatible with standards such as IEC 61508. Results on a Leon 3-based system are presented.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"187 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133718800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841905
Carlos Ivan Castro Marquez, M. Strum, J. Wang
Formal techniques provide exhaustive design verification, but computational margins have an important negative impact on its efficiency. Sequential equivalence checking is an effective approach, but traditionally it has been only applied between circuit descriptions with one-to-one correspondence for states. Applying it between RTL descriptions and high-level reference models requires removing signals, variables and states exclusive of the RTL description so as to comply with the state correspondence restriction. In this paper, we extend a previous formal methodology for RTL verification with high-level models, to check also the signals and protocol implemented in the RTL design. This protocol implementation is compared formally to a description captured from the specification. Thus, we can prove thoroughly the sequential behavior of a design under verification.
{"title":"A unified sequential equivalence checking approach to verify high-level functionality and protocol specification implementations in RTL designs","authors":"Carlos Ivan Castro Marquez, M. Strum, J. Wang","doi":"10.1109/LATW.2014.6841905","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841905","url":null,"abstract":"Formal techniques provide exhaustive design verification, but computational margins have an important negative impact on its efficiency. Sequential equivalence checking is an effective approach, but traditionally it has been only applied between circuit descriptions with one-to-one correspondence for states. Applying it between RTL descriptions and high-level reference models requires removing signals, variables and states exclusive of the RTL description so as to comply with the state correspondence restriction. In this paper, we extend a previous formal methodology for RTL verification with high-level models, to check also the signals and protocol implemented in the RTL design. This protocol implementation is compared formally to a description captured from the specification. Thus, we can prove thoroughly the sequential behavior of a design under verification.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"242 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132966660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841898
S. Bendhia, A. Boyer
With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. On-chip characterization of noise becomes necessary for model validation and design optimization to reduce redesign costs and time-to-market for IC manufacturers. This paper presents an on-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level, such as power and signal integrity, substrate coupling, conducted emission and susceptibility to electromagnetic interferences. The different architectures of the sensor are presented as well as a demonstration of its measurement performance and benefits through many case studies. Applications of on-chip measurement may be extended towards online diagnosis and self-healing.
{"title":"Design of on-chip sensors to monitor electromagnetic activity in ICs: Towards on-line diagnosis and self-healing","authors":"S. Bendhia, A. Boyer","doi":"10.1109/LATW.2014.6841898","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841898","url":null,"abstract":"With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. On-chip characterization of noise becomes necessary for model validation and design optimization to reduce redesign costs and time-to-market for IC manufacturers. This paper presents an on-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level, such as power and signal integrity, substrate coupling, conducted emission and susceptibility to electromagnetic interferences. The different architectures of the sensor are presented as well as a demonstration of its measurement performance and benefits through many case studies. Applications of on-chip measurement may be extended towards online diagnosis and self-healing.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133038664","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841924
A. Vaskova, A. Fabregat, M. Portela-García, M. García-Valderas, C. López-Ongil, M. Reorda
Digital electronic systems in automotive applications are in charge of different tasks, ranging from very critical control functions (e.g., airbag, ABS, ESP) to comfort services (e.g., handling of mirrors, seats, windows, wipers). Hardening these systems involves suitably trading off cost and reliability. Due to standards and regulations in the area, the reliability of subsystems involved even in the least critical applications has to be evaluated, and in most cases hardening has to be performed with very low extra cost. In this work, two approaches are proposed for hardening the LIN bus, which implements a serial communication network typically used in low-throughput and low-cost sub-systems in automotive applications. First, critical elements in LIN nodes are identified and some techniques to harden them are proposed following a selective hardening approach. Secondly, collaborative hardening techniques are proposed for reducing global sensitivity in a LIN network built with commercial devices, trying to achieve a high degree of robustness in the network with low cost solutions. We report some experimental results allowing evaluating the hardware cost and the robustness of the proposed techniques.
{"title":"Reducing SEU sensitivity in LIN networks: Selective and collaborative hardening techniques","authors":"A. Vaskova, A. Fabregat, M. Portela-García, M. García-Valderas, C. López-Ongil, M. Reorda","doi":"10.1109/LATW.2014.6841924","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841924","url":null,"abstract":"Digital electronic systems in automotive applications are in charge of different tasks, ranging from very critical control functions (e.g., airbag, ABS, ESP) to comfort services (e.g., handling of mirrors, seats, windows, wipers). Hardening these systems involves suitably trading off cost and reliability. Due to standards and regulations in the area, the reliability of subsystems involved even in the least critical applications has to be evaluated, and in most cases hardening has to be performed with very low extra cost. In this work, two approaches are proposed for hardening the LIN bus, which implements a serial communication network typically used in low-throughput and low-cost sub-systems in automotive applications. First, critical elements in LIN nodes are identified and some techniques to harden them are proposed following a selective hardening approach. Secondly, collaborative hardening techniques are proposed for reducing global sensitivity in a LIN network built with commercial devices, trying to achieve a high degree of robustness in the network with low cost solutions. We report some experimental results allowing evaluating the hardware cost and the robustness of the proposed techniques.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121080627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841918
K. Coulié-Castellani, W. Rahajandraibe, G. Micolau, H. Aziza, J. Portal
A way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a VCO response. In order to improve the correlation between the input current and the oscillator response, a new way of VCO implementation is proposed. The new output parameter variations are analyzed.
{"title":"Improvement of a VCO concept for low energy particule detection and recognition","authors":"K. Coulié-Castellani, W. Rahajandraibe, G. Micolau, H. Aziza, J. Portal","doi":"10.1109/LATW.2014.6841918","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841918","url":null,"abstract":"A way of improvement of an oscillator concept, dedicated to detection and tracking of low energy particles with low fluxes, is presented. The solution is based on an indirect detection of the current generated at the input of the detection chain, through a VCO response. In order to improve the correlation between the input current and the oscillator response, a new way of VCO implementation is proposed. The new output parameter variations are analyzed.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115827094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841900
C. Chenet, A. J. C. Lanot, T. Balen
Due to the technology scaling of modern integrated circuits, the electronic systems are increasingly become more susceptible to transient faults, potentially caused by radiation interaction with the semiconductor. Furthermore the variability of production process, associated to this scaling, and the increase on the operating frequencies, lead to an increase on the probability of faults of complex circuits. This work addresses the concepts of redundancy and diversity with the DTMR technique to improve the fault tolerance of a data acquisition system. A physical implementation is made using a Programmable SoC from Cypress Semiconductor. Results indicate that the system is effective to tolerate single, double and multiple bit-flip faults.
{"title":"Design diversity redundancy with spatial-temporal voting applied to data acquisition systems","authors":"C. Chenet, A. J. C. Lanot, T. Balen","doi":"10.1109/LATW.2014.6841900","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841900","url":null,"abstract":"Due to the technology scaling of modern integrated circuits, the electronic systems are increasingly become more susceptible to transient faults, potentially caused by radiation interaction with the semiconductor. Furthermore the variability of production process, associated to this scaling, and the increase on the operating frequencies, lead to an increase on the probability of faults of complex circuits. This work addresses the concepts of redundancy and diversity with the DTMR technique to improve the fault tolerance of a data acquisition system. A physical implementation is made using a Programmable SoC from Cypress Semiconductor. Results indicate that the system is effective to tolerate single, double and multiple bit-flip faults.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133143356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841911
P. Briff, A. Lutenberg, L. Vega, Fabian Vargas, M. Patwary
In this work we propose a fail-safe control strategy to achieve a target network reliability by estimating the lifetime of nodes in a Wireless Sensor Network (WSN). In the proposed scheme, a network coordinator estimates the outage probability of small-scale uncorrelated fading channel uses and regulates the transmit power of each node in the network in order to simultaneously guarantee the outage probability of each sensor and the overall network availability within predefined limits. The proposed control strategy attains the maximum possible lifetime of the key nodes, and makes readily available a set of results that allows to achieve the proposed targets either by finely tuning the transmit power, the message transmission rate and relevant parameter estimation accuracy, or by reconfiguring the network topology in a timely manner when the key nodes' lifetime falls below a predefined minimum acceptable limit.
{"title":"A novel control strategy for fail-safe cyclic data exchange in wireless sensor networks","authors":"P. Briff, A. Lutenberg, L. Vega, Fabian Vargas, M. Patwary","doi":"10.1109/LATW.2014.6841911","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841911","url":null,"abstract":"In this work we propose a fail-safe control strategy to achieve a target network reliability by estimating the lifetime of nodes in a Wireless Sensor Network (WSN). In the proposed scheme, a network coordinator estimates the outage probability of small-scale uncorrelated fading channel uses and regulates the transmit power of each node in the network in order to simultaneously guarantee the outage probability of each sensor and the overall network availability within predefined limits. The proposed control strategy attains the maximum possible lifetime of the key nodes, and makes readily available a set of results that allows to achieve the proposed targets either by finely tuning the transmit power, the message transmission rate and relevant parameter estimation accuracy, or by reconfiguring the network topology in a timely manner when the key nodes' lifetime falls below a predefined minimum acceptable limit.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132280110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841927
S. Sindia, V. Agrawal
An accepted industry practice for testing of analog and RF circuits is to use specification-based tests. These tests are capable of providing a very low defect level but tend to be long and costly. In this work, we focus on minimizing the specification-based tests without exceeding any given defect level. We use Monte Carlo simulation to determine the probabilities with which a test covers specifications it was not originally intended to cover. These probabilities and the given defect level then define an integer linear programming (ILP) model for eliminating unnecessary tests. This paper gives sufficient evidence of successful implementation of the proposed methodology. A hypothetical example of ten specifications illustrates that depending upon the defect level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications of a commercially available operational amplifier circuit is presented as evidence for the applicability of the technique.
{"title":"Specification test minimization for given defect level","authors":"S. Sindia, V. Agrawal","doi":"10.1109/LATW.2014.6841927","DOIUrl":"https://doi.org/10.1109/LATW.2014.6841927","url":null,"abstract":"An accepted industry practice for testing of analog and RF circuits is to use specification-based tests. These tests are capable of providing a very low defect level but tend to be long and costly. In this work, we focus on minimizing the specification-based tests without exceeding any given defect level. We use Monte Carlo simulation to determine the probabilities with which a test covers specifications it was not originally intended to cover. These probabilities and the given defect level then define an integer linear programming (ILP) model for eliminating unnecessary tests. This paper gives sufficient evidence of successful implementation of the proposed methodology. A hypothetical example of ten specifications illustrates that depending upon the defect level requirement up to half of the tests may be eliminated. Monte Carlo simulation using spice for probabilistic characterization of tests versus specifications of a commercially available operational amplifier circuit is presented as evidence for the applicability of the technique.","PeriodicalId":305922,"journal":{"name":"2014 15th Latin American Test Workshop - LATW","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126246565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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