Pub Date : 2014-03-12DOI: 10.1109/LATW.2014.6841901
Arwa Ben Dhia, M. Slimani, L. Naviner
As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the hardening cost. First, we had to spot, among the switch box multiplexers, the most eligible one to be hardened. Then, we built different possible architectures for the latter by assembling different standard cells from a 65nm industrial library. These architectures were studied under single defect injection by a tool that models several possible defects for a given design according to its extracted netlist. Eventually, the most robust architecture was picked.
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