Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008599
Zehan Cui, Yan Zhu, Yungang Bao, Mingyu Chen
The ever growing energy consumption of computer systems have become a more and more serious problem in the past few years. Power profiling is a fundamental way for us to better understand where, when and how energy is consumed. This paper presents a direct measurement method to measure the power of main computer components with fine time granularity. To achieve this goal, only small amount of extra hardware are employed. An approach to synchronize power dissipation with program phases has also been proposed in this paper. Based on the preliminary version of our tools, we measure the power of CPU, memory and disk when running SPEC CPU2006 benchmarks, and prove that measurement with fine time granularity is essential. The phenomenon we observe from memory power may be served as a guide for memory management or architecture design towards energy efficiency.
{"title":"A fine-grained component-level power measurement method","authors":"Zehan Cui, Yan Zhu, Yungang Bao, Mingyu Chen","doi":"10.1109/IGCC.2011.6008599","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008599","url":null,"abstract":"The ever growing energy consumption of computer systems have become a more and more serious problem in the past few years. Power profiling is a fundamental way for us to better understand where, when and how energy is consumed. This paper presents a direct measurement method to measure the power of main computer components with fine time granularity. To achieve this goal, only small amount of extra hardware are employed. An approach to synchronize power dissipation with program phases has also been proposed in this paper. Based on the preliminary version of our tools, we measure the power of CPU, memory and disk when running SPEC CPU2006 benchmarks, and prove that measurement with fine time granularity is essential. The phenomenon we observe from memory power may be served as a guide for memory management or architecture design towards energy efficiency.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129687921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008553
B. Rountree, D. Lowenthal, M. Schulz, B. Supinski
Predicting performance under Dynamic Voltage Frequency Scaling (DVFS) remains an open problem. Current best practice explores available performance counters to serve as input to linear regression models that predict performance. However, the inaccuracies of these models require that large-scale DVFS runtime algorithms predict performance conservatively in order to avoid significant consequences of mispredictions. Recent theoretical work based on interval analysis advocates a more accurate and reliable solution based on a single new performance counter, Leading Loads. In this paper, we evaluate a processor-independent analytic framework for existing performance counters based on this interval analysis model. We begin with an analysis of the counters used in many published models. We then briefly describe the Leading Loads architectural model and describe how we can use Leading Loads Cycles to predict performance under DVFS. We validate this approach for the NAS Parallel Benchmarks and SPEC CPU 2006 benchmarks, demonstrating an order of magnitude improvement in both error and standard deviation compared to the best existing approaches.
动态电压频率标度(DVFS)下的性能预测仍然是一个有待解决的问题。当前的最佳实践探索可用的性能计数器，作为预测性能的线性回归模型的输入。然而，这些模型的不准确性要求大规模DVFS运行时算法保守地预测性能，以避免错误预测的严重后果。最近基于区间分析的理论工作提倡一种更准确和可靠的解决方案，该解决方案基于一个新的性能计数器，Leading Loads。在本文中，我们基于这个区间分析模型，评估了一个与处理器无关的现有性能计数器分析框架。我们首先分析许多已发布模型中使用的计数器。然后，我们简要地描述了超前负载架构模型，并描述了如何使用超前负载周期来预测DVFS下的性能。我们在NAS并行基准测试和SPEC CPU 2006基准测试中验证了这种方法，与现有的最佳方法相比，在误差和标准偏差方面都有了数量级的改进。
{"title":"Practical performance prediction under Dynamic Voltage Frequency Scaling","authors":"B. Rountree, D. Lowenthal, M. Schulz, B. Supinski","doi":"10.1109/IGCC.2011.6008553","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008553","url":null,"abstract":"Predicting performance under Dynamic Voltage Frequency Scaling (DVFS) remains an open problem. Current best practice explores available performance counters to serve as input to linear regression models that predict performance. However, the inaccuracies of these models require that large-scale DVFS runtime algorithms predict performance conservatively in order to avoid significant consequences of mispredictions. Recent theoretical work based on interval analysis advocates a more accurate and reliable solution based on a single new performance counter, Leading Loads. In this paper, we evaluate a processor-independent analytic framework for existing performance counters based on this interval analysis model. We begin with an analysis of the counters used in many published models. We then briefly describe the Leading Loads architectural model and describe how we can use Leading Loads Cycles to predict performance under DVFS. We validate this approach for the NAS Parallel Benchmarks and SPEC CPU 2006 benchmarks, demonstrating an order of magnitude improvement in both error and standard deviation compared to the best existing approaches.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115015768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008550
Ryan Jansen, P. Brenner
Reducing energy consumption is a critical step in lowering data center operating costs for various institutions. As such, with the growing popularity of cloud computing, it is necessary to examine various methods by which energy consumption in cloud environments can be reduced. We analyze the effects of virtual machine allocation on energy consumption, using a variety of real-world policies and a realistic testing scenario. We found that by using an allocation policy designed to minimize energy, total energy consumption could be reduced by up to 14%, and total monetary energy costs could be reduced by up to 26%.
{"title":"Energy efficient virtual machine allocation in the cloud","authors":"Ryan Jansen, P. Brenner","doi":"10.1109/IGCC.2011.6008550","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008550","url":null,"abstract":"Reducing energy consumption is a critical step in lowering data center operating costs for various institutions. As such, with the growing popularity of cloud computing, it is necessary to examine various methods by which energy consumption in cloud environments can be reduced. We analyze the effects of virtual machine allocation on energy consumption, using a variety of real-world policies and a realistic testing scenario. We found that by using an allocation policy designed to minimize energy, total energy consumption could be reduced by up to 14%, and total monetary energy costs could be reduced by up to 26%.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123614020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008552
Vasileios Spiliopoulos, S. Kaxiras, G. Keramidas
We present Continuously Adaptive Dynamic Voltage/Frequency scaling in Linux systems running on Intel i7 and AMD Phenom II processors. By exploiting slack, inherent in memory-bound programs, our approach aims to improve power efficiency even when the processor does not sit idle. Our underlying methodology is based on a simple first-order processor performance model in which frequency scaling is expressed as a change (in cycles) of the main memory latency. Utilizing available monitoring hardware we show that our model is powerful enough to i) predict with reasonable accuracy the effect of frequency scaling (in terms of performance loss) and ii) predict the core energy under different V/f combinations. To validate our approach we perform highly accurate, fine-grained power measurements directly on the off-chip voltage regulators. We use our model to implement various DVFS policies as Linux “green” governors to continuously optimize for various power-efficiency metrics such as EDP or ED2P, or achieve energy savings with a user-specified limit on performance loss. Our evaluation shows that, for SPEC2006 workloads, our governors achieve dynamically the same optimal EDP or ED2P (within 2% on avg.) as an exhaustive search of all possible frequencies. Energy savings can reach up to 56% in memory-bound workloads with corresponding improvements of about 55% for EDP or ED2P.
{"title":"Green governors: A framework for Continuously Adaptive DVFS","authors":"Vasileios Spiliopoulos, S. Kaxiras, G. Keramidas","doi":"10.1109/IGCC.2011.6008552","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008552","url":null,"abstract":"We present Continuously Adaptive Dynamic Voltage/Frequency scaling in Linux systems running on Intel i7 and AMD Phenom II processors. By exploiting slack, inherent in memory-bound programs, our approach aims to improve power efficiency even when the processor does not sit idle. Our underlying methodology is based on a simple first-order processor performance model in which frequency scaling is expressed as a change (in cycles) of the main memory latency. Utilizing available monitoring hardware we show that our model is powerful enough to i) predict with reasonable accuracy the effect of frequency scaling (in terms of performance loss) and ii) predict the core energy under different V/f combinations. To validate our approach we perform highly accurate, fine-grained power measurements directly on the off-chip voltage regulators. We use our model to implement various DVFS policies as Linux “green” governors to continuously optimize for various power-efficiency metrics such as EDP or ED2P, or achieve energy savings with a user-specified limit on performance loss. Our evaluation shows that, for SPEC2006 workloads, our governors achieve dynamically the same optimal EDP or ED2P (within 2% on avg.) as an exhaustive search of all possible frequencies. Energy savings can reach up to 56% in memory-bound workloads with corresponding improvements of about 55% for EDP or ED2P.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"84 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128458485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008564
Thomas Wirtz, Rong Ge
MapReduce is a programming model for data intensive computing on large-scale distributed systems. With its wide acceptance and deployment, improving the energy efficiency of MapReduce will lead to significant energy savings for data centers and computational grids. In this paper, we study the performance and energy efficiency of the Hadoop implementation of MapReduce under the context of energy-proportional computing. We consider how MapReduce efficiency varies with two runtime configurations: resource allocation that changes the number of available concurrent workers, and DVFS (Dynamic Voltage and Frequency Scaling) that adjusts the processor frequency based on the workloads' computational needs. Our experimental results indicate significant energy savings can be achieved from judicious resource allocation and intelligent DVFS scheduling for computation intensive applications, though the level of improvements depends on both workload characteristic of the MapReduce application and the policy of resource and DVFS scheduling.
{"title":"Improving MapReduce energy efficiency for computation intensive workloads","authors":"Thomas Wirtz, Rong Ge","doi":"10.1109/IGCC.2011.6008564","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008564","url":null,"abstract":"MapReduce is a programming model for data intensive computing on large-scale distributed systems. With its wide acceptance and deployment, improving the energy efficiency of MapReduce will lead to significant energy savings for data centers and computational grids. In this paper, we study the performance and energy efficiency of the Hadoop implementation of MapReduce under the context of energy-proportional computing. We consider how MapReduce efficiency varies with two runtime configurations: resource allocation that changes the number of available concurrent workers, and DVFS (Dynamic Voltage and Frequency Scaling) that adjusts the processor frequency based on the workloads' computational needs. Our experimental results indicate significant energy savings can be achieved from judicious resource allocation and intelligent DVFS scheduling for computation intensive applications, though the level of improvements depends on both workload characteristic of the MapReduce application and the policy of resource and DVFS scheduling.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124067565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008567
L. Costa, S. Al-Kiswany, R. Lopes, M. Ripeanu
The energy costs of running computer systems are a growing concern: for large data centers, recent estimates put these costs higher than the cost of hardware itself. As a consequence, energy efficiency has become a pervasive theme for designing, deploying, and operating computer systems. This paper evaluates the energy trade-offs brought by data deduplication in distributed storage systems. Depending on the workload, deduplication can enable a lower storage footprint, reduce the I/O pressure on the storage system, and reduce network traffic, at the cost of increased computational overhead. From an energy perspective, data deduplication enables a trade-off between the energy consumed for additional computation and the energy saved by lower storage and network load. The main point our experiments and model bring home is the following: while for non energy-proportional machines performance- and energy-centric optimizations have break-even points that are relatively close, for the newer generation of energy proportional machines the break-even points are significantly different. An important consequence of this difference is that, with newer systems, there are higher energy inefficiencies when the system is optimized for performance.
{"title":"Assessing data deduplication trade-offs from an energy and performance perspective","authors":"L. Costa, S. Al-Kiswany, R. Lopes, M. Ripeanu","doi":"10.1109/IGCC.2011.6008567","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008567","url":null,"abstract":"The energy costs of running computer systems are a growing concern: for large data centers, recent estimates put these costs higher than the cost of hardware itself. As a consequence, energy efficiency has become a pervasive theme for designing, deploying, and operating computer systems. This paper evaluates the energy trade-offs brought by data deduplication in distributed storage systems. Depending on the workload, deduplication can enable a lower storage footprint, reduce the I/O pressure on the storage system, and reduce network traffic, at the cost of increased computational overhead. From an energy perspective, data deduplication enables a trade-off between the energy consumed for additional computation and the energy saved by lower storage and network load. The main point our experiments and model bring home is the following: while for non energy-proportional machines performance- and energy-centric optimizations have break-even points that are relatively close, for the newer generation of energy proportional machines the break-even points are significantly different. An important consequence of this difference is that, with newer systems, there are higher energy inefficiencies when the system is optimized for performance.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"4609 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130794500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008554
Hafiz Fahad Sheikh, I. Ahmad
Thermal management is highly crucial for efficient exploitation of the potentially enormous computational power offered by advanced multi-core processors. Higher temperatures can adversely affect these processors. Without any thermal constraint, a task graph may be scheduled to run on the cores at their maximum voltage. Very often, multiple factors lead to imposing constraints on temperature, ensuring that cores remain below a certain temperature range and yet deliver good performance. The challenge is how to schedule the same task graph under the imposed thermal constraints such that the performance degradation is the minimum. In this paper we present two algorithms for minimizing the performance degradation and the corresponding overhead while satisfying the thermal constraints. The proposed algorithms, named PAVD, and TAVD, adjust a given schedule of a task graph by decreasing the voltage level of judiciously selected tasks in each step. The algorithms differ in the way they select a task at each step and the amount of time spent in searching that task. TAVD selects the tasks by prioritizing among the cores and tasks which attained maximum temperature while PAVD selects the tasks with the minimum performance penalty. For comparison, we develop a simpler greedy-based approach to show that the problem is non-trivial. Extensive experiments using both random and application-oriented task graphs demonstrate that all three algorithms satisfy the imposed thermal constraints by trading-off performance, while each showing its own strength.
{"title":"Fast algorithms for thermal constrained performance optimization in DAG scheduling on multi-core processors","authors":"Hafiz Fahad Sheikh, I. Ahmad","doi":"10.1109/IGCC.2011.6008554","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008554","url":null,"abstract":"Thermal management is highly crucial for efficient exploitation of the potentially enormous computational power offered by advanced multi-core processors. Higher temperatures can adversely affect these processors. Without any thermal constraint, a task graph may be scheduled to run on the cores at their maximum voltage. Very often, multiple factors lead to imposing constraints on temperature, ensuring that cores remain below a certain temperature range and yet deliver good performance. The challenge is how to schedule the same task graph under the imposed thermal constraints such that the performance degradation is the minimum. In this paper we present two algorithms for minimizing the performance degradation and the corresponding overhead while satisfying the thermal constraints. The proposed algorithms, named PAVD, and TAVD, adjust a given schedule of a task graph by decreasing the voltage level of judiciously selected tasks in each step. The algorithms differ in the way they select a task at each step and the amount of time spent in searching that task. TAVD selects the tasks by prioritizing among the cores and tasks which attained maximum temperature while PAVD selects the tasks with the minimum performance penalty. For comparison, we develop a simpler greedy-based approach to show that the problem is non-trivial. Extensive experiments using both random and application-oriented task graphs demonstrate that all three algorithms satisfy the imposed thermal constraints by trading-off performance, while each showing its own strength.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126944574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008598
Hui Chen, Shinan Wang, Weisong Shi
In the last few years the power dissipation problem of computer systems has attracted more and more attention. A lot of work has been done to decrease power dissipation and increase energy efficiency. We are still, however, not observing significant decrease of power dissipation. On the contrary, modern computer systems consume ever increasing amounts of energy. Where does the power go in a computer system is a question that many people are concerned with. Through comprehensive experiments and measurements, we observe several phenomenons that are in opposition to our common sense. Many people believe, for instance, that CPU utilization is a good indicator of the power dissipation of CPU. Our experiment results, however, show that CPU utilization is not an accurate reflection of the CPU power. Moreover, we discover that despite the performance improvements it introduces, cache could be a big problem for power reducing. Based on our observations we derive ten implications that are important for energy efficient system design.
{"title":"Where does the power go in a computer system: Experimental analysis and implications","authors":"Hui Chen, Shinan Wang, Weisong Shi","doi":"10.1109/IGCC.2011.6008598","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008598","url":null,"abstract":"In the last few years the power dissipation problem of computer systems has attracted more and more attention. A lot of work has been done to decrease power dissipation and increase energy efficiency. We are still, however, not observing significant decrease of power dissipation. On the contrary, modern computer systems consume ever increasing amounts of energy. Where does the power go in a computer system is a question that many people are concerned with. Through comprehensive experiments and measurements, we observe several phenomenons that are in opposition to our common sense. Many people believe, for instance, that CPU utilization is a good indicator of the power dissipation of CPU. Our experiment results, however, show that CPU utilization is not an accurate reflection of the CPU power. Moreover, we discover that despite the performance improvements it introduces, cache could be a big problem for power reducing. Based on our observations we derive ten implications that are important for energy efficient system design.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126746000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008601
D. Sengupta, A. Veneris, S. Wilton, A. Ivanov, R. Saleh
In the nanometer era of VLSI design, high power consumption is considered to be a “show-stopper” for many applications. Voltage Island design has emerged as a popular method for addressing this issue. This technique requires multiple supply voltages on the same chip with blocks assigned to different supply voltages. Implementation challenges force blocks with similar supply voltages to be placed contiguous to one another, thereby creating “islands”. Classical floorplanners assume a single supply voltage in the entire SoC and thus require additional design steps to realize voltage islands. In this paper we present a new floorplanning algorithm based on the sequence pair representation that can floorplan blocks in the form of islands. Given the possible supply voltage choices for each block, the floorplanner simultaneously attempts to reduce power and area of the chip. Our floorplanner integrates the tasks of assigning blocks to different supply voltages and the placing of the blocks in the chip. Compared to previous work, the proposed floorplanner on average reduces the area overhead of the chip by 13.5% with 34% runtime improvement. Additionally we explore the tradeoff between power and area for different floorplan solutions.
{"title":"Sequence pair based voltage island floorplanning","authors":"D. Sengupta, A. Veneris, S. Wilton, A. Ivanov, R. Saleh","doi":"10.1109/IGCC.2011.6008601","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008601","url":null,"abstract":"In the nanometer era of VLSI design, high power consumption is considered to be a “show-stopper” for many applications. Voltage Island design has emerged as a popular method for addressing this issue. This technique requires multiple supply voltages on the same chip with blocks assigned to different supply voltages. Implementation challenges force blocks with similar supply voltages to be placed contiguous to one another, thereby creating “islands”. Classical floorplanners assume a single supply voltage in the entire SoC and thus require additional design steps to realize voltage islands. In this paper we present a new floorplanning algorithm based on the sequence pair representation that can floorplan blocks in the form of islands. Given the possible supply voltage choices for each block, the floorplanner simultaneously attempts to reduce power and area of the chip. Our floorplanner integrates the tasks of assigning blocks to different supply voltages and the placing of the blocks in the chip. Compared to previous work, the proposed floorplanner on average reduces the area overhead of the chip by 13.5% with 34% runtime improvement. Additionally we explore the tradeoff between power and area for different floorplan solutions.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"37 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132972942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008595
Jun Lu, Qinru Qiu
In this paper we propose a low-complexity and effective task mapping, scheduling and power management method for multi-core real-time embedded systems with energy harvesting. The proposed method is based on the concept of task CPU utilization, which is defined as the worst-case task execution time divided by its period. This work mathematically proves that by allocating the new task to the core with the lowest utilization, we can achieve the lowest overall energy dissipation. This method, combined with a new dynamic voltage and frequency selection (DVFS) algorithm with energy harvesting awareness and task slack management (TSM) forms the proposed UTilization Based (UTB) algorithm. With periodical tasks in a multi-core platform, this partitioned scheduling method is optimal for energy dissipation if the proposed utilization-based scheduling and DVFS algorithm is applied on each core. Experimental results show that new algorithm achieves better performance in terms of deadline miss rate in a single-core environment, comparing to the best of existing algorithm. When applied on a multi-core platform, the UTB algorithm achieves better efficiency in utilizing the harvested energy and overflowed energy.
{"title":"Scheduling and mapping of periodic tasks on multi-core embedded systems with energy harvesting","authors":"Jun Lu, Qinru Qiu","doi":"10.1109/IGCC.2011.6008595","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008595","url":null,"abstract":"In this paper we propose a low-complexity and effective task mapping, scheduling and power management method for multi-core real-time embedded systems with energy harvesting. The proposed method is based on the concept of task CPU utilization, which is defined as the worst-case task execution time divided by its period. This work mathematically proves that by allocating the new task to the core with the lowest utilization, we can achieve the lowest overall energy dissipation. This method, combined with a new dynamic voltage and frequency selection (DVFS) algorithm with energy harvesting awareness and task slack management (TSM) forms the proposed UTilization Based (UTB) algorithm. With periodical tasks in a multi-core platform, this partitioned scheduling method is optimal for energy dissipation if the proposed utilization-based scheduling and DVFS algorithm is applied on each core. Experimental results show that new algorithm achieves better performance in terms of deadline miss rate in a single-core environment, comparing to the best of existing algorithm. When applied on a multi-core platform, the UTB algorithm achieves better efficiency in utilizing the harvested energy and overflowed energy.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134464967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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