Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008574
Ming-yu Hsieh
It has become increasingly challenging to understand supercomputers behavior and performance as they grow. New hurdles in scalability, programmability, power consumption, reliability, cost, and cooling are emerging. This paper introduces the integrated power, area, temperature, reliability modeling framework in the open, modular, multiscale, parallel Structural Simulation Toolkit (SST) to help evaluate new technologies and guide design of future computers. In this study, the simulation framework is used to evaluate different dynamic thermal management techniques, in terms of power, temperature and reliability, on multicore systems running multithreaded and more irregular applications. Simulation results shed some new light on application-aware, performance/power efficient thermal and reliability management policies of multithreaded multicore systems.
{"title":"A scalable simulation framework for evaluating thermal management techniques and the lifetime reliability of multithreaded multicore systems","authors":"Ming-yu Hsieh","doi":"10.1109/IGCC.2011.6008574","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008574","url":null,"abstract":"It has become increasingly challenging to understand supercomputers behavior and performance as they grow. New hurdles in scalability, programmability, power consumption, reliability, cost, and cooling are emerging. This paper introduces the integrated power, area, temperature, reliability modeling framework in the open, modular, multiscale, parallel Structural Simulation Toolkit (SST) to help evaluate new technologies and guide design of future computers. In this study, the simulation framework is used to evaluate different dynamic thermal management techniques, in terms of power, temperature and reliability, on multicore systems running multithreaded and more irregular applications. Simulation results shed some new light on application-aware, performance/power efficient thermal and reliability management policies of multithreaded multicore systems.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132181574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008562
Yifeng Guo, Dakai Zhu, Hakan Aydin
The negative effects of the Dynamic Voltage and Frequency Scaling (DVFS) technique on the system reliability has recently promoted the research on reliability-aware power management (RAPM). RAPM aims at reducing the system energy consumption while preserving the system's reliability. In this paper, we study the RAPM problem for parallel realtime applications for shared memory multiprocessor systems in the presence of precedence constraints. We show that this problem is NP-hard. Depending on how recoveries are scheduled and utilized by a subset of selected tasks, we investigate both individual-recovery and shared-recovery based RAPM heuristics. Online RAPM schemes that exploit dynamic slack generated at runtime are also considered. The proposed schemes are evaluated through extensive simulations. The results show that all schemes can preserve system reliability under all settings. For modest system loads, similar energy savings are obtained by all static schemes. However, when the system load is low, the shared-recovery based schemes need coordinated recovery operations on all processors and thus save less energy. Moreover, by reclaiming dynamic slack, the online schemes yield better energy savings.
{"title":"Reliability-aware power management for parallel real-time applications with precedence constraints","authors":"Yifeng Guo, Dakai Zhu, Hakan Aydin","doi":"10.1109/IGCC.2011.6008562","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008562","url":null,"abstract":"The negative effects of the Dynamic Voltage and Frequency Scaling (DVFS) technique on the system reliability has recently promoted the research on reliability-aware power management (RAPM). RAPM aims at reducing the system energy consumption while preserving the system's reliability. In this paper, we study the RAPM problem for parallel realtime applications for shared memory multiprocessor systems in the presence of precedence constraints. We show that this problem is NP-hard. Depending on how recoveries are scheduled and utilized by a subset of selected tasks, we investigate both individual-recovery and shared-recovery based RAPM heuristics. Online RAPM schemes that exploit dynamic slack generated at runtime are also considered. The proposed schemes are evaluated through extensive simulations. The results show that all schemes can preserve system reliability under all settings. For modest system loads, similar energy savings are obtained by all static schemes. However, when the system load is low, the shared-recovery based schemes need coordinated recovery operations on all processors and thus save less energy. Moreover, by reclaiming dynamic slack, the online schemes yield better energy savings.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126778701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008570
X. Mountrouidou, Alma Riska, E. Smirni
We present a robust framework that aims at harvesting future idle intervals for power savings within strict constraints: first, it is imperative to contain the delays in service of IO requests that occur during power savings since the time to bring up the disk is not negligible and second, ensure that the power saving mechanism is triggered few times only, such that the disk wear out due to powering up and down does not compromise its lifetime. Extensive experimentation on a set of enterprise storage traces illustrates frameworks effectiveness.
{"title":"Saving power without compromising disk drive reliability","authors":"X. Mountrouidou, Alma Riska, E. Smirni","doi":"10.1109/IGCC.2011.6008570","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008570","url":null,"abstract":"We present a robust framework that aims at harvesting future idle intervals for power savings within strict constraints: first, it is imperative to contain the delays in service of IO requests that occur during power savings since the time to bring up the disk is not negligible and second, ensure that the power saving mechanism is triggered few times only, such that the disk wear out due to powering up and down does not compromise its lifetime. Extensive experimentation on a set of enterprise storage traces illustrates frameworks effectiveness.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008602
Shen Li, T. Abdelzaher, Mindi Yuan
In this paper, we analytically derive, implement, and empirically evaluate a solution for maximizing the execution rate of Map-Reduce jobs subject to power constraints in data centers. Our solution is novel in that it takes into account the dependence of power consumption on temperature, attributed to temperature-induced changes in leakage current and fan speed. While this dependence is well-known, we are the first to consider it in the context of maximizing the throughput of Map-Reduce workdloads. Accordingly, we provide a new power model and optimization strategy for temperature-aware power allocation (TAPA), and modify Hadoop on a 13-machine cluster to implement our optimization algorithm. Our experimental results show that TAPA can not only limit the power consumption to the power budget but also achieves higher computational efficiency against static solutions and temperature oblivious DVFS solutions.
{"title":"TAPA: Temperature aware power allocation in data center with Map-Reduce","authors":"Shen Li, T. Abdelzaher, Mindi Yuan","doi":"10.1109/IGCC.2011.6008602","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008602","url":null,"abstract":"In this paper, we analytically derive, implement, and empirically evaluate a solution for maximizing the execution rate of Map-Reduce jobs subject to power constraints in data centers. Our solution is novel in that it takes into account the dependence of power consumption on temperature, attributed to temperature-induced changes in leakage current and fan speed. While this dependence is well-known, we are the first to consider it in the context of maximizing the throughput of Map-Reduce workdloads. Accordingly, we provide a new power model and optimization strategy for temperature-aware power allocation (TAPA), and modify Hadoop on a 13-machine cluster to implement our optimization algorithm. Our experimental results show that TAPA can not only limit the power consumption to the power budget but also achieves higher computational efficiency against static solutions and temperature oblivious DVFS solutions.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133345746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008604
Joseph Crop, R. Pawlowski, N. M. Madani, J. Jackson, P. Chiang
Ultra-low power digital circuit design using sub-threshold supply voltages has recently been popularized for energy-constrained systems, sensor networks and bio-sensor applications. The conventional method to improve digital circuit operation in the sub-threshold region is to design every logic cell manually, requiring complete re-design and re-characterization for every process node. This proposed work introduces a computational design automation that tests every cell in a standard cell library for proper operation in the sub-threshold region, eliminating cells that perform poorly. The result of this culling process is improved sub-/near-threshold operation for any standard cell library, improving delay, area, and energy. Monte-Carlo simulation results of a synthesized 90nm-CMOS Floating-Point Adder verifies improved mean timing delay (32%) and overall energy per computation (37%) of the culled standard cell library design over a regular synthesized design.
{"title":"Design automation methodology for improving the variability of synthesized digital circuits operating in the sub/near-threshold regime","authors":"Joseph Crop, R. Pawlowski, N. M. Madani, J. Jackson, P. Chiang","doi":"10.1109/IGCC.2011.6008604","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008604","url":null,"abstract":"Ultra-low power digital circuit design using sub-threshold supply voltages has recently been popularized for energy-constrained systems, sensor networks and bio-sensor applications. The conventional method to improve digital circuit operation in the sub-threshold region is to design every logic cell manually, requiring complete re-design and re-characterization for every process node. This proposed work introduces a computational design automation that tests every cell in a standard cell library for proper operation in the sub-threshold region, eliminating cells that perform poorly. The result of this culling process is improved sub-/near-threshold operation for any standard cell library, improving delay, area, and energy. Monte-Carlo simulation results of a synthesized 90nm-CMOS Floating-Point Adder verifies improved mean timing delay (32%) and overall energy per computation (37%) of the culled standard cell library design over a regular synthesized design.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117310401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008575
Md. Ashfaquzzaman Khan, Can Hankendi, A. Coskun, M. Herbordt
As an initial step in our Green Software research, this paper investigates whether software optimization at the application level can help achieve higher energy efficiency and better thermal behavior. We use both direct measurements and modeling to quantify power, energy and temperature for a given software method. The infrastructure includes a new power estimator for multicore systems developed by regressing measurements from a custom-designed suite of microbenchmarks. Using our evaluation methodology on a real-life multicore system, we explore two case studies. In the first one, we use software tuning for improving the scalability and energy-efficiency of a parallel application. The second case study explores the effect of temperature optimization on system-level energy consumption.
{"title":"Software optimization for performance, energy, and thermal distribution: Initial case studies","authors":"Md. Ashfaquzzaman Khan, Can Hankendi, A. Coskun, M. Herbordt","doi":"10.1109/IGCC.2011.6008575","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008575","url":null,"abstract":"As an initial step in our Green Software research, this paper investigates whether software optimization at the application level can help achieve higher energy efficiency and better thermal behavior. We use both direct measurements and modeling to quantify power, energy and temperature for a given software method. The infrastructure includes a new power estimator for multicore systems developed by regressing measurements from a custom-designed suite of microbenchmarks. Using our evaluation methodology on a real-life multicore system, we explore two case studies. In the first one, we use software tuning for improving the scalability and energy-efficiency of a parallel application. The second case study explores the effect of temperature optimization on system-level energy consumption.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121905222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008608
Wei Zhao, M. Tehranipoor
Peak power during test can seriously impact circuit performance as well as the power safety for both CUT and tester. In this paper, we propose a method of layout-aware weighted switching activity identification flow that evaluates peak current/power on power bumps to detect high power patterns. The dynamic power model uses load capacitance as a metric to represent its value. Parasitic capacitance is also extracted from layout and taken into account in calculating power. Resistance network is considered regarding power bus to determine the power delivery path and power level on each specific power bump. The peak power identification flow can be integrated in gate level pattern simulation that the IR-drop results have good correlation with commercial power sign-off analysis tool.
{"title":"Peak power identification on power bumps during test application","authors":"Wei Zhao, M. Tehranipoor","doi":"10.1109/IGCC.2011.6008608","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008608","url":null,"abstract":"Peak power during test can seriously impact circuit performance as well as the power safety for both CUT and tester. In this paper, we propose a method of layout-aware weighted switching activity identification flow that evaluates peak current/power on power bumps to detect high power patterns. The dynamic power model uses load capacitance as a metric to represent its value. Parasitic capacitance is also extracted from layout and taken into account in calculating power. Resistance network is considered regarding power bus to determine the power delivery path and power level on each specific power bump. The peak power identification flow can be integrated in gate level pattern simulation that the IR-drop results have good correlation with commercial power sign-off analysis tool.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125314692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008591
Ran Duan, Mingsong Bi, C. Gniady
Recent development of sophisticated smartphones has made them indispensable part of our everyday life. However, advances in battery technology cannot keep up with the demand for longer battery life. Subsequently, energy efficiency has become one of the most important factors in designing smartphones. Multitasking and better multimedia features in the mobile applications continuously push memory requirements further, making energy optimizations for memory critical. Mobile RAM is already optimized for energy efficiency at the hardware level. It also provides power state switching interfaces to the operating system which enables the OS level energy optimizations. Many RAM optimizations have been explored for computer systems and in this paper we explore their applicability to smartphone hardware. In addition, we apply those optimizations to the newly emerging Phase Change Memory and study their energy efficiency and performance. Finally, we propose a hybrid approach to take the advantage of both Mobile RAM and Phase Change Memory. Results show that our hybrid mechanism can save more than 98% of memory energy as compared to the standard smartphone system with negligible impact on user experience.
{"title":"Exploring memory energy optimizations in smartphones","authors":"Ran Duan, Mingsong Bi, C. Gniady","doi":"10.1109/IGCC.2011.6008591","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008591","url":null,"abstract":"Recent development of sophisticated smartphones has made them indispensable part of our everyday life. However, advances in battery technology cannot keep up with the demand for longer battery life. Subsequently, energy efficiency has become one of the most important factors in designing smartphones. Multitasking and better multimedia features in the mobile applications continuously push memory requirements further, making energy optimizations for memory critical. Mobile RAM is already optimized for energy efficiency at the hardware level. It also provides power state switching interfaces to the operating system which enables the OS level energy optimizations. Many RAM optimizations have been explored for computer systems and in this paper we explore their applicability to smartphone hardware. In addition, we apply those optimizations to the newly emerging Phase Change Memory and study their energy efficiency and performance. Finally, we propose a hybrid approach to take the advantage of both Mobile RAM and Phase Change Memory. Results show that our hybrid mechanism can save more than 98% of memory energy as compared to the standard smartphone system with negligible impact on user experience.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125421853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008585
Xinghui Zhao, Nadeem Jamali
There is growing interest in the energy consumed by computer systems, for both individual (battery life) and environmental (global warming) reasons. Multicore architectures offer a potential opportunity for energy conservation by allowing cores to operate at lower frequencies. Previous work on analyzing power consumption of multicores assumes that all cores must run at the same frequency. However, new technologies, such as fast voltage scaling and Turbo Boost, allow cores to operate at different frequencies. In this paper, we present an energy-aware resource management model, ROT-MCP, which provides a flexible way to analyze energy consumption of multicores operating at non-uniform frequencies. This information can then be used to generate a energy-efficient schedule for execution of the computations - as well as a schedule of frequency changes on a per-core basis - while satisfying performance requirements of computations. Experimental results show that the energy savings achieved using this approach far outweigh the energy consumed in the reasoning required for generating the schedules.
{"title":"Fine-grained per-core frequency scheduling for power efficient-multicore execution","authors":"Xinghui Zhao, Nadeem Jamali","doi":"10.1109/IGCC.2011.6008585","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008585","url":null,"abstract":"There is growing interest in the energy consumed by computer systems, for both individual (battery life) and environmental (global warming) reasons. Multicore architectures offer a potential opportunity for energy conservation by allowing cores to operate at lower frequencies. Previous work on analyzing power consumption of multicores assumes that all cores must run at the same frequency. However, new technologies, such as fast voltage scaling and Turbo Boost, allow cores to operate at different frequencies. In this paper, we present an energy-aware resource management model, ROT-MCP, which provides a flexible way to analyze energy consumption of multicores operating at non-uniform frequencies. This information can then be used to generate a energy-efficient schedule for execution of the computations - as well as a schedule of frequency changes on a per-core basis - while satisfying performance requirements of computations. Experimental results show that the energy savings achieved using this approach far outweigh the energy consumed in the reasoning required for generating the schedules.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122340846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008605
V. Bhagavatula, W. Wesson, J. Rudell
Enabling long-range, small form-factor transceivers can address a number of green and environmental monitoring applications. This paper explores an alternative method for sensor data communication using long-range wireless transceivers to communicate sensor data. A Wide Area Radio Network for Sensor (WARNS) communication which allows direct communication of a sensor mote to a base-station several kilometers away is proposed along with a discussion on the associated hardware challenges. A study is also provided for one of the most challenging hardware blocks in a WARNS radio, the Power Amplifier (PA).
{"title":"Green monitoring using a Wide Area Radio Network for Sensor (WARNS) communication","authors":"V. Bhagavatula, W. Wesson, J. Rudell","doi":"10.1109/IGCC.2011.6008605","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008605","url":null,"abstract":"Enabling long-range, small form-factor transceivers can address a number of green and environmental monitoring applications. This paper explores an alternative method for sensor data communication using long-range wireless transceivers to communicate sensor data. A Wide Area Radio Network for Sensor (WARNS) communication which allows direct communication of a sensor mote to a base-station several kilometers away is proposed along with a discussion on the associated hardware challenges. A study is also provided for one of the most challenging hardware blocks in a WARNS radio, the Power Amplifier (PA).","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127861165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：