Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008582
Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, J. Peir
Graphics Processing Units (GPUs) have emerged as a promising platform for parallel computation. With a large number of scalar processors and abundant memory bandwidth, GPUs provide substantial computation power. While delivering high computation performance, the GPU also consumes high power and needs to be equipped with sufficient power supplies and cooling systems. Therefore, it is essential to institute an efficient mechanism for evaluating and understanding the power consumption requirement when running real applications on high-end GPUs. In this paper, we present a high-level GPU power consumption model using sophisticated tree-based random forest methods which can correlate the power consumption with a set of independent performance variables. This statistical model not only predicts the GPU runtime power consumption accurately, but more importantly, it also provides sufficient insights for understanding the dependence between the GPU runtime power consumption and the individual performance metrics. In order to gain more insights, we use a GPU simulator that can collect more runtime performance metrics than hardware counters. We measure the power consumption of a wide-range of CUDA kernels on an experimental system with GTX 280 GPU as statistical samples for our power analysis. This methodology can certainly be applied to any other CUDA GPU.
{"title":"Statistical GPU power analysis using tree-based methods","authors":"Jianmin Chen, Bin Li, Ying Zhang, Lu Peng, J. Peir","doi":"10.1109/IGCC.2011.6008582","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008582","url":null,"abstract":"Graphics Processing Units (GPUs) have emerged as a promising platform for parallel computation. With a large number of scalar processors and abundant memory bandwidth, GPUs provide substantial computation power. While delivering high computation performance, the GPU also consumes high power and needs to be equipped with sufficient power supplies and cooling systems. Therefore, it is essential to institute an efficient mechanism for evaluating and understanding the power consumption requirement when running real applications on high-end GPUs. In this paper, we present a high-level GPU power consumption model using sophisticated tree-based random forest methods which can correlate the power consumption with a set of independent performance variables. This statistical model not only predicts the GPU runtime power consumption accurately, but more importantly, it also provides sufficient insights for understanding the dependence between the GPU runtime power consumption and the individual performance metrics. In order to gain more insights, we use a GPU simulator that can collect more runtime performance metrics than hardware counters. We measure the power consumption of a wide-range of CUDA kernels on an experimental system with GTX 280 GPU as statistical samples for our power analysis. This methodology can certainly be applied to any other CUDA GPU.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116228728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008592
Suraj Pathak, Y. Tay, Q. Wei
Two major performance issues of Flash NAND are the write latency for random writes, and the lifetime of NAND chips. Several methods, mainly focusing on the Flash Translation Layer (FTL) or the Flash Buffer Management have been proposed to address these problems. In this paper, we propose an idea of reducing write traffic to Flash by the following steps: First we avoid repeated writes to Flash SSD by finding the redundant writes using a cryptographic HASH cipher. We design a set of acceleration techniques to reduce the latency overhead of this extra computational cost. Then we propose a PCM-based buffer extender for Flash SSD where we write the frequent updates to hot pages of Flash into PCM layer, which allows in-page update. Finally, while merging the PCM updated data to the Flash page, we use a special merging technique to change the flushes into sequential flushes, as sequential writes on Flash are almost thrice as fast as random writes. We maintain the redundant write finder mechanism in PCM. We test our design using a trace-driven simulator. The results show that compared to the traditional design technique, lifetime of Flash SSD can be more than quadrupled, while consuming 20% less power to do so with some improvement in write performance as well.
{"title":"Power and endurance aware Flash-PCM memory system","authors":"Suraj Pathak, Y. Tay, Q. Wei","doi":"10.1109/IGCC.2011.6008592","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008592","url":null,"abstract":"Two major performance issues of Flash NAND are the write latency for random writes, and the lifetime of NAND chips. Several methods, mainly focusing on the Flash Translation Layer (FTL) or the Flash Buffer Management have been proposed to address these problems. In this paper, we propose an idea of reducing write traffic to Flash by the following steps: First we avoid repeated writes to Flash SSD by finding the redundant writes using a cryptographic HASH cipher. We design a set of acceleration techniques to reduce the latency overhead of this extra computational cost. Then we propose a PCM-based buffer extender for Flash SSD where we write the frequent updates to hot pages of Flash into PCM layer, which allows in-page update. Finally, while merging the PCM updated data to the Flash page, we use a special merging technique to change the flushes into sequential flushes, as sequential writes on Flash are almost thrice as fast as random writes. We maintain the redundant write finder mechanism in PCM. We test our design using a trace-driven simulator. The results show that compared to the traditional design technique, lifetime of Flash SSD can be more than quadrupled, while consuming 20% less power to do so with some improvement in write performance as well.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130893666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008548
Nga Dang, E. Bozorgzadeh, N. Venkatasubramanian
Renewable energy technology has become a promising solution to reduce energy concerns due to limited battery in wireless sensor networks. While this enables us to prolong the lifetime of a sensor network (perpetually), unstable environmental energy sources bring challenges in the design of sustainable sensor networks. In this paper, we propose an adaptive energy harvesting management framework, QuARES, which exploits an application's tolerance to quality degradation to adjust application quality based on energy harvesting conditions. The proposed framework consists of two stages: an offline stage which uses prediction of harvested energy to allocate energy budget for time slots; and an online stage to tackle the fluctuation in time-varying energy harvesting profile. We implemented the application and our framework in a network simulator, QualNet. In comparison with other approaches (e.g., [9]), our system offers improved sustainability (low energy consumption, no node deaths) during operation with data quality improvement ranging from 30–70%. QuARES is currently being deployed in a campus-wide pervasive space at UCI called Responsphere[11].
{"title":"QuARES: Quality-aware data collection in energy harvesting sensor networks","authors":"Nga Dang, E. Bozorgzadeh, N. Venkatasubramanian","doi":"10.1109/IGCC.2011.6008548","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008548","url":null,"abstract":"Renewable energy technology has become a promising solution to reduce energy concerns due to limited battery in wireless sensor networks. While this enables us to prolong the lifetime of a sensor network (perpetually), unstable environmental energy sources bring challenges in the design of sustainable sensor networks. In this paper, we propose an adaptive energy harvesting management framework, QuARES, which exploits an application's tolerance to quality degradation to adjust application quality based on energy harvesting conditions. The proposed framework consists of two stages: an offline stage which uses prediction of harvested energy to allocate energy budget for time slots; and an online stage to tackle the fluctuation in time-varying energy harvesting profile. We implemented the application and our framework in a network simulator, QualNet. In comparison with other approaches (e.g., [9]), our system offers improved sustainability (low energy consumption, no node deaths) during operation with data quality improvement ranging from 30–70%. QuARES is currently being deployed in a campus-wide pervasive space at UCI called Responsphere[11].","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"76 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134128157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008559
G. Agosta, Marco Bessi, E. Capra, C. Francalanci
Software applications directly impact on IT energy consumptions as they indirectly guide hardware operations. Optimizing algorithms has a direct beneficial impact on energy efficiency, but it requires domain knowledge and an accurate analysis of the code, which may be infeasible and too costly to perform for large code bases. In this paper we present an approach based on dynamic memoization to increase software energy efficiency. This implies to identify a subset of pure functions that can be tabulated and to automatically store the results corresponding to the most frequent invocations. We implemented a prototype software system to apply memoization and tested it on a set of financial functions. Empirical results show average energy savings of 74% and time performance savings of 79%.
{"title":"Dynamic memoization for energy efficiency in financial applications","authors":"G. Agosta, Marco Bessi, E. Capra, C. Francalanci","doi":"10.1109/IGCC.2011.6008559","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008559","url":null,"abstract":"Software applications directly impact on IT energy consumptions as they indirectly guide hardware operations. Optimizing algorithms has a direct beneficial impact on energy efficiency, but it requires domain knowledge and an accurate analysis of the code, which may be infeasible and too costly to perform for large code bases. In this paper we present an approach based on dynamic memoization to increase software energy efficiency. This implies to identify a subset of pure functions that can be tabulated and to automatically store the results corresponding to the most frequent invocations. We implemented a prototype software system to apply memoization and tested it on a set of financial functions. Empirical results show average energy savings of 74% and time performance savings of 79%.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132082028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008593
Farzad Samie, A. Baniasadi
In this work we study control independence in embedded processors. We classify control independent instructions to data dependent and data independent and measure each group's frequency and behavior. Moreover, we study how control independent instructions impact power dissipation and resource utilization. We also investigate control independent instructions' behavior for different processors and branch predictors. Our study shows that data independent instructions account for 34% of the control independent instructions in the applications studied here. We also show that control independent instructions account for upto 12% of the processor energy and 15.6%, 11.2% and 8.6% of the instructions fetched, decoded and executed respectively. We also show that control independent instruction frequency increases with register update unit (RUU) size and issue width but shows little sensitivity to branch predictor size. In addition, we illustrate that control independent data independent instructions account for upto 6% of the processor energy. We also show that control independent data independent instruction frequency increases with RUU size and issue width.
{"title":"Power and frequency analysis for data and control independence in embedded processors","authors":"Farzad Samie, A. Baniasadi","doi":"10.1109/IGCC.2011.6008593","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008593","url":null,"abstract":"In this work we study control independence in embedded processors. We classify control independent instructions to data dependent and data independent and measure each group's frequency and behavior. Moreover, we study how control independent instructions impact power dissipation and resource utilization. We also investigate control independent instructions' behavior for different processors and branch predictors. Our study shows that data independent instructions account for 34% of the control independent instructions in the applications studied here. We also show that control independent instructions account for upto 12% of the processor energy and 15.6%, 11.2% and 8.6% of the instructions fetched, decoded and executed respectively. We also show that control independent instruction frequency increases with register update unit (RUU) size and issue width but shows little sensitivity to branch predictor size. In addition, we illustrate that control independent data independent instructions account for upto 6% of the processor energy. We also show that control independent data independent instruction frequency increases with RUU size and issue width.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132573420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008579
Jie Meng, Daniel Rossell, A. Coskun
3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5°C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.
{"title":"Exploring performance, power, and temperature characteristics of 3D systems with on-chip DRAM","authors":"Jie Meng, Daniel Rossell, A. Coskun","doi":"10.1109/IGCC.2011.6008579","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008579","url":null,"abstract":"3D integration enables stacking DRAM layers on processor cores within the same chip. On-chip memory has the potential to dramatically improve performance due to lower memory access latency and higher bandwidth. Higher core performance increases power density, requiring a thorough evaluation of the tradeoff between performance and temperature. This paper presents a comprehensive framework for exploring the power, performance, and temperature characteristics of 3D systems with on-chip DRAM. Utilizing this framework, we quantify the performance improvement as well as the power and thermal profiles of parallel workloads running on a 16-core 3D system with on-chip DRAM. The 3D system improves application performance by 72.6% on average in comparison to an equivalent 2D chip with off-chip memory. Power consumption per core increases by up to 32.7%. The increase in peak chip temperature, however, is limited to 1.5°C as the lower power DRAM layers share the heat of the hotter cores. Experimental results show that while DRAM stacking is a promising technique for high-end systems, efficient thermal management strategies are needed in embedded systems with cost or space restrictions to compensate for the lack of efficient cooling.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133253502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008588
Hui Chen, Meina Song, Junde Song, Ada Gavrilovska, K. Schwan, M. Kesavan
Using virtualization to consolidate servers is a routine method for reducing power consumption in data centers. Current practice, however, assumes homogeneous servers that operate in a homogeneous physical environment. Experimental evidence collected in our mid-size, fully instrumented data center challenges those assumptions, by finding that chassis construction can significantly influence cooling power usage. In particular, the multiple power domains in a single chassis can have different levels of power efficiency, and further, power consumption is affected by the differences in electrical current levels across these two domains. This paper describes experiments designed to validate these facts, followed by a proposed current-aware capacity management system (CACM) that controls resource allocation across power domains by periodically migrating virtual machines among servers. The method not only fully accounts for the influence of current difference between the two domains, but also enforces power caps and safety levels for node temperature levels. Comparisons with industry-standard techniques that are not aware of physical constraints show that current-awareness can improve performance as well as power consumption, with about 16% in energy savings. Such savings indicate the utility of adding physical awareness to the ways in which IT systems are managed.
{"title":"CACM: Current-aware capacity management in consolidated server enclosures","authors":"Hui Chen, Meina Song, Junde Song, Ada Gavrilovska, K. Schwan, M. Kesavan","doi":"10.1109/IGCC.2011.6008588","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008588","url":null,"abstract":"Using virtualization to consolidate servers is a routine method for reducing power consumption in data centers. Current practice, however, assumes homogeneous servers that operate in a homogeneous physical environment. Experimental evidence collected in our mid-size, fully instrumented data center challenges those assumptions, by finding that chassis construction can significantly influence cooling power usage. In particular, the multiple power domains in a single chassis can have different levels of power efficiency, and further, power consumption is affected by the differences in electrical current levels across these two domains. This paper describes experiments designed to validate these facts, followed by a proposed current-aware capacity management system (CACM) that controls resource allocation across power domains by periodically migrating virtual machines among servers. The method not only fully accounts for the influence of current difference between the two domains, but also enforces power caps and safety levels for node temperature levels. Comparisons with industry-standard techniques that are not aware of physical constraints show that current-awareness can improve performance as well as power consumption, with about 16% in energy savings. Such savings indicate the utility of adding physical awareness to the ways in which IT systems are managed.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115069642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008612
S. Gupta, Rose Robin Gilbert, Ayan Banerjee, Z. Abbasi, T. Mukherjee, G. Varsamopoulos
Energy consumption in data centers can be reduced by efficient design of the data centers and efficient management of computing resources and cooling units. A major obstacle in the analysis of data centers is the lack of a holistic simulator, where the impact of new computing resource (or cooling) management techniques can be tested with diffierent designs (i.e., layouts and configurations) of data centers. To fill this gap, this paper proposes Green Data Center Simulator (GDCSim) for studying the energy efficiency of data centers under various data center geometries, workload characteristics, platform power management schemes, and scheduling algorithms. GDCSim is used to iteratively design green data centers. Further, it is validated against established CFD simulators. GDCSim is developed as a part of the BlueTool infrastructure project at Impact Lab.
{"title":"GDCSim: A tool for analyzing Green Data Center design and resource management techniques","authors":"S. Gupta, Rose Robin Gilbert, Ayan Banerjee, Z. Abbasi, T. Mukherjee, G. Varsamopoulos","doi":"10.1109/IGCC.2011.6008612","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008612","url":null,"abstract":"Energy consumption in data centers can be reduced by efficient design of the data centers and efficient management of computing resources and cooling units. A major obstacle in the analysis of data centers is the lack of a holistic simulator, where the impact of new computing resource (or cooling) management techniques can be tested with diffierent designs (i.e., layouts and configurations) of data centers. To fill this gap, this paper proposes Green Data Center Simulator (GDCSim) for studying the energy efficiency of data centers under various data center geometries, workload characteristics, platform power management schemes, and scheduling algorithms. GDCSim is used to iteratively design green data centers. Further, it is validated against established CFD simulators. GDCSim is developed as a part of the BlueTool infrastructure project at Impact Lab.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116478335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Energy consumption is becoming a growing concern in data centers. Many energy-conservation techniques have been proposed to address this problem. However, an integrated method is still needed to evaluate energy efficiency of storage systems and various power conservation techniques. Extensive measurements of different workloads on storage systems are often very time-consuming and require expensive equipments. We have analyzed changing characteristics such as power and performance of stand-alone disks and RAID arrays, and then defined MIND as a black box power model for RAID arrays. MIND is devised to quantitatively measure the power consumption of redundant disk arrays running different workloads in a variety of execution modes. In MIND, we define five modes (idle, standby, and several types of access) and four actions, to precisely characterize power states and changes of RAID arrays. In addition, we develop corresponding metrics for each mode and action, and then integrate the model and a measurement algorithm into a popular trace tool - blktrace. With these features, we are able to run different IO traces on large-scale storage systems with power conservation techniques. Accurate energy consumption and performance statistics are then collected to evaluate energy efficiency of storage system designs and power conservation techniques. Our experiments running both synthetic and real-world workloads on enterprise RAID arrays show that MIND can estimate power consumptions of disk arrays with an error rate less than 2%.
{"title":"MIND: A black-box energy consumption model for disk arrays","authors":"Zhuo Liu, Jian Zhou, Weikuan Yu, Fei Wu, X. Qin, C. Xie","doi":"10.1109/IGCC.2011.6008571","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008571","url":null,"abstract":"Energy consumption is becoming a growing concern in data centers. Many energy-conservation techniques have been proposed to address this problem. However, an integrated method is still needed to evaluate energy efficiency of storage systems and various power conservation techniques. Extensive measurements of different workloads on storage systems are often very time-consuming and require expensive equipments. We have analyzed changing characteristics such as power and performance of stand-alone disks and RAID arrays, and then defined MIND as a black box power model for RAID arrays. MIND is devised to quantitatively measure the power consumption of redundant disk arrays running different workloads in a variety of execution modes. In MIND, we define five modes (idle, standby, and several types of access) and four actions, to precisely characterize power states and changes of RAID arrays. In addition, we develop corresponding metrics for each mode and action, and then integrate the model and a measurement algorithm into a popular trace tool - blktrace. With these features, we are able to run different IO traces on large-scale storage systems with power conservation techniques. Accurate energy consumption and performance statistics are then collected to evaluate energy efficiency of storage system designs and power conservation techniques. Our experiments running both synthetic and real-world workloads on enterprise RAID arrays show that MIND can estimate power consumptions of disk arrays with an error rate less than 2%.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"281 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134148912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008590
Xiongzi Ge, D. Feng, D. Du
Much research has been conducted on energy efficient cache buffer management for disk based storage systems. Some of them use greedy prefetching technique to artificially increase disk idle intervals if there are a large number of known future requests. However, this might result in sub-optimal solution by not exploiting the relationship between I/O access pattern (sequential/random) and application pattern (CPU required for computing time). In a CPU-bound application, by explicitly taking into account this relationship it may reduce energy conservation by up to 50% and increase power cycle number by 100% compared to an existing efficient prefetching scheme without this consideration. In this paper, we consider the tradeoff between disk power consumption, performance guarantee and disk reliability all together by proposing a Disk characteristic based Power-Optimal Prefetching (DiscPOP) scheme. Specifically, we make two contributions: (i) A theoretical model is conducted to analyze energy-efficient cache buffer management in disk I/O system and it is formulated as an optimization problem. We have shown it can be solved via an Integer Linear Programming (ILP) technique. (ii) We propose a simple Divide-and-Conquer based offline algorithm named Greedy Partition (GP) to divide the problem into several small ones and solve them separately via an ILP solver. We use trace-driven simulations to evaluate our proposed scheme. The results show GP outperforms the traditional aggressive prefetching by up to 29.2% more disk energy conservation and 20.6% power cycle reduction.
{"title":"DiscPOP: Power-aware buffer management for disk accesses","authors":"Xiongzi Ge, D. Feng, D. Du","doi":"10.1109/IGCC.2011.6008590","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008590","url":null,"abstract":"Much research has been conducted on energy efficient cache buffer management for disk based storage systems. Some of them use greedy prefetching technique to artificially increase disk idle intervals if there are a large number of known future requests. However, this might result in sub-optimal solution by not exploiting the relationship between I/O access pattern (sequential/random) and application pattern (CPU required for computing time). In a CPU-bound application, by explicitly taking into account this relationship it may reduce energy conservation by up to 50% and increase power cycle number by 100% compared to an existing efficient prefetching scheme without this consideration. In this paper, we consider the tradeoff between disk power consumption, performance guarantee and disk reliability all together by proposing a Disk characteristic based Power-Optimal Prefetching (DiscPOP) scheme. Specifically, we make two contributions: (i) A theoretical model is conducted to analyze energy-efficient cache buffer management in disk I/O system and it is formulated as an optimization problem. We have shown it can be solved via an Integer Linear Programming (ILP) technique. (ii) We propose a simple Divide-and-Conquer based offline algorithm named Greedy Partition (GP) to divide the problem into several small ones and solve them separately via an ILP solver. We use trace-driven simulations to evaluate our proposed scheme. The results show GP outperforms the traditional aggressive prefetching by up to 29.2% more disk energy conservation and 20.6% power cycle reduction.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132837122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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