Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008584
M. Collin, M. Brorsson, Johnny Öberg
We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.
{"title":"A performance and energy exploration of dictionary code compression architectures","authors":"M. Collin, M. Brorsson, Johnny Öberg","doi":"10.1109/IGCC.2011.6008584","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008584","url":null,"abstract":"We have made a performance and energy exploration of a previously proposed dictionary code compression mechanism where frequently executed individual instructions and/or sequences are replaced in memory with short code words. Our simulated design shows a dramatically reduced instruction memory access frequency leading to a performance improvement for small instruction cache sizes and to significantly reduced energy consumption in the instruction fetch path. We have evaluated the performance and energy implications of three architectural parameters: branch prediction accuracy, instruction cache size and organization. To asses the complexity of the design we have implemented the critical stages in VHDL.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122290814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008568
Norifumi Nishikawa, M. Nakano, M. Kitsuregawa
Power consumption of storage at data centers is increasing rapidly. Large storage facilities have various RAID configurations incorporating different RAID levels, numbers of drives, and media types. Nevertheless, few discussions of RAID configurations have been pursued from an energy saving perspective. We first investigate how different RAID configurations affect not only application performance but also power consumption of storage installations. We then present simulation results of power consumption and application performance conducted with various RAID configurations. Results show that a RAID configuration strongly impacts energy conservation based on application I/O features.
{"title":"Energy aware RAID configuration for large storage systems","authors":"Norifumi Nishikawa, M. Nakano, M. Kitsuregawa","doi":"10.1109/IGCC.2011.6008568","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008568","url":null,"abstract":"Power consumption of storage at data centers is increasing rapidly. Large storage facilities have various RAID configurations incorporating different RAID levels, numbers of drives, and media types. Nevertheless, few discussions of RAID configurations have been pursued from an energy saving perspective. We first investigate how different RAID configurations affect not only application performance but also power consumption of storage installations. We then present simulation results of power consumption and application performance conducted with various RAID configurations. Results show that a RAID configuration strongly impacts energy conservation based on application I/O features.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008603
C. Teuscher, H. Chung, A. Grimm, Avinash Amarnath, Neha Parashar
Power and energy issues have significantly gained in importance in computing environments in the last few decades. In a world of mobile devices and massive-scale data centers, low-power systems are crucial for cost, availability, and the environment. Minimizing power consumption in a computing system is a complex problem that can be addressed with various strategies and on various levels. In this paper we focus on System-on-Chip (SoC), and in particular on power-efficient Network-on-Chip (NoC) topologies. The popular saying that “there ain't no such thing as a free lunch” applies to computing systems likewise. In the quest for power and performance optima in the design space of NoC, we investigate non-local interconnect architectures for SoC. By adopting a complex network perspective and by employing an optimization technique, we show that small-world networks with power-law distance-dependent wire-length distributions are more power-efficient while offering the same performance than simple small-world topologies. We argue that such networks occupy optimal spots in the design space of NoCs. Our results are particularly relevant for addressing the scalability problem of global (or long-range) links, for building more power-efficient computers, and for emerging computing devices built through self-assembly.
{"title":"The power of power-laws: Or how to save power in SoC","authors":"C. Teuscher, H. Chung, A. Grimm, Avinash Amarnath, Neha Parashar","doi":"10.1109/IGCC.2011.6008603","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008603","url":null,"abstract":"Power and energy issues have significantly gained in importance in computing environments in the last few decades. In a world of mobile devices and massive-scale data centers, low-power systems are crucial for cost, availability, and the environment. Minimizing power consumption in a computing system is a complex problem that can be addressed with various strategies and on various levels. In this paper we focus on System-on-Chip (SoC), and in particular on power-efficient Network-on-Chip (NoC) topologies. The popular saying that “there ain't no such thing as a free lunch” applies to computing systems likewise. In the quest for power and performance optima in the design space of NoC, we investigate non-local interconnect architectures for SoC. By adopting a complex network perspective and by employing an optimization technique, we show that small-world networks with power-law distance-dependent wire-length distributions are more power-efficient while offering the same performance than simple small-world topologies. We argue that such networks occupy optimal spots in the design space of NoCs. Our results are particularly relevant for addressing the scalability problem of global (or long-range) links, for building more power-efficient computers, and for emerging computing devices built through self-assembly.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128923173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008613
Megan Ayers, Yao Liang
Quality of Service (QoS) control is of paramount importance in wireless sensor networks. In this paper we propose a new QoS control algorithm, referred to as Gureen Game, for wireless sensor networks. Gureen Game not only improves the Gur Game for QoS control but also significantly addresses the power consumption weakness of the original Gur Game based QoS control for senor networks. We study the logic behaviors of the proposed Gureen Game, and evaluate its QoS performance compared with the original Gur Game and a recent control algorithm called Shuffle for energy-efficient QoS control. Our simulation results demonstrate the merits of the proposed Gureen Game.
{"title":"Gureen Game: An energy-efficient QoS control scheme for wireless sensor networks","authors":"Megan Ayers, Yao Liang","doi":"10.1109/IGCC.2011.6008613","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008613","url":null,"abstract":"Quality of Service (QoS) control is of paramount importance in wireless sensor networks. In this paper we propose a new QoS control algorithm, referred to as Gureen Game, for wireless sensor networks. Gureen Game not only improves the Gur Game for QoS control but also significantly addresses the power consumption weakness of the original Gur Game based QoS control for senor networks. We study the logic behaviors of the proposed Gureen Game, and evaluate its QoS performance compared with the original Gur Game and a recent control algorithm called Shuffle for energy-efficient QoS control. Our simulation results demonstrate the merits of the proposed Gureen Game.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115779100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008576
Bing Shi, Ankur Srivastava
This paper investigated micro-channel based liquid cooling in 3D-ICs. Specifically, the structure of 3D-IC with micro-channels, and its thermal/hydrodynamic modeling are studied. Also, the design challenges of micro-channel heat sinks in 3D-IC are summarized.
{"title":"Liquid cooling for 3D-ICs","authors":"Bing Shi, Ankur Srivastava","doi":"10.1109/IGCC.2011.6008576","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008576","url":null,"abstract":"This paper investigated micro-channel based liquid cooling in 3D-ICs. Specifically, the structure of 3D-IC with micro-channels, and its thermal/hydrodynamic modeling are studied. Also, the design challenges of micro-channel heat sinks in 3D-IC are summarized.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128151218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008611
Anshul Gandhi, Yuan Chen, D. Gmach, M. Arlitt, M. Marwah
This paper presents a novel approach to correctly allocate resources in data centers, such that SLA violations and energy consumption are minimized. Our approach first analyzes historical workload traces to identify long-term patterns that establish a “base” workload. It then employs two techniques to dynamically allocate capacity: predictive provisioning handles the estimated base workload at coarse time scales (e.g., hours or days) and reactive provisioning handles any excess workload at finer time scales (e.g., minutes). The combination of predictive and reactive provisioning achieves a significant improvement in meeting SLAs, conserving energy, and reducing provisioning costs. We implement and evaluate our approach using traces from four production systems. The results show that our approach can provide up to 35% savings in power consumption and reduce SLA violations by as much as 21% compared to existing techniques, while avoiding frequent power cycling of servers.
{"title":"Minimizing data center SLA violations and power consumption via hybrid resource provisioning","authors":"Anshul Gandhi, Yuan Chen, D. Gmach, M. Arlitt, M. Marwah","doi":"10.1109/IGCC.2011.6008611","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008611","url":null,"abstract":"This paper presents a novel approach to correctly allocate resources in data centers, such that SLA violations and energy consumption are minimized. Our approach first analyzes historical workload traces to identify long-term patterns that establish a “base” workload. It then employs two techniques to dynamically allocate capacity: predictive provisioning handles the estimated base workload at coarse time scales (e.g., hours or days) and reactive provisioning handles any excess workload at finer time scales (e.g., minutes). The combination of predictive and reactive provisioning achieves a significant improvement in meeting SLAs, conserving energy, and reducing provisioning costs. We implement and evaluate our approach using traces from four production systems. The results show that our approach can provide up to 35% savings in power consumption and reduce SLA violations by as much as 21% compared to existing techniques, while avoiding frequent power cycling of servers.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008609
X. Lin
Minimizing power consumption during functional operation and during manufacturing test has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial DFT tool point of view, this paper describes the capabilities the DFT tools can provide to achieve comprehensive testing of low power designs as well as to reduce test power consumption during test application.
{"title":"Low power testing - What can commercial DFT tools provide?","authors":"X. Lin","doi":"10.1109/IGCC.2011.6008609","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008609","url":null,"abstract":"Minimizing power consumption during functional operation and during manufacturing test has become one of the dominant requirements for the semiconductor designs in the past decade. From commercial DFT tool point of view, this paper describes the capabilities the DFT tools can provide to achieve comprehensive testing of low power designs as well as to reduce test power consumption during test application.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128879315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008566
Youngjin Nam, Guanlin Lu, D. Du
Reliability in deduplication storage has not attracted much research attention yet. To provide a demanded reliability for an incoming data stream, most deduplication storage systems first carry out deduplication process by eliminating duplicates from the data stream and then apply erasure coding for the remaining (unique) chunks. A unique chunk may be shared (i.e., duplicated) at many places of the data stream and shared by other data streams. That is why deduplication can reduce the required storage capacity. However, this occasionally becomes problematic to assure certain reliability levels required from different data streams. We introduce two reliability parameters for deduplication storage: chunk reliability and chunk loss severity. The chunk reliability means each chunk's tolerance level in the face of any failures. The chunk loss severity represents an expected damage level in the event of a chunk loss, formally defined as the multiplication of actual damage by the probability of a chunk loss. We propose a reliability-aware deduplication solution that not only assures all demanded chunk reliability levels by making already existing chunks sharable only if its reliability is high enough, but also mitigates the chunk loss severity by adaptively reducing the probability of having a chunk loss. In addition, we provide future research directions following to the current study.
{"title":"Reliability-aware deduplication storage: Assuring chunk reliability and chunk loss severity","authors":"Youngjin Nam, Guanlin Lu, D. Du","doi":"10.1109/IGCC.2011.6008566","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008566","url":null,"abstract":"Reliability in deduplication storage has not attracted much research attention yet. To provide a demanded reliability for an incoming data stream, most deduplication storage systems first carry out deduplication process by eliminating duplicates from the data stream and then apply erasure coding for the remaining (unique) chunks. A unique chunk may be shared (i.e., duplicated) at many places of the data stream and shared by other data streams. That is why deduplication can reduce the required storage capacity. However, this occasionally becomes problematic to assure certain reliability levels required from different data streams. We introduce two reliability parameters for deduplication storage: chunk reliability and chunk loss severity. The chunk reliability means each chunk's tolerance level in the face of any failures. The chunk loss severity represents an expected damage level in the event of a chunk loss, formally defined as the multiplication of actual damage by the probability of a chunk loss. We propose a reliability-aware deduplication solution that not only assures all demanded chunk reliability levels by making already existing chunks sharable only if its reliability is high enough, but also mitigates the chunk loss severity by adaptively reducing the probability of having a chunk loss. In addition, we provide future research directions following to the current study.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"49 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120941128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008569
Rishiraj A. Bheda, Jason A. Poovey, Jesse G. Beu, T. Conte
Phase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As the need for high-density memory increases, DRAM has proven to be less attractive from the point of view of scaling and energy consumption. PCM-only memories suffer from latency issues, high write energy, and the problem of limited write endurance. Research in this domain has focused mainly on using various hybrid memory configurations to address these shortcomings. A commodity DRAM module as a cache for PCM memory has emerged as a potential solution. But this method requires use of a separate memory controller and is unable to achieve better performance than a DRAM-only based memory at low energy. We propose a PCM based main memory system design using a small, embedded DRAM (eDRAM) cache to replace the row buffers in the PCM memory chip. This reduces the high latencies of PCM and the energy consumption of the main memory system. Our methodology also eliminates the need for separate memory controllers. Through simulation results, we show competitive performance by reducing average memory access time of a slow PCM based memory and significant energy reductions against a DDR3 commodity DRAM memory system of similar storage size. Our proposed system is highly energy efficient and provides 35.02%improvement in EDP over a DRAM-only system. Our system consumes less energy than the state-of-the-art PCM hybrid system using a commodity DRAM cache.
{"title":"Energy efficient Phase Change Memory based main memory for future high performance systems","authors":"Rishiraj A. Bheda, Jason A. Poovey, Jesse G. Beu, T. Conte","doi":"10.1109/IGCC.2011.6008569","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008569","url":null,"abstract":"Phase Change Memory (PCM) has recently attracted a lot of attention as a scalable alternative to DRAM for main memory systems. As the need for high-density memory increases, DRAM has proven to be less attractive from the point of view of scaling and energy consumption. PCM-only memories suffer from latency issues, high write energy, and the problem of limited write endurance. Research in this domain has focused mainly on using various hybrid memory configurations to address these shortcomings. A commodity DRAM module as a cache for PCM memory has emerged as a potential solution. But this method requires use of a separate memory controller and is unable to achieve better performance than a DRAM-only based memory at low energy. We propose a PCM based main memory system design using a small, embedded DRAM (eDRAM) cache to replace the row buffers in the PCM memory chip. This reduces the high latencies of PCM and the energy consumption of the main memory system. Our methodology also eliminates the need for separate memory controllers. Through simulation results, we show competitive performance by reducing average memory access time of a slow PCM based memory and significant energy reductions against a DDR3 commodity DRAM memory system of similar storage size. Our proposed system is highly energy efficient and provides 35.02%improvement in EDP over a DRAM-only system. Our system consumes less energy than the state-of-the-art PCM hybrid system using a commodity DRAM cache.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"13 11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125760382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-07-25DOI: 10.1109/IGCC.2011.6008610
Wei Huang, Malcolm S. Allen-Ware, J. Carter, E. Elnozahy, H. Hamann, T. Keller, C. Lefurgy, Jian Li, K. Rajamani, J. Rubio
A large portion of the power consumption of data centers can be attributed to cooling. In dynamic thermal management mechanisms for data centers and servers, thermal setpoints are typically chosen statically and conservatively, which leaves significant room for improvement in the form of improved energy efficiency. In this paper, we propose two hierarchical thermal-aware power optimization techniques that are complementary to each other and achieve (i) lower overall system power with no performance penalty or (ii) higher performance within the same power budget.
{"title":"TAPO: Thermal-aware power optimization techniques for servers and data centers","authors":"Wei Huang, Malcolm S. Allen-Ware, J. Carter, E. Elnozahy, H. Hamann, T. Keller, C. Lefurgy, Jian Li, K. Rajamani, J. Rubio","doi":"10.1109/IGCC.2011.6008610","DOIUrl":"https://doi.org/10.1109/IGCC.2011.6008610","url":null,"abstract":"A large portion of the power consumption of data centers can be attributed to cooling. In dynamic thermal management mechanisms for data centers and servers, thermal setpoints are typically chosen statically and conservatively, which leaves significant room for improvement in the form of improved energy efficiency. In this paper, we propose two hierarchical thermal-aware power optimization techniques that are complementary to each other and achieve (i) lower overall system power with no performance penalty or (ii) higher performance within the same power budget.","PeriodicalId":306876,"journal":{"name":"2011 International Green Computing Conference and Workshops","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133592650","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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