Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546482
C. Rodríguez, J. R. García, F. García, F. Almeida, Daniel González
We extend the sequential model for dynamic programming to a parallel model. We propose three general parallel dynamic programming algorithms for pipeline and ring networks for multistage automatons. The study of the optimality lead us to the introduction of two new classes of multistage automatons: nondecreasing automatons and strongly increasing automatons. As an example, this parallel dynamic programming approach is applied to the single resource allocation problem. Results both for transputer networks and for local area networks using PVM are reported. The experience proves that the proposed algorithms can be easily and efficiently implemented. Furthermore, these procedures constitute a suitable kernel to build general parallel tools for dynamic programming.
{"title":"Paradigms for parallel dynamic programming","authors":"C. Rodríguez, J. R. García, F. García, F. Almeida, Daniel González","doi":"10.1109/EURMIC.1996.546482","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546482","url":null,"abstract":"We extend the sequential model for dynamic programming to a parallel model. We propose three general parallel dynamic programming algorithms for pipeline and ring networks for multistage automatons. The study of the optimality lead us to the introduction of two new classes of multistage automatons: nondecreasing automatons and strongly increasing automatons. As an example, this parallel dynamic programming approach is applied to the single resource allocation problem. Results both for transputer networks and for local area networks using PVM are reported. The experience proves that the proposed algorithms can be easily and efficiently implemented. Furthermore, these procedures constitute a suitable kernel to build general parallel tools for dynamic programming.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133058245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546375
E. Lassila
This paper describes an experimental prototype of a code generation tool for embedded special-purpose processors. The tool is a retargetable assembly-code-level macro expander capable of program flow analysis. The main advantage of the tool is its strong support for macro hierarchy: hierarchical macro libraries make the code (produced either by the compiler writer or by the assembly language programmer) more modular.
{"title":"A macro expansion approach to embedded processor code generation","authors":"E. Lassila","doi":"10.1109/EURMIC.1996.546375","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546375","url":null,"abstract":"This paper describes an experimental prototype of a code generation tool for embedded special-purpose processors. The tool is a retargetable assembly-code-level macro expander capable of program flow analysis. The main advantage of the tool is its strong support for macro hierarchy: hierarchical macro libraries make the code (produced either by the compiler writer or by the assembly language programmer) more modular.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124825293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546392
H. Martin
This paper presents a new method for improving the timing behaviour of digital circuits, which contain enable-registers and, e.g., come from the high level synthesis. Known techniques optimize all long combinational paths assuming only one clock cycle between registers. But enable-registers cause also paths having more time than one clock cycle. The consideration of this paths leads to a larger optimization potential. As a second topic in the presented method a register relocation is performed for a circuit containing enable registers and D-Flipflops. A suitable retiming algorithm is developed for such circuits.
{"title":"Retiming for circuits with enable registers","authors":"H. Martin","doi":"10.1109/EURMIC.1996.546392","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546392","url":null,"abstract":"This paper presents a new method for improving the timing behaviour of digital circuits, which contain enable-registers and, e.g., come from the high level synthesis. Known techniques optimize all long combinational paths assuming only one clock cycle between registers. But enable-registers cause also paths having more time than one clock cycle. The consideration of this paths leads to a larger optimization potential. As a second topic in the presented method a register relocation is performed for a circuit containing enable registers and D-Flipflops. A suitable retiming algorithm is developed for such circuits.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124909450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546475
A. Postula, D. Abramson, P. Logothetis
This paper presents the design decisions encountered during the development of a specialised processor for the Monte-Carlo simulation of metallurgical sintering. Several possible architectures are presented. We show that such a specialised processor using commercially available gate array technology can solve the same problem more than 100 times faster than a modern high-end workstation. Even using slower FPGAs it is possible to achieve a speedup of over 50 times faster than a workstation, which supports the concept of programmable special purpose computers attached to general purpose machines. A prototype of the processor is now being built using Xilinx FPGA and Aptix FPIC switch technology.
{"title":"The design of a specialised processor for the simulation of sintering","authors":"A. Postula, D. Abramson, P. Logothetis","doi":"10.1109/EURMIC.1996.546475","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546475","url":null,"abstract":"This paper presents the design decisions encountered during the development of a specialised processor for the Monte-Carlo simulation of metallurgical sintering. Several possible architectures are presented. We show that such a specialised processor using commercially available gate array technology can solve the same problem more than 100 times faster than a modern high-end workstation. Even using slower FPGAs it is possible to achieve a speedup of over 50 times faster than a workstation, which supports the concept of programmable special purpose computers attached to general purpose machines. A prototype of the processor is now being built using Xilinx FPGA and Aptix FPIC switch technology.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113980368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546459
K. Goseva-Popstojanova, A. Grnarov
This paper presents an unified approach aimed at modeling the joint behavior of the N version system and its operational environment. Our objective is to develop reliability model that considers both functional and performance requirements which is particularly important for real-time applications. The model is constructed in two steps. First, the Markov model of N version failure and execution behavior is developed. Next, we develop the user-oriented model of the operational environment. In accounting for dependence we use the idea that the influence of the operational environment on versions failures and execution times induces correlation. The model addresses a number of basic issues and yet yields closed-form solutions that provide considerable insight into how reliability is affected by both versions characteristics and the operational environment.
{"title":"N-version programming: a unified modeling approach","authors":"K. Goseva-Popstojanova, A. Grnarov","doi":"10.1109/EURMIC.1996.546459","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546459","url":null,"abstract":"This paper presents an unified approach aimed at modeling the joint behavior of the N version system and its operational environment. Our objective is to develop reliability model that considers both functional and performance requirements which is particularly important for real-time applications. The model is constructed in two steps. First, the Markov model of N version failure and execution behavior is developed. Next, we develop the user-oriented model of the operational environment. In accounting for dependence we use the idea that the influence of the operational environment on versions failures and execution times induces correlation. The model addresses a number of basic issues and yet yields closed-form solutions that provide considerable insight into how reliability is affected by both versions characteristics and the operational environment.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126604166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546474
M. Bettaz, M. Maouche, Kamel Barkaoui
ECATNets are a specification framework based on an ad-hoc combination of Petri nets and abstract data types. The concept of rewriting logic is used to give them a "clean" semantics. Transforming this logic into a rewriting system may be used for prototyping the specified systems. A major drawback of our framework is that the achieved prototypes suffer from a lack of efficiency during their execution. To palliate this lack, we introduced in a previous work the concept of hidden sorted ECATNets, a combination of net/object model allowing to "hide" internal states, and then to get more rapid prototypes. The objective of this paper is to show the practical applicability of this concept on a "benchmark" from the area of communication protocols, the Ethernet protocol such as seen by a sending station.
{"title":"Formal specification of communication protocols with object-based ECATNets","authors":"M. Bettaz, M. Maouche, Kamel Barkaoui","doi":"10.1109/EURMIC.1996.546474","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546474","url":null,"abstract":"ECATNets are a specification framework based on an ad-hoc combination of Petri nets and abstract data types. The concept of rewriting logic is used to give them a \"clean\" semantics. Transforming this logic into a rewriting system may be used for prototyping the specified systems. A major drawback of our framework is that the achieved prototypes suffer from a lack of efficiency during their execution. To palliate this lack, we introduced in a previous work the concept of hidden sorted ECATNets, a combination of net/object model allowing to \"hide\" internal states, and then to get more rapid prototypes. The objective of this paper is to show the practical applicability of this concept on a \"benchmark\" from the area of communication protocols, the Ethernet protocol such as seen by a sending station.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"20 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132610138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546481
Y. Cotronis
A message passing program composition methodology, called Ensemble, applied for Parix is presented. Ensemble overcomes the implementation problems and complexities in developing applications in message passing environments. Parallel applications are virtually specified by Process Communication Graphs (PCGs) annotated with communication information for Parix processes. Annotated PCGs are generated from application scripts by supporting tools. Reusable Parix executable components are defined from which all processes are created. A universal Parix program loader interprets the annotated PCGs creating the application processes from the reusable components and establishing their communication dependencies. Ensemble is applied to compose variations of Parix applications using the same reusable components. The methodology has been applied for PVM.
{"title":"Efficient program composition on Parix by the Ensemble methodology","authors":"Y. Cotronis","doi":"10.1109/EURMIC.1996.546481","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546481","url":null,"abstract":"A message passing program composition methodology, called Ensemble, applied for Parix is presented. Ensemble overcomes the implementation problems and complexities in developing applications in message passing environments. Parallel applications are virtually specified by Process Communication Graphs (PCGs) annotated with communication information for Parix processes. Annotated PCGs are generated from application scripts by supporting tools. Reusable Parix executable components are defined from which all processes are created. A universal Parix program loader interprets the annotated PCGs creating the application processes from the reusable components and establishing their communication dependencies. Ensemble is applied to compose variations of Parix applications using the same reusable components. The methodology has been applied for PVM.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"251 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132437796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546483
A. Molano, A. García-Martínez, Á. Viña
In this paper we present the design and implementation of a client/server based multimedia architecture for supporting video-on-demand applications. We describe in detail the software architecture of the implementation along with the adopted buffering mechanism. The proposed multithreaded architecture obtains, on one hand, a high degree of parallelism at the server side, allowing both the disk controller and the network card controller work in parallel. On the other hand; at the client side, it achieves the synchronized playback of the video stream at its precise rate, decoupling this process from the reception of data through the network. Additionally, we have derived, under an engineering perspective, some services that a real-time operating system should offer to satisfy the requirements found in video-on-demand applications.
{"title":"The design and implementation of a multimedia storage server to support video-on-demand applications","authors":"A. Molano, A. García-Martínez, Á. Viña","doi":"10.1109/EURMIC.1996.546483","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546483","url":null,"abstract":"In this paper we present the design and implementation of a client/server based multimedia architecture for supporting video-on-demand applications. We describe in detail the software architecture of the implementation along with the adopted buffering mechanism. The proposed multithreaded architecture obtains, on one hand, a high degree of parallelism at the server side, allowing both the disk controller and the network card controller work in parallel. On the other hand; at the client side, it achieves the synchronized playback of the video stream at its precise rate, decoupling this process from the reception of data through the network. Additionally, we have derived, under an engineering perspective, some services that a real-time operating system should offer to satisfy the requirements found in video-on-demand applications.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"128 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131718347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546366
A. García-Martínez, J. Fernández-Conde, Á. Viña
In real-time computing the accurate characterization of the performance and determinism that a particular real-time operating system/hardware combination can provide for real-time applications is essential. This issue is not properly addressed by existing performance metrics mainly due to the lack of completeness and generalization. In this paper we present a set of comprehensive, easy-to-implement and useful metrics covering three basic real-time operating system features: response to external events, intertask synchronization and resource sharing, and intertask data transferring. The evaluation of real-time operating systems using a set of fine-grained metrics is fundamental to guarantee that we can reach the required determinism in real-world applications.
{"title":"A comprehensive approach in performance evaluation for modern real-time operating systems","authors":"A. García-Martínez, J. Fernández-Conde, Á. Viña","doi":"10.1109/EURMIC.1996.546366","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546366","url":null,"abstract":"In real-time computing the accurate characterization of the performance and determinism that a particular real-time operating system/hardware combination can provide for real-time applications is essential. This issue is not properly addressed by existing performance metrics mainly due to the lack of completeness and generalization. In this paper we present a set of comprehensive, easy-to-implement and useful metrics covering three basic real-time operating system features: response to external events, intertask synchronization and resource sharing, and intertask data transferring. The evaluation of real-time operating systems using a set of fine-grained metrics is fundamental to guarantee that we can reach the required determinism in real-world applications.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121190459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546365
Aziz Can Yuceturk, B. Klauer, S. Zickenheiner, R. Moore, K. Waldschmidt
The aim of this paper is to give a formal definition for mapping neural networks onto data flow graphs. The intention of this research is to show formally that data flow computers can be used to implement neural network models. To do this, we need formal definitions of both data flow graphs and neural networks. Based on these definitions, we generate rules for mapping neural network models onto data flow graphs.
{"title":"Mapping of neural networks onto data flow graphs","authors":"Aziz Can Yuceturk, B. Klauer, S. Zickenheiner, R. Moore, K. Waldschmidt","doi":"10.1109/EURMIC.1996.546365","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546365","url":null,"abstract":"The aim of this paper is to give a formal definition for mapping neural networks onto data flow graphs. The intention of this research is to show formally that data flow computers can be used to implement neural network models. To do this, we need formal definitions of both data flow graphs and neural networks. Based on these definitions, we generate rules for mapping neural network models onto data flow graphs.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116332418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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