Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546458
R. Bevacqua, L. Guerrazzi, F. Fummi
Test pattern storage is an important problem affecting all Design for Testability (DfT) techniques based on scan-path. Built-In Self Test (BIST) methodologies are used in conjunction to scan-path techniques for reducing the amount of test patterns that must be stored. This paper analyzes two SCAN/BIST approaches and identifies conditions which guarantee that such techniques require shorter test sequences in relation to a simple scan method. Such conditions concern the ability of sequential test pattern generators (TPGs) to concatenate test sequences, but, unfortunately, standard sequential TPGs do not show sufficient capabilities in this task. This, the paper presents an innovative concatenation strategy for test sequences based on implicit techniques. Preliminary results and a case-study show that the use of the presented SCAN/BIST approaches, with the proposed test generation strategy, generates a test methodology that sensibly reduce the amount of test patterns which must be stored.
{"title":"SCAN/BIST techniques for decreasing test storage and their implications to test pattern generation","authors":"R. Bevacqua, L. Guerrazzi, F. Fummi","doi":"10.1109/EURMIC.1996.546458","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546458","url":null,"abstract":"Test pattern storage is an important problem affecting all Design for Testability (DfT) techniques based on scan-path. Built-In Self Test (BIST) methodologies are used in conjunction to scan-path techniques for reducing the amount of test patterns that must be stored. This paper analyzes two SCAN/BIST approaches and identifies conditions which guarantee that such techniques require shorter test sequences in relation to a simple scan method. Such conditions concern the ability of sequential test pattern generators (TPGs) to concatenate test sequences, but, unfortunately, standard sequential TPGs do not show sufficient capabilities in this task. This, the paper presents an innovative concatenation strategy for test sequences based on implicit techniques. Preliminary results and a case-study show that the use of the presented SCAN/BIST approaches, with the proposed test generation strategy, generates a test methodology that sensibly reduce the amount of test patterns which must be stored.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122091798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546464
P. Raatikainen, Teleste Oy, Juha Zidbeck
This article surveys some interconnection networks, especially rings, utilized in broadband switching and compares their transfer delay performance. Special attention is paid to a ring, named Frame Synchronized Ring (FSR), which is developed for high speed switching and experimented as an ATM-switch. The study concentrates on analysing the transfer delay performance of the switching architectures to compare the rings with the other introduced switch structures (i.e. multidrop bus, crossbar, and multistage banyan network). The analysis is followed by some characteristics and experiments with the FSR.
{"title":"Performance comparison of experimented switching architectures for ATM","authors":"P. Raatikainen, Teleste Oy, Juha Zidbeck","doi":"10.1109/EURMIC.1996.546464","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546464","url":null,"abstract":"This article surveys some interconnection networks, especially rings, utilized in broadband switching and compares their transfer delay performance. Special attention is paid to a ring, named Frame Synchronized Ring (FSR), which is developed for high speed switching and experimented as an ATM-switch. The study concentrates on analysing the transfer delay performance of the switching architectures to compare the rings with the other introduced switch structures (i.e. multidrop bus, crossbar, and multistage banyan network). The analysis is followed by some characteristics and experiments with the FSR.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128071760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546486
Winfried Grünewald, T. Ungerer
Multithreaded processors use a fast context switch to bridge latencies caused by memory accesses or by synchronization operations. In the block-multithreaded processor-called Rhamma-load/store, synchronization and execution operations of different threads of control are executed simultaneously by appropriate functional units. A fast context switch is performed, whenever a functional unit comes across an operation destined for another unit. Switching contexts on each load/store instruction sequence allows a much faster context switch in the execution unit than previously published designs do. The results show the potential of multithreading to spare expensive off-chip cache in a workstation environment. The load/store unit proves as the principal bottleneck. In particular the memory cycle time is performance critical. We show that multithreaded processors profit more than conventional RISC processors by a shorter memory cycle time.
{"title":"Towards extremely fast context switching in a block-multithreaded processor","authors":"Winfried Grünewald, T. Ungerer","doi":"10.1109/EURMIC.1996.546486","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546486","url":null,"abstract":"Multithreaded processors use a fast context switch to bridge latencies caused by memory accesses or by synchronization operations. In the block-multithreaded processor-called Rhamma-load/store, synchronization and execution operations of different threads of control are executed simultaneously by appropriate functional units. A fast context switch is performed, whenever a functional unit comes across an operation destined for another unit. Switching contexts on each load/store instruction sequence allows a much faster context switch in the execution unit than previously published designs do. The results show the potential of multithreading to spare expensive off-chip cache in a workstation environment. The load/store unit proves as the principal bottleneck. In particular the memory cycle time is performance critical. We show that multithreaded processors profit more than conventional RISC processors by a shorter memory cycle time.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132263843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546376
J. Hlavicka, S. Racek, Pavel Smrha
The paper presents an alternative approach to the formal specification and validation of distributed asynchronous algorithms. It begins with a syntactically correct description of the algorithm whose correctness is then to be validated. The validation of the algorithm is based on the process-oriented discrete simulation and permits a partial correctness validation of the algorithm implemented by a program. The suggested method enables to model independent activity of several processors (using pseudo-parallel processes) in simulation time and to model communication channels with defined time behavior and failure semantics. Using the approach it is easy to add other processes like model of system's environment, fault injector and state observer. The method is described with the aid of a simple C-based validation tool called C-Sim. The utilization of C-Sim requires only slight changes in C-coded implementation of the verified algorithm. An example of validation of distributed election algorithm with the presence of faults is presented.
{"title":"Functional validation of fault-tolerant asynchronous algorithms","authors":"J. Hlavicka, S. Racek, Pavel Smrha","doi":"10.1109/EURMIC.1996.546376","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546376","url":null,"abstract":"The paper presents an alternative approach to the formal specification and validation of distributed asynchronous algorithms. It begins with a syntactically correct description of the algorithm whose correctness is then to be validated. The validation of the algorithm is based on the process-oriented discrete simulation and permits a partial correctness validation of the algorithm implemented by a program. The suggested method enables to model independent activity of several processors (using pseudo-parallel processes) in simulation time and to model communication channels with defined time behavior and failure semantics. Using the approach it is easy to add other processes like model of system's environment, fault injector and state observer. The method is described with the aid of a simple C-based validation tool called C-Sim. The utilization of C-Sim requires only slight changes in C-coded implementation of the verified algorithm. An example of validation of distributed election algorithm with the presence of faults is presented.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131410531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546476
Johan Stärner, J. Adomat, Johan Furunäs, L. Lindh
Multiprocessor real-time systems are difficult to design to achieve predictable time behaviour. Our approach to simplification of the design and timing analysis is to use a scheduling coprocessor. We present the real-time services provided by the coprocessor as well as its implementation and timing. The scheduling coprocessor is a specially designed digital chip and is called the Real-Time Unit (RTU) with latency in the /spl mu/s domain.
{"title":"Real-time scheduling co-processor in hardware for single and multiprocessor systems","authors":"Johan Stärner, J. Adomat, Johan Furunäs, L. Lindh","doi":"10.1109/EURMIC.1996.546476","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546476","url":null,"abstract":"Multiprocessor real-time systems are difficult to design to achieve predictable time behaviour. Our approach to simplification of the design and timing analysis is to use a scheduling coprocessor. We present the real-time services provided by the coprocessor as well as its implementation and timing. The scheduling coprocessor is a specially designed digital chip and is called the Real-Time Unit (RTU) with latency in the /spl mu/s domain.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"14 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129953534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546377
M. Svéda
This paper presents principles of a rapid prototyping technique aimed at software design for embedded distributed systems. It introduces the principles of a local time concept supporting real-time distributed systems specifications: the developed local-time model stems both from counting asynchronous events and from modelling a physical generator of periodic events. The asynchronous specification language stemming from that model respects local timing in individual nodes while communication proceeds by message passing. The rapid prototyping makes use of (1) attribute grammars for language constructs specification and (2) textual macroprocessors or Prolog definite clause grammars for low-cost implementation. Executable specifications are supported by prototyping hardware components, real-time executives, and communication tasks.
{"title":"A prototyping technique with an asynchronous specification language","authors":"M. Svéda","doi":"10.1109/EURMIC.1996.546377","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546377","url":null,"abstract":"This paper presents principles of a rapid prototyping technique aimed at software design for embedded distributed systems. It introduces the principles of a local time concept supporting real-time distributed systems specifications: the developed local-time model stems both from counting asynchronous events and from modelling a physical generator of periodic events. The asynchronous specification language stemming from that model respects local timing in individual nodes while communication proceeds by message passing. The rapid prototyping makes use of (1) attribute grammars for language constructs specification and (2) textual macroprocessors or Prolog definite clause grammars for low-cost implementation. Executable specifications are supported by prototyping hardware components, real-time executives, and communication tasks.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"97 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124677128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546479
P. Zemánek
This paper treats data structures for image representation suitable for parallel algorithms for operations associated with databases of images. In our approach, images are converted from input pixel form to linear quadtrees that allow efficient storage of image data and that are suitable for a large number of operations, e.g. set operations such as union, intersection and difference. Set operations are essential for data retrieval in spatial database queries. All the algorithms mentioned above were developed on a MasPar SIMD parallel computer.
{"title":"Parallel set operations with visual data","authors":"P. Zemánek","doi":"10.1109/EURMIC.1996.546479","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546479","url":null,"abstract":"This paper treats data structures for image representation suitable for parallel algorithms for operations associated with databases of images. In our approach, images are converted from input pixel form to linear quadtrees that allow efficient storage of image data and that are suitable for a large number of operations, e.g. set operations such as union, intersection and difference. Set operations are essential for data retrieval in spatial database queries. All the algorithms mentioned above were developed on a MasPar SIMD parallel computer.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122286904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546487
C. Piguet, T. Schneider, J. Masgonty, C. Arm, S. Durand, M. Stegers
Low-power consumption has emerged as a very important issue in the design of integrated circuits in CMOS technology. The basic idea behind low-power RISC-like architectures is to reduce the number of executed instructions and clock cycles for the execution of a given task. In addition to these architectural issues, important power savings have been obtained by lowering the supply voltage, by pipelining, by adopting gated clock techniques as well as by using hierarchical memories.
{"title":"Low-power embedded microprocessor design","authors":"C. Piguet, T. Schneider, J. Masgonty, C. Arm, S. Durand, M. Stegers","doi":"10.1109/EURMIC.1996.546487","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546487","url":null,"abstract":"Low-power consumption has emerged as a very important issue in the design of integrated circuits in CMOS technology. The basic idea behind low-power RISC-like architectures is to reduce the number of executed instructions and clock cycles for the execution of a given task. In addition to these architectural issues, important power savings have been obtained by lowering the supply voltage, by pipelining, by adopting gated clock techniques as well as by using hierarchical memories.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114534833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546473
C. Dou
As a formal notation for telecommunication systems, SDL (Specification and Description Language, CCITT Z.100) has been widely used for modeling, analyzing, and simulations of communication protocols and/or real time systems. This paper first introduces a Timed-SDL to incorporate timing and probabilistic specifications into the original SDL functional descriptions. Then this Timed-SDL is used to specify, the formal models of communication protocols. These formal models also support validations and performance evaluations of communication protocols. The principles of the "observer" concept are adopted in the paper. The "observer" concept associates each SDL process in a system model with an observer process. Each observer process allows: (i) to date all the time stamps upon the occurrences of the inbound and outbound signals of the process being observed (Performance prospect); (ii) to describe the temporal properties that are needed to be validated on the process being observed (Validation prospect). By using the "observer" concept, both prospects of formal specification of communication protocols are investigated based on the Timed-SDL.
{"title":"Formal specification of communication protocols based on a Timed-SDL: validation and performance prospects","authors":"C. Dou","doi":"10.1109/EURMIC.1996.546473","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546473","url":null,"abstract":"As a formal notation for telecommunication systems, SDL (Specification and Description Language, CCITT Z.100) has been widely used for modeling, analyzing, and simulations of communication protocols and/or real time systems. This paper first introduces a Timed-SDL to incorporate timing and probabilistic specifications into the original SDL functional descriptions. Then this Timed-SDL is used to specify, the formal models of communication protocols. These formal models also support validations and performance evaluations of communication protocols. The principles of the \"observer\" concept are adopted in the paper. The \"observer\" concept associates each SDL process in a system model with an observer process. Each observer process allows: (i) to date all the time stamps upon the occurrences of the inbound and outbound signals of the process being observed (Performance prospect); (ii) to describe the temporal properties that are needed to be validated on the process being observed (Validation prospect). By using the \"observer\" concept, both prospects of formal specification of communication protocols are investigated based on the Timed-SDL.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129702657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546385
José M. García, A. Flores
Congestion in interconnection networks due to the presence of hot spots is an important and difficult problem that occurs in parallel machines. This problem has been studied in depth and different solutions for the case of multiprocessors with shared memory have been proposed. Current trends point towards the implementation of systems with physically distributed memory, either based on, message passing (multicomputers) or on a single shared memory address space (multiprocessors). Our paper is developed in this context. Up to now, proposals to improve the throughput of networks with hot-spots have focused on using virtual channels or adaptive algorithms. We present a novel solution based on reconfigurable networks. A reconfigurable network is one in which nodes can change their position depending on the communication pattern in order to diminish the congestion produced in the network and, therefore, increase its throughput. We studied this problem in two-dimensional k-ary n-cube networks using a deterministic routing algorithm and wormhole routing. In this paper the main features of a reconfigurable network are presented and the results obtained by simulation are shown. These results confirm that this technique is a very interesting one for systems with distributed memory, with applications to a great variety of problems.
{"title":"A novel approach to improve the performance of interconnection networks with hot-spots","authors":"José M. García, A. Flores","doi":"10.1109/EURMIC.1996.546385","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546385","url":null,"abstract":"Congestion in interconnection networks due to the presence of hot spots is an important and difficult problem that occurs in parallel machines. This problem has been studied in depth and different solutions for the case of multiprocessors with shared memory have been proposed. Current trends point towards the implementation of systems with physically distributed memory, either based on, message passing (multicomputers) or on a single shared memory address space (multiprocessors). Our paper is developed in this context. Up to now, proposals to improve the throughput of networks with hot-spots have focused on using virtual channels or adaptive algorithms. We present a novel solution based on reconfigurable networks. A reconfigurable network is one in which nodes can change their position depending on the communication pattern in order to diminish the congestion produced in the network and, therefore, increase its throughput. We studied this problem in two-dimensional k-ary n-cube networks using a deterministic routing algorithm and wormhole routing. In this paper the main features of a reconfigurable network are presented and the results obtained by simulation are shown. These results confirm that this technique is a very interesting one for systems with distributed memory, with applications to a great variety of problems.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130694235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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