Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546371
Karlheinz Agsteiner, D. Monjau, Sören Schulze
In this paper we present a new method to specify digital systems at the system level and to automatically transform a specification into a set of required system components from which in turn a complete system can be constructed using a knowledge-based configuration system. Our approach bases on an object-oriented domain model which captures all knowledge about a certain domain of systems. Throughout the paper we use the domain of RISC processors as an example. We show how the designer specifies systems based on a given domain model and how a specification is automatically mapped into a set of system functions.
{"title":"Automating system-level design: from specification to architecture","authors":"Karlheinz Agsteiner, D. Monjau, Sören Schulze","doi":"10.1109/EURMIC.1996.546371","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546371","url":null,"abstract":"In this paper we present a new method to specify digital systems at the system level and to automatically transform a specification into a set of required system components from which in turn a complete system can be constructed using a knowledge-based configuration system. Our approach bases on an object-oriented domain model which captures all knowledge about a certain domain of systems. Throughout the paper we use the domain of RISC processors as an example. We show how the designer specifies systems based on a given domain model and how a specification is automatically mapped into a set of system functions.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116971354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546369
R. Rauscher
At the core of contemporary VLSI designs is the task of determining and evaluating the set of decisions relevant for the particular design project. In many designs the set of design decisions is handled intuitively, and also the set of alternatives for each of the design decisions is strongly influenced by experiences from earlier designs. The paper discusses the list of design decisions under consideration, their alternatives, and the ordering of such a set of design decisions. A set of practical designs have been analyzed using the system introduced in the paper.
{"title":"A design assistant for scheduling of design decisions","authors":"R. Rauscher","doi":"10.1109/EURMIC.1996.546369","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546369","url":null,"abstract":"At the core of contemporary VLSI designs is the task of determining and evaluating the set of decisions relevant for the particular design project. In many designs the set of design decisions is handled intuitively, and also the set of alternatives for each of the design decisions is strongly influenced by experiences from earlier designs. The paper discusses the list of design decisions under consideration, their alternatives, and the ordering of such a set of design decisions. A set of practical designs have been analyzed using the system introduced in the paper.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114909061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546457
J. Cunha, J. G. Silva
Memory protection has been widely recognized as an effective concurrent error detection method. Some of the studies made show that its effectiveness changes as the percentage of unused memory grows, since the probability of a wrong address falling on the unused zone also grows. In this paper, we follow that hint, and try to determine how better does the detection capability of protected memory get, when the protection boundaries are dynamically changed to encompass just the code of the function being executed. We implemented this method on a VME standard board, monitoring a commercial MC68000-based system. The system was tested by means of physical injection of about 25000 faults. Experimental results revealed that this mechanism can typically detect more than 80% of the faults, improving in about 5% the results from the traditional mechanisms. We also verified that only around 30% of the undetected faults induced a system failure.
{"title":"DELFIM: error detection by thin memory protection","authors":"J. Cunha, J. G. Silva","doi":"10.1109/EURMIC.1996.546457","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546457","url":null,"abstract":"Memory protection has been widely recognized as an effective concurrent error detection method. Some of the studies made show that its effectiveness changes as the percentage of unused memory grows, since the probability of a wrong address falling on the unused zone also grows. In this paper, we follow that hint, and try to determine how better does the detection capability of protected memory get, when the protection boundaries are dynamically changed to encompass just the code of the function being executed. We implemented this method on a VME standard board, monitoring a commercial MC68000-based system. The system was tested by means of physical injection of about 25000 faults. Experimental results revealed that this mechanism can typically detect more than 80% of the faults, improving in about 5% the results from the traditional mechanisms. We also verified that only around 30% of the undetected faults induced a system failure.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126856695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546466
Morten Kjelsø, M. Gooch, S. Jones
In this paper we show that hardware main memory data compression is both feasible and worthwhile. We demonstrate that paging due to insufficient memory resources can reduce system performance several fold, and argue that hardware memory compression can eliminate this paging hence providing a substantial performance improvement. We describe the design and implementation of a novel compression method, the X-Match algorithm, which is efficient at compressing small blocks of data and suitable for high-speed hardware implementation. Our experimental investigation shows that on average the X-Match algorithm doubles the memory capacity for commonly used Unix applications. Furthermore, the substantial impact such memory compression has on overall system performance is demonstrated.
{"title":"Design and performance of a main memory hardware data compressor","authors":"Morten Kjelsø, M. Gooch, S. Jones","doi":"10.1109/EURMIC.1996.546466","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546466","url":null,"abstract":"In this paper we show that hardware main memory data compression is both feasible and worthwhile. We demonstrate that paging due to insufficient memory resources can reduce system performance several fold, and argue that hardware memory compression can eliminate this paging hence providing a substantial performance improvement. We describe the design and implementation of a novel compression method, the X-Match algorithm, which is efficient at compressing small blocks of data and suitable for high-speed hardware implementation. Our experimental investigation shows that on average the X-Match algorithm doubles the memory capacity for commonly used Unix applications. Furthermore, the substantial impact such memory compression has on overall system performance is demonstrated.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121669415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546381
Peter Grün, P. Eles, K. Kuchcinski, Zebo Peng
This paper presents an approach to automatic parallelization of an internal design representation for high-level synthesis of hardware structures. It concentrates on aspects which are specific to the parallelization of the Petri net based representation used by our design environment. Preservation of safeness and conflict freeness of the internal representation during parallelization are basic requirements for the correctness of the resulted hardware. A hierarchical Petri net structure has been used as an intermediate representation during parallelization, which results in an important reduction of the complexity of the parallelization process. Experimental results demonstrate the efficiency our approach in the context of the CAMAD high-level synthesis system.
{"title":"Automatic parallelization of a Petri net-based design representation for high-level synthesis","authors":"Peter Grün, P. Eles, K. Kuchcinski, Zebo Peng","doi":"10.1109/EURMIC.1996.546381","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546381","url":null,"abstract":"This paper presents an approach to automatic parallelization of an internal design representation for high-level synthesis of hardware structures. It concentrates on aspects which are specific to the parallelization of the Petri net based representation used by our design environment. Preservation of safeness and conflict freeness of the internal representation during parallelization are basic requirements for the correctness of the resulted hardware. A hierarchical Petri net structure has been used as an intermediate representation during parallelization, which results in an important reduction of the complexity of the parallelization process. Experimental results demonstrate the efficiency our approach in the context of the CAMAD high-level synthesis system.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121934510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546471
H. Choi, Jaesoo Yoo, Ok-Bae Chang
Recently, some research on control service models for distributed multimedia objects have been made based on socket. However, the existing socket-based control service models are too primitive to provide interconnectivity among the open distributed systems. In this paper, we propose a new control service model based on CORBA, called DIMCA/ORB, for the distributed multimedia objects that solves the problems of the existing socket-based models. The proposed DIMCA/ORB provides real-time bindings, Quality of Service (QoS), and negotiation between objects for the transfer of multimedia data. It also supports an effective solution for the integration of heterogeneous components in an open distributed environment.
{"title":"A new control service model based on CORBA for distributed multimedia objects","authors":"H. Choi, Jaesoo Yoo, Ok-Bae Chang","doi":"10.1109/EURMIC.1996.546471","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546471","url":null,"abstract":"Recently, some research on control service models for distributed multimedia objects have been made based on socket. However, the existing socket-based control service models are too primitive to provide interconnectivity among the open distributed systems. In this paper, we propose a new control service model based on CORBA, called DIMCA/ORB, for the distributed multimedia objects that solves the problems of the existing socket-based models. The proposed DIMCA/ORB provides real-time bindings, Quality of Service (QoS), and negotiation between objects for the transfer of multimedia data. It also supports an effective solution for the integration of heterogeneous components in an open distributed environment.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126255692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546461
T. Bartha
System-level fault diagnosis is a methodology to identify, the failed components in a multiprocessor system. The traditional approach to system-level diagnosis does not take into consideration many important aspects of modern multiprocessor architectures. This paper examines a special class of multiprocessors, called massively parallel computers. As a practical example, the Parsytec GCel system is presented. The paper describes a new method developed for the Parsytec GCel, called local information diagnosis. The diagnostic algorithm is based on the generalized test invalidation model, therefore it is applicable to a wide range of systems, including inhomogeneous ones. Due to the employed syndrome decoding mechanism, the space and computational complexity of the algorithm is also smaller than in conventional methods.
{"title":"Effective approximate fault diagnosis of systems with inhomogeneous test invalidation","authors":"T. Bartha","doi":"10.1109/EURMIC.1996.546461","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546461","url":null,"abstract":"System-level fault diagnosis is a methodology to identify, the failed components in a multiprocessor system. The traditional approach to system-level diagnosis does not take into consideration many important aspects of modern multiprocessor architectures. This paper examines a special class of multiprocessors, called massively parallel computers. As a practical example, the Parsytec GCel system is presented. The paper describes a new method developed for the Parsytec GCel, called local information diagnosis. The diagnostic algorithm is based on the generalized test invalidation model, therefore it is applicable to a wide range of systems, including inhomogeneous ones. Due to the employed syndrome decoding mechanism, the space and computational complexity of the algorithm is also smaller than in conventional methods.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130580209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546372
D. D. Vito, Olivier Michel
We describe in this paper an effective code generation scheme for a declarative data-parallel language targeted towards sequential, vector or SIMD architectures. The code generation is produced from the declarative data-parallel language 8 1/2, a language that relies on the notions of stream and collection in a high-level declarative framework. We first describe the language and its specificities focusing on data-parallelism. Then we present two optimizations for the generated code: the sharing of common control expressions and the optimization of delay copies. Next, we give some elements for the evaluation of the generated code. As a conclusion, we recall the overall effectiveness of the execution scheme and draw some plans for the future.
{"title":"Effective SIMD code generation for the high-level declarative data-parallel language 8 1/2","authors":"D. D. Vito, Olivier Michel","doi":"10.1109/EURMIC.1996.546372","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546372","url":null,"abstract":"We describe in this paper an effective code generation scheme for a declarative data-parallel language targeted towards sequential, vector or SIMD architectures. The code generation is produced from the declarative data-parallel language 8 1/2, a language that relies on the notions of stream and collection in a high-level declarative framework. We first describe the language and its specificities focusing on data-parallelism. Then we present two optimizations for the generated code: the sharing of common control expressions and the optimization of delay copies. Next, we give some elements for the evaluation of the generated code. As a conclusion, we recall the overall effectiveness of the execution scheme and draw some plans for the future.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"445 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116721881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546360
L. Józwiak, S. Ong
The importance of the information processing system's market, technology revolution, explosion of new market competitors, high requirements of application oriented embedded systems, and many other factors create a situation in which the quality-driven design is becoming a necessity. The aim of this paper is to provide and discuss some theoretical and methodological foundations of the quality-driven decision making for design. In the paper a new definition of quality is proposed and the quality-driven design paradigm is introduced. Subsequently, an original methodology of the design space exploration is proposed; specifically, the methods for the construction and analysis of the decision models. A number of ideas presented in the paper have already been applied with success for solving various design problems. Currently, the methodology presented is being applied to the hardware/software partitioning.
{"title":"Quality-driven decision making methodology for system-level design","authors":"L. Józwiak, S. Ong","doi":"10.1109/EURMIC.1996.546360","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546360","url":null,"abstract":"The importance of the information processing system's market, technology revolution, explosion of new market competitors, high requirements of application oriented embedded systems, and many other factors create a situation in which the quality-driven design is becoming a necessity. The aim of this paper is to provide and discuss some theoretical and methodological foundations of the quality-driven decision making for design. In the paper a new definition of quality is proposed and the quality-driven design paradigm is introduced. Subsequently, an original methodology of the design space exploration is proposed; specifically, the methods for the construction and analysis of the decision models. A number of ideas presented in the paper have already been applied with success for solving various design problems. Currently, the methodology presented is being applied to the hardware/software partitioning.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134351783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546460
O. Benkahla, F. Chevassu, B. Remy, C. Robach
This paper presents an evaluation tool, SimDiag, developed in order to allow quantitative analysis of distributed diagnosis algorithms. This tool uses a process-based model for simulating diagnosis algorithms. It allows the evaluation of many interesting diagnosis performance characteristics such as diagnosis latency, total number of generated tests and total number of transmitted messages. Four algorithms are evaluated using SimDiag. Three of them use a static testing strategy whereas the other is based on an adaptive strategy. Presented results concern two aspects. First, an evaluation of the effect of increasing diagnosis functionalities is performed. Then, a practical comparison of used testing strategies is provided.
{"title":"Performance evaluation of testing strategies in parallel systems","authors":"O. Benkahla, F. Chevassu, B. Remy, C. Robach","doi":"10.1109/EURMIC.1996.546460","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546460","url":null,"abstract":"This paper presents an evaluation tool, SimDiag, developed in order to allow quantitative analysis of distributed diagnosis algorithms. This tool uses a process-based model for simulating diagnosis algorithms. It allows the evaluation of many interesting diagnosis performance characteristics such as diagnosis latency, total number of generated tests and total number of transmitted messages. Four algorithms are evaluated using SimDiag. Three of them use a static testing strategy whereas the other is based on an adaptive strategy. Presented results concern two aspects. First, an evaluation of the effect of increasing diagnosis functionalities is performed. Then, a practical comparison of used testing strategies is provided.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116577139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：