Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546492
R. Collins, G. Steven
It is increasingly accepted that superscalar processors can only achieve their full performance potential through compile-time instruction scheduling. The paper presents preliminary performance results using a conditional group scheduler which targets the HSA processor model developed at the University of Hertfordshire. In particular, we show that guarded instruction execution improves performance by allowing the processor to squash instructions in the instruction buffer before they are issued to functional units and enables the scheduler to delete a significant number of branch instructions.
{"title":"Instruction scheduling for a superscalar architecture","authors":"R. Collins, G. Steven","doi":"10.1109/EURMIC.1996.546492","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546492","url":null,"abstract":"It is increasingly accepted that superscalar processors can only achieve their full performance potential through compile-time instruction scheduling. The paper presents preliminary performance results using a conditional group scheduler which targets the HSA processor model developed at the University of Hertfordshire. In particular, we show that guarded instruction execution improves performance by allowing the processor to squash instructions in the instruction buffer before they are issued to functional units and enables the scheduler to delete a significant number of branch instructions.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124852843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546373
G. G. C. Neto, R. Lima, R. Lins, André L. M. Santos
Benchmarking implementations is fundamental to allow analysing performance amongst different platforms. The choice of a benchmark that makes possible a reliable and fair comparison of a particular aspect is a difficult task, however. The Pseudoknot benchmark is a floating-point intensive application taken from molecular biology which was used to compare the compile-time and execution-time performance of over 25 different implementations of functional languages. Amongst those implementations was /spl Gamma/CMC, an abstract machine for efficient implementation of lazy functional languages. /spl Gamma/CMC pioneered the transference of the control of the execution flow to C, as much as possible, to take advantage of the extremely low cost of procedure calls in modern RISC architectures. /spl Gamma/CMC was amongst the machines that presented good Pseudoknot figures, although it did not use some of the sophisticated optimisations of most of the other implementations. The experience of implementing Pseudoknot in /spl Gamma/CMC was most valuable in providing insights for new ways in optimising it. This paper describes several optimisations introduced to /spl Gamma/CMC which bring a better Pseudoknot performance.
{"title":"Optimising Pseudoknot in /spl Gamma/CMC","authors":"G. G. C. Neto, R. Lima, R. Lins, André L. M. Santos","doi":"10.1109/EURMIC.1996.546373","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546373","url":null,"abstract":"Benchmarking implementations is fundamental to allow analysing performance amongst different platforms. The choice of a benchmark that makes possible a reliable and fair comparison of a particular aspect is a difficult task, however. The Pseudoknot benchmark is a floating-point intensive application taken from molecular biology which was used to compare the compile-time and execution-time performance of over 25 different implementations of functional languages. Amongst those implementations was /spl Gamma/CMC, an abstract machine for efficient implementation of lazy functional languages. /spl Gamma/CMC pioneered the transference of the control of the execution flow to C, as much as possible, to take advantage of the extremely low cost of procedure calls in modern RISC architectures. /spl Gamma/CMC was amongst the machines that presented good Pseudoknot figures, although it did not use some of the sophisticated optimisations of most of the other implementations. The experience of implementing Pseudoknot in /spl Gamma/CMC was most valuable in providing insights for new ways in optimising it. This paper describes several optimisations introduced to /spl Gamma/CMC which bring a better Pseudoknot performance.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125560737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546378
O. Hammerschmidt, T. Doersam
The amount of hardware and especially software for systems in automation and control is still increasing. Faced with short product life cycles, the need for appropriate design methods for distributed real-time systems in this application field arises. In order to handle the complexity of software for automation systems of larger scale in manufacturing nowadays procedural-oriented and object-oriented methods are used. Within the latter alternative we developed an object- and service-oriented approach to cope with problems of complexity and to ease and accelerate the software design process. In this paper we present a service-based concept, give a possible definition of basic services and discuss experiences made in an application example of a three-fingered robot gripper.
{"title":"Software engineering in control using objects and services","authors":"O. Hammerschmidt, T. Doersam","doi":"10.1109/EURMIC.1996.546378","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546378","url":null,"abstract":"The amount of hardware and especially software for systems in automation and control is still increasing. Faced with short product life cycles, the need for appropriate design methods for distributed real-time systems in this application field arises. In order to handle the complexity of software for automation systems of larger scale in manufacturing nowadays procedural-oriented and object-oriented methods are used. Within the latter alternative we developed an object- and service-oriented approach to cope with problems of complexity and to ease and accelerate the software design process. In this paper we present a service-based concept, give a possible definition of basic services and discuss experiences made in an application example of a three-fingered robot gripper.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"53 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127335117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546362
G. Hayek, Yves Le Traon, C. Robach
In this paper, a test-based hardware/software partitioning approach for co-design specifications is presented. The testability of a hierarchical specified co-design system is discussed and an estimate is proposed to evaluate the system testing cost. It depends on the hardware/software testing cost values for each unit-level component. These values are provided by a mutation-test approach applied for testing both software and hardware unit-level implementations. Results have shown that this approach provides a new helpful partitioning criterion which can be used with other already known criteria. A real case study provided by Aerospatiale illustrates this testing cost oriented partitioning.
{"title":"Considering test economics in the process of hardware/software partitioning","authors":"G. Hayek, Yves Le Traon, C. Robach","doi":"10.1109/EURMIC.1996.546362","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546362","url":null,"abstract":"In this paper, a test-based hardware/software partitioning approach for co-design specifications is presented. The testability of a hierarchical specified co-design system is discussed and an estimate is proposed to evaluate the system testing cost. It depends on the hardware/software testing cost values for each unit-level component. These values are provided by a mutation-test approach applied for testing both software and hardware unit-level implementations. Results have shown that this approach provides a new helpful partitioning criterion which can be used with other already known criteria. A real case study provided by Aerospatiale illustrates this testing cost oriented partitioning.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128847126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546398
J. Sosnowski, A. Kusmierczyk
The paper deals with the problem of testing microprocessors in the system environment. We discuss two approaches to testing microprocessors: deterministic and pseudorandom. They are related to Intel 80/spl times/86 processors. Many drawbacks of the deterministic approach can be overcome with pseudorandom tests. However developing pseudorandom test programs we face some other problems. The paper shows how to combine the two approaches.
{"title":"Pseudorandom versus deterministic testing of Intel 80/spl times/86 processors","authors":"J. Sosnowski, A. Kusmierczyk","doi":"10.1109/EURMIC.1996.546398","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546398","url":null,"abstract":"The paper deals with the problem of testing microprocessors in the system environment. We discuss two approaches to testing microprocessors: deterministic and pseudorandom. They are related to Intel 80/spl times/86 processors. Many drawbacks of the deterministic approach can be overcome with pseudorandom tests. However developing pseudorandom test programs we face some other problems. The paper shows how to combine the two approaches.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127053691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546396
I. Majzik
Signature based error detection techniques (e.g. the application of watchdog processors) can be easily extended to support software debugging. The run-time sequence of signatures is stored in an extension of the traditional checker. As the signatures identify the states of the program, a trace of the statements executed by the checked processor is available. The signature buffer can be efficiently utilized if the signature sequence is compressed. In the paper, two real-time compression methods are presented and compared. The general method uses predefined dictionaries, while the other one utilizes the structural information encoded in the signatures.
{"title":"Software monitoring and debugging using compressed signature sequences","authors":"I. Majzik","doi":"10.1109/EURMIC.1996.546396","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546396","url":null,"abstract":"Signature based error detection techniques (e.g. the application of watchdog processors) can be easily extended to support software debugging. The run-time sequence of signatures is stored in an extension of the traditional checker. As the signatures identify the states of the program, a trace of the statements executed by the checked processor is available. The signature buffer can be efficiently utilized if the signature sequence is compressed. In the paper, two real-time compression methods are presented and compared. The general method uses predefined dictionaries, while the other one utilizes the structural information encoded in the signatures.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116593319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546493
E. Filho, Edil S. T. Fernandes, A. Wolfe
New techniques are increasing the degree of instruction-level parallelism exploited by processors. Recent superscalar implementations include multiple functional units, allowing the parallel execution of several instructions from the same application program. The trend towards an expansion of the number of hardware resources is likely to continue in future superscalar designs, and in order to maximize the processor throughput, the computational load must be balanced among these resources by the dynamic instruction-issuing algorithm. We investigate the effect on performance caused by the way instructions are distributed among the functional units of superscalar processors. Our results show that a performance gain of up to 38% can be obtained when the instructions are evenly distributed among the functional units.
{"title":"Load balancing in superscalar architectures","authors":"E. Filho, Edil S. T. Fernandes, A. Wolfe","doi":"10.1109/EURMIC.1996.546493","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546493","url":null,"abstract":"New techniques are increasing the degree of instruction-level parallelism exploited by processors. Recent superscalar implementations include multiple functional units, allowing the parallel execution of several instructions from the same application program. The trend towards an expansion of the number of hardware resources is likely to continue in future superscalar designs, and in order to maximize the processor throughput, the computational load must be balanced among these resources by the dynamic instruction-issuing algorithm. We investigate the effect on performance caused by the way instructions are distributed among the functional units of superscalar processors. Our results show that a performance gain of up to 38% can be obtained when the instructions are evenly distributed among the functional units.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116910139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546478
V. Tchoumatchenko, T. Vassileva, P. Gurov
We present an FPGA implementation of a non-restoring integer square-root algorithm, that uses estimates for result-digit selection and radix-2 redundant addition in recurrence. On-the-fly conversion of the result-digit and signed-digit adder/substractor are used to simplify the hardware realization. Modifications of the equations for th optimal use of Xilinx CLBs, and the necessary CLB resources for different bit-length calculations are outlined, for the XC3000 family.
{"title":"A FPGA based square-root coprocessor","authors":"V. Tchoumatchenko, T. Vassileva, P. Gurov","doi":"10.1109/EURMIC.1996.546478","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546478","url":null,"abstract":"We present an FPGA implementation of a non-restoring integer square-root algorithm, that uses estimates for result-digit selection and radix-2 redundant addition in recurrence. On-the-fly conversion of the result-digit and signed-digit adder/substractor are used to simplify the hardware realization. Modifications of the equations for th optimal use of Xilinx CLBs, and the necessary CLB resources for different bit-length calculations are outlined, for the XC3000 family.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115027627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546384
R. Giorgi, C. Prete, L. Ricciardi, G. Prina
This paper describes a hybrid methodology (based on both actual and synthetic reference streams) to produce traces representing significant complete workloads. By means of a software approach, we generate traces that include both user and kernel references starting from source traces containing only user references. We consider the aspects of kernel that have a deeper impact on the multiprocessor performance by (i) simulating the process scheduling and the virtual-to-physical address translation, and (ii) stochastically modeling the kernel reference stream. The target system of our study is a shared-bus shared-memory multiprocessor used as a general-purpose machine with a multitasking operating system.
{"title":"A hybrid approach to trace generation for performance evaluation of shared-bus multiprocessors","authors":"R. Giorgi, C. Prete, L. Ricciardi, G. Prina","doi":"10.1109/EURMIC.1996.546384","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546384","url":null,"abstract":"This paper describes a hybrid methodology (based on both actual and synthetic reference streams) to produce traces representing significant complete workloads. By means of a software approach, we generate traces that include both user and kernel references starting from source traces containing only user references. We consider the aspects of kernel that have a deeper impact on the multiprocessor performance by (i) simulating the process scheduling and the virtual-to-physical address translation, and (ii) stochastically modeling the kernel reference stream. The target system of our study is a shared-bus shared-memory multiprocessor used as a general-purpose machine with a multitasking operating system.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-09-02DOI: 10.1109/EURMIC.1996.546386
L. Borzemski, A. Kieda
We present a load balancing system for the network of Windows NT computers. Tasks can arrive at any computer in the network and can be distributed transparently over the network. The system can be seen as a networked Windows NT based metacomputer platform. As the testbeds we present the computational experiments performed for the needs of the multistage recognition.
{"title":"A load balancing system for Windows NT networks","authors":"L. Borzemski, A. Kieda","doi":"10.1109/EURMIC.1996.546386","DOIUrl":"https://doi.org/10.1109/EURMIC.1996.546386","url":null,"abstract":"We present a load balancing system for the network of Windows NT computers. Tasks can arrive at any computer in the network and can be distributed transparently over the network. The system can be seen as a networked Windows NT based metacomputer platform. As the testbeds we present the computational experiments performed for the needs of the multistage recognition.","PeriodicalId":311520,"journal":{"name":"Proceedings of EUROMICRO 96. 22nd Euromicro Conference. Beyond 2000: Hardware and Software Design Strategies","volume":"127 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128802445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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