Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344431
Y. G. G. D. Costa, José Antônio Gomes de Lima, Guilherme Navarro
As the technology advances, space imaging systems use equipment of increasing resolutions. Hence, it is necessary to ensure that this great quantity of data arrives at its destination reliably. Among some variables involved, data compression plays an important role to accomplish this requirement. In this context, this paper proposes a digital hardware approach of a low complexity satellite image lossless compressor based on prediction and Golomb-Rice coding, which has achieved excellent results considering hardware and compression performance. In order to validate and analyze the compressor, a functional verification and FPGA prototyping methodology were followed. Given an image set from Brazilian's National Institute for Space Research (INPE, in Portuguese acronyms), its results on FPGA show that this compressor achieves compression ratio around 3.4, comparable value to related works in this area, and throughput of 28 MPixel/s (224 Mbit/s). Taking advantage of images nature, its compression can be parallelized through simultaneous multi-cores compressors. For example, using 5 cores, this work is able to compress those images in a rate of 142 MPixel/s (1.1 Gbit/s). All these features make it useful and effective as a current remote sensing imaging system.
{"title":"A low complexity lossless data compressor IP-core for satellite images","authors":"Y. G. G. D. Costa, José Antônio Gomes de Lima, Guilherme Navarro","doi":"10.1109/SBCCI.2012.6344431","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344431","url":null,"abstract":"As the technology advances, space imaging systems use equipment of increasing resolutions. Hence, it is necessary to ensure that this great quantity of data arrives at its destination reliably. Among some variables involved, data compression plays an important role to accomplish this requirement. In this context, this paper proposes a digital hardware approach of a low complexity satellite image lossless compressor based on prediction and Golomb-Rice coding, which has achieved excellent results considering hardware and compression performance. In order to validate and analyze the compressor, a functional verification and FPGA prototyping methodology were followed. Given an image set from Brazilian's National Institute for Space Research (INPE, in Portuguese acronyms), its results on FPGA show that this compressor achieves compression ratio around 3.4, comparable value to related works in this area, and throughput of 28 MPixel/s (224 Mbit/s). Taking advantage of images nature, its compression can be parallelized through simultaneous multi-cores compressors. For example, using 5 cores, this work is able to compress those images in a rate of 142 MPixel/s (1.1 Gbit/s). All these features make it useful and effective as a current remote sensing imaging system.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127844328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344429
T. Rosa, Vivian Larrea, Ney Laert Vilar Calazans, F. Moraes
The use of power management techniques is mandatory in embedded devices, which must provide high performance with low energy consumption. Due to the high variability present in the applications workload executed by these devices, this management should be executed dynamically. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved to be useful in several scenarios to save energy. Nonetheless, due to technology scaling that limits the voltage variation and slow response of the DVFS schemes, the use of such technique may become inadequate. As alternative, the use of dynamic frequency scaling (DFS) may provide a good trade-off between power savings and power overhead. This paper proposes a distributed DFS scheme for NoC-based MPSoCs. Both NoC and PEs have an individual controlling scheme. The DFS scheme for PEs takes into account its computation and communication load to dynamically change the operating frequency. In the NoC, the DFS controller uses packet information to decide the router operating frequency. Real and synthetic applications were used to evaluate the proposed scheme. Results show that the number of executed instructions is reduced up to 41%, with an execution time overhead up to 18%. The power dissipation is reduced in PEs up to 26% and in the NoC up to 76%.
{"title":"Power consumption reduction in MPSoCs through DFS","authors":"T. Rosa, Vivian Larrea, Ney Laert Vilar Calazans, F. Moraes","doi":"10.1109/SBCCI.2012.6344429","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344429","url":null,"abstract":"The use of power management techniques is mandatory in embedded devices, which must provide high performance with low energy consumption. Due to the high variability present in the applications workload executed by these devices, this management should be executed dynamically. The use of traditional dynamic voltage and frequency scaling (DVFS) techniques proved to be useful in several scenarios to save energy. Nonetheless, due to technology scaling that limits the voltage variation and slow response of the DVFS schemes, the use of such technique may become inadequate. As alternative, the use of dynamic frequency scaling (DFS) may provide a good trade-off between power savings and power overhead. This paper proposes a distributed DFS scheme for NoC-based MPSoCs. Both NoC and PEs have an individual controlling scheme. The DFS scheme for PEs takes into account its computation and communication load to dynamically change the operating frequency. In the NoC, the DFS controller uses packet information to decide the router operating frequency. Real and synthetic applications were used to evaluate the proposed scheme. Results show that the number of executed instructions is reduced up to 41%, with an execution time overhead up to 18%. The power dissipation is reduced in PEs up to 26% and in the NoC up to 76%.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121295890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344430
P. S. B. Nascimento, F. Neves, H. Souza, M. A. O. Domingues
Very important fields for utilization of FPGA technology are industrial applications such as power converters, renewable energy systems, uninterruptible power supplies, active power filters, dynamic voltage restorers and power systems protection. Many of these applications require the detection of three-phase signals characteristics. Generally, these techniques are implemented in DSP devices, with the execution time limited by sample rates of input signals. FPGA implementation results in several advantages. In this paper, an FPGA design flow for industrial digital signal processing is proposed. The first contribution is a metric for comparison between FPGA devices and DSP devices. This metric estimates the quality of implementations based on the efficiency of resources utilization in both technologies. A case study of a magnitude and phase angle detector of the fundamental-frequency positive-sequence component of a three-phase signal is presented. As a second contribution, a proposed FPGA-controller architecture is presented. For validation of the proposed metric, the advantages and possibilities of the use of FPGA in the case study are demonstrated in comparison with the DSP, in terms of the efficiency of resource usage metric, which is based on the capacity for increasing the application algorithms complexity and capacity of exploring the parallelism of operations, allowing for a much shorter execution time.
{"title":"FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector","authors":"P. S. B. Nascimento, F. Neves, H. Souza, M. A. O. Domingues","doi":"10.1109/SBCCI.2012.6344430","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344430","url":null,"abstract":"Very important fields for utilization of FPGA technology are industrial applications such as power converters, renewable energy systems, uninterruptible power supplies, active power filters, dynamic voltage restorers and power systems protection. Many of these applications require the detection of three-phase signals characteristics. Generally, these techniques are implemented in DSP devices, with the execution time limited by sample rates of input signals. FPGA implementation results in several advantages. In this paper, an FPGA design flow for industrial digital signal processing is proposed. The first contribution is a metric for comparison between FPGA devices and DSP devices. This metric estimates the quality of implementations based on the efficiency of resources utilization in both technologies. A case study of a magnitude and phase angle detector of the fundamental-frequency positive-sequence component of a three-phase signal is presented. As a second contribution, a proposed FPGA-controller architecture is presented. For validation of the proposed metric, the advantages and possibilities of the use of FPGA in the case study are demonstrated in comparison with the DSP, in terms of the efficiency of resource usage metric, which is based on the capacity for increasing the application algorithms complexity and capacity of exploring the parallelism of operations, allowing for a much shorter execution time.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132655907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344448
H. Cubas, J. Soares
The present paper reports a top-down design for the design of a Low Power Sigma-Delta Modulator, going from determining the architecture and specifications to the transistor-level design. A Multi-bit CIFF (Chain of Integrators with Feed Forward) implementation was chosen for low power consumption. The Sigma-Delta Modulator is designed in the 0.18 μm IBM CMOS technology and has a 98dB Dynamic Range, 2 Vpp Full Scale, and 20-20 kHz input bandwidth (Audio Bandwidth). The final circuit reached a simulated power consumption of 2.77 mW (Cadence), for 1.8 V power supply.
本文报道了一种低功耗Sigma-Delta调制器的自顶向下设计，从确定结构和规格到晶体管级设计。为了降低功耗，我们选择了多比特的前馈集成商链(Chain of Integrators with Feed Forward)实现。Sigma-Delta调制器采用0.18 μm IBM CMOS技术设计，动态范围为98dB，满量程为2 Vpp，输入带宽为20-20 kHz(音频带宽)。在1.8 V电源下，最终电路达到了2.77 mW (Cadence)的模拟功耗。
{"title":"Top-down design for Low power Multi-bit Sigma-Delta Modulator","authors":"H. Cubas, J. Soares","doi":"10.1109/SBCCI.2012.6344448","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344448","url":null,"abstract":"The present paper reports a top-down design for the design of a Low Power Sigma-Delta Modulator, going from determining the architecture and specifications to the transistor-level design. A Multi-bit CIFF (Chain of Integrators with Feed Forward) implementation was chosen for low power consumption. The Sigma-Delta Modulator is designed in the 0.18 μm IBM CMOS technology and has a 98dB Dynamic Range, 2 Vpp Full Scale, and 20-20 kHz input bandwidth (Audio Bandwidth). The final circuit reached a simulated power consumption of 2.77 mW (Cadence), for 1.8 V power supply.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132326603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344449
Thiago N. C. Cardoso, E. Barros, B. Prado, Andre Aziz
The electronic devices market demands a larger amount of functionality integrated into a single product. To address this demand, the industry migrated to solutions based on processors, increasing the software role in the systems. However, processor-based solutions raises the design complexity due to the complexity of Hardware-dependent Software (HdS). To cope with this complexity, the virtual platforms approach is applied, in which the whole system is modeled in order to reduce the design time. Nowadays, much of this work is manually performed, synthesizing all structures and behavior required in a system level design language (SLDL). However, with the increasing systems complexity, it is becoming impractical to continue performing this synthesis manually. In the last decade, several studies have addressed the synthesis of software components from descriptions in SLDLs and recently in the Unified Modeling Language (UML). Although significant automation has been obtained, there are limitations in the abstraction achieved. In order to raise the abstraction of the description, the UML-ESL profile was proposed to abstract the communication structure, with a synthesis technique for communication between software and hardware interfaces. This work presents a technique to synthesize the multitasking support and the communication between software components of the system from a description in UML-ESL for virtual platform simulation. The results obtained showed up to 60% decrease in the amount of code manually written.
{"title":"Communication software synthesis from UML-ESL models","authors":"Thiago N. C. Cardoso, E. Barros, B. Prado, Andre Aziz","doi":"10.1109/SBCCI.2012.6344449","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344449","url":null,"abstract":"The electronic devices market demands a larger amount of functionality integrated into a single product. To address this demand, the industry migrated to solutions based on processors, increasing the software role in the systems. However, processor-based solutions raises the design complexity due to the complexity of Hardware-dependent Software (HdS). To cope with this complexity, the virtual platforms approach is applied, in which the whole system is modeled in order to reduce the design time. Nowadays, much of this work is manually performed, synthesizing all structures and behavior required in a system level design language (SLDL). However, with the increasing systems complexity, it is becoming impractical to continue performing this synthesis manually. In the last decade, several studies have addressed the synthesis of software components from descriptions in SLDLs and recently in the Unified Modeling Language (UML). Although significant automation has been obtained, there are limitations in the abstraction achieved. In order to raise the abstraction of the description, the UML-ESL profile was proposed to abstract the communication structure, with a synthesis technique for communication between software and hardware interfaces. This work presents a technique to synthesize the multitasking support and the communication between software components of the system from a description in UML-ESL for virtual platform simulation. The results obtained showed up to 60% decrease in the amount of code manually written.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128872791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344453
J. Y. Mori, C. Llanos, P. Berger
Intending to improve design trade offs in image processing architectures this work presents some kernel analysis for convolution-based image filtering. Some well-known filter kernels have been analyzed in order to identify symmetries and to allow the development of alternative architectures that can contribute to reduce power consumption and/or FPGA resources, maintaining or improving the overall system throughput. The separable kernel technique is also analyzed, and two architectures were developed and tested. Additionally, a technique based on overlapping kernels have been developed, analyzed and tested. All architectures were implemented and synthesized using Altera Quartus II EDA software and prototyped in four real-time image processing platforms. These platforms are composed by a CMOS camera, four Terasic FPGA development kits (with Altera devices) and an LCD. Synthesis, simulations and real-time results show the suitability of such architectures for this kind of design trade off.
为了改善图像处理架构的设计权衡，本工作提出了一些基于卷积的图像滤波的核分析。为了识别对称性，并允许开发替代架构，从而有助于降低功耗和/或FPGA资源，维持或提高整体系统吞吐量，对一些知名的滤波器内核进行了分析。分析了可分离核技术，开发了两种体系结构并进行了测试。此外，还开发了一种基于重叠核的技术，并对其进行了分析和测试。所有架构都使用Altera Quartus II EDA软件实现和合成，并在四个实时图像处理平台上进行原型设计。这些平台由一个CMOS相机、四个Terasic FPGA开发套件(带有Altera器件)和一个LCD组成。综合、仿真和实时结果表明，这种架构适合这种设计权衡。
{"title":"Kernel analysis for architecture design trade off in convolution-based image filtering","authors":"J. Y. Mori, C. Llanos, P. Berger","doi":"10.1109/SBCCI.2012.6344453","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344453","url":null,"abstract":"Intending to improve design trade offs in image processing architectures this work presents some kernel analysis for convolution-based image filtering. Some well-known filter kernels have been analyzed in order to identify symmetries and to allow the development of alternative architectures that can contribute to reduce power consumption and/or FPGA resources, maintaining or improving the overall system throughput. The separable kernel technique is also analyzed, and two architectures were developed and tested. Additionally, a technique based on overlapping kernels have been developed, analyzed and tested. All architectures were implemented and synthesized using Altera Quartus II EDA software and prototyped in four real-time image processing platforms. These platforms are composed by a CMOS camera, four Terasic FPGA development kits (with Altera devices) and an LCD. Synthesis, simulations and real-time results show the suitability of such architectures for this kind of design trade off.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129752206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344424
F. Marranghello, A. Reis, R. Ribas
This paper presents a new design oriented model for estimating the delay of a CMOS inverter. The model considers the impact of input transition time, input-to-output coupling capacitance, and physical effects such as drain-induced barrier lowering (DIBL) and velocity saturation. Thus, it is quite suitable for nanometer technologies. Moreover, no fitting parameters are required. Results are in very good agreement with HSPICE simulations based on BSIM4 transistor model over a wide range of input slopes and output loads, considering different inverter configurations. An average error of 3% in correlation to HSPICE has been attained.
{"title":"Design-oriented delay model for CMOS inverter","authors":"F. Marranghello, A. Reis, R. Ribas","doi":"10.1109/SBCCI.2012.6344424","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344424","url":null,"abstract":"This paper presents a new design oriented model for estimating the delay of a CMOS inverter. The model considers the impact of input transition time, input-to-output coupling capacitance, and physical effects such as drain-induced barrier lowering (DIBL) and velocity saturation. Thus, it is quite suitable for nanometer technologies. Moreover, no fitting parameters are required. Results are in very good agreement with HSPICE simulations based on BSIM4 transistor model over a wide range of input slopes and output loads, considering different inverter configurations. An average error of 3% in correlation to HSPICE has been attained.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127213518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344419
Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum
MPSoCs are able to support multiple applications on the same chip. This flexibility also represents a vulnerability, turning the MPSoC security specially challenging. Most of the current MPSoCs security services are based on symmetric and public-key cryptographic mechanisms. So that, MPSoCs integrate a large set of keys that must be exchanged in an efficient and secure way. In such scenario, any security concept will be ineffective if the key management is weak. In this paper, we present the implementation of an on-chip hybrid communication (HoCs) security-based architecture, that combines bus and Network-on-chip (NoC), to address the efficient and secure key management at MPSoCs. The HoC implements dynamically the QoSS (Quality of Security Service) concept that allows the customization of security. We evaluate the effectiveness of our approach over several MPSoCs attack scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications. Our hybrid approach saves upto 16% and 25% of communication latency and power consumption, respectively, when compared to the NoC-based architecture without any security.
{"title":"Hybrid-on-chip communication architecture for dynamic MP-SoC protection","authors":"Martha Johanna Sepúlveda, G. Gogniat, R. Pires, J. Wang, M. Strum","doi":"10.1109/SBCCI.2012.6344419","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344419","url":null,"abstract":"MPSoCs are able to support multiple applications on the same chip. This flexibility also represents a vulnerability, turning the MPSoC security specially challenging. Most of the current MPSoCs security services are based on symmetric and public-key cryptographic mechanisms. So that, MPSoCs integrate a large set of keys that must be exchanged in an efficient and secure way. In such scenario, any security concept will be ineffective if the key management is weak. In this paper, we present the implementation of an on-chip hybrid communication (HoCs) security-based architecture, that combines bus and Network-on-chip (NoC), to address the efficient and secure key management at MPSoCs. The HoC implements dynamically the QoSS (Quality of Security Service) concept that allows the customization of security. We evaluate the effectiveness of our approach over several MPSoCs attack scenarios and estimate their impact on the overall performance. We show that our architecture can perform a fast detection of a wide range of attacks and a fast configuration of the different security policies for several MPSoC applications. Our hybrid approach saves upto 16% and 25% of communication latency and power consumption, respectively, when compared to the NoC-based architecture without any security.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"87 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124734477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344450
Seyed-Hosein Attarzadeh-Niaki, Gilmar S. Beserra, N. Andersen, Mathias Verdon, I. Sander
The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.
{"title":"Heterogeneous system-level modeling for small and medium enterprises","authors":"Seyed-Hosein Attarzadeh-Niaki, Gilmar S. Beserra, N. Andersen, Mathias Verdon, I. Sander","doi":"10.1109/SBCCI.2012.6344450","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344450","url":null,"abstract":"The design of today's electronic embedded systems is an increasingly complicated task. This is especially problematic for Small and Medium Enterprises (SMEs) which have limited resources. In this work, we identify a set of common design practices used in industry, with a special focus on problems faced by smaller companies, and formulate them as design scenarios. We show how SMEs can benefit from a system-level design approach by customizing a formal heterogeneous system modeling framework for each scenario. The applicability of this approach is demonstrated by two industrial use cases, an impulse-radio radar and a UART-based protocol.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124394646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-11-12DOI: 10.1109/SBCCI.2012.6344435
C. Santos, R. Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte
Reducing clock network power is an efficient way to reduce power consumption of the high-frequency ASICs since it accounts for a considerable amount of the dynamic chip power. Recently, the use of multi-bit flip-flops (MBFFs) has been shown to be an effective design technique to improve clock tree synthesis and can be used either as an alternative or in conjunction with the well-known clock gating approach targeting clock power reduction. The idea behind this technique is that clock tree power savings can be achieved by using flip-flop cells with optimized design and also through a reduced clock tree once the number of clock sinks is smaller in a design with MBFF cells. Some recent works have been proposing methods to take advantage of using MBFFs in standard cell based designs, where single-bit flip-flops are replaced by MBFF cells during logic and/or physical syntheses. However, a more complete analysis is still needed for different steps of a design flow to help understanding the impact of MBFFs on the physical design. We present in this work a comprehensive comparison between traditional flip-flop and MBFF implementations of an industrial 55nm design. Our results consider area, power and timing as well as some side effects like clock skew, routing congestion and voltage drop distribution. Finally, this study points to some potential drawbacks of using MBFFs which may be helpful for designers to make trade-off decisions in high performance SoC designs.
{"title":"Multi-bit flip-flop usage impact on physical synthesis","authors":"C. Santos, R. Reis, Guilherme Godoi, Marcos Barros, Fabio Duarte","doi":"10.1109/SBCCI.2012.6344435","DOIUrl":"https://doi.org/10.1109/SBCCI.2012.6344435","url":null,"abstract":"Reducing clock network power is an efficient way to reduce power consumption of the high-frequency ASICs since it accounts for a considerable amount of the dynamic chip power. Recently, the use of multi-bit flip-flops (MBFFs) has been shown to be an effective design technique to improve clock tree synthesis and can be used either as an alternative or in conjunction with the well-known clock gating approach targeting clock power reduction. The idea behind this technique is that clock tree power savings can be achieved by using flip-flop cells with optimized design and also through a reduced clock tree once the number of clock sinks is smaller in a design with MBFF cells. Some recent works have been proposing methods to take advantage of using MBFFs in standard cell based designs, where single-bit flip-flops are replaced by MBFF cells during logic and/or physical syntheses. However, a more complete analysis is still needed for different steps of a design flow to help understanding the impact of MBFFs on the physical design. We present in this work a comprehensive comparison between traditional flip-flop and MBFF implementations of an industrial 55nm design. Our results consider area, power and timing as well as some side effects like clock skew, routing congestion and voltage drop distribution. Finally, this study points to some potential drawbacks of using MBFFs which may be helpful for designers to make trade-off decisions in high performance SoC designs.","PeriodicalId":311528,"journal":{"name":"2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130674272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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