Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00020
Hiroyoshi Ichikawa, A. Kobayashi
Selfish nodes can collapse autonomous distributed network systems, such as ad hoc network systems or peer-to-peer network systems. In our previous work, we proposed an autonomous distributed collaborative messaging system model utilizing blockchain technology. An intermediate node obtains tokens of sending a message like a postage stamp if the node relays a message which is not from the node neither to the node. We revealed that communication by multiple relaying nodes can be executed, and selfish node cannot commit fraud. In this paper, we evaluate our proposed method to reveal its effectiveness.
{"title":"Experimental Performance Analysis on Autonomous Distributed Collaborative Messaging Protocol","authors":"Hiroyoshi Ichikawa, A. Kobayashi","doi":"10.1109/CANDARW.2018.00020","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00020","url":null,"abstract":"Selfish nodes can collapse autonomous distributed network systems, such as ad hoc network systems or peer-to-peer network systems. In our previous work, we proposed an autonomous distributed collaborative messaging system model utilizing blockchain technology. An intermediate node obtains tokens of sending a message like a postage stamp if the node relays a message which is not from the node neither to the node. We revealed that communication by multiple relaying nodes can be executed, and selfish node cannot commit fraud. In this paper, we evaluate our proposed method to reveal its effectiveness.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123865451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00026
Toru Koizumi, Satoshi Nakae, A. Fukuda, H. Irie, S. Sakai
It is effective to remove false dependencies to efficiently perform out-of-order (OoO) execution which improves single thread performance. Hardware register renaming removes these dependencies, but it is one of the bottlenecks of the processor because of its complexity. The use of a STRAIGHT architecture is one of the approaches that allow the compiler to remove these dependencies. Because the source operand is specified as the distance between the producer instruction and consumer instruction and there is no register overwriting, no false dependency occurs. Instead, the compiler must generate code that satisfies the constraint of specifying operands as constant distances that are not dependent on the execution path. Although the basic algorithms for realizing the constraint are already known, the machine code generated thereby cannot achieve high performance because it is necessary to execute many inter-register transfer instructions added by compiler to satisfy the constraints. This paper presents an efficient algorithm that uses data flow analysis to determine the value causing an increase in the number of executed instructions and improve the performance by spilling them on the stack. We developed a compiler that implements the proposed method using LLVM and evaluated using CoreMark as a benchmark. The number of executed instructions was reduced by approximately 31 %, and the execution performance improved by up to 32 %.
{"title":"Reduction of Instruction Increase Overhead by STRAIGHT Compiler","authors":"Toru Koizumi, Satoshi Nakae, A. Fukuda, H. Irie, S. Sakai","doi":"10.1109/CANDARW.2018.00026","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00026","url":null,"abstract":"It is effective to remove false dependencies to efficiently perform out-of-order (OoO) execution which improves single thread performance. Hardware register renaming removes these dependencies, but it is one of the bottlenecks of the processor because of its complexity. The use of a STRAIGHT architecture is one of the approaches that allow the compiler to remove these dependencies. Because the source operand is specified as the distance between the producer instruction and consumer instruction and there is no register overwriting, no false dependency occurs. Instead, the compiler must generate code that satisfies the constraint of specifying operands as constant distances that are not dependent on the execution path. Although the basic algorithms for realizing the constraint are already known, the machine code generated thereby cannot achieve high performance because it is necessary to execute many inter-register transfer instructions added by compiler to satisfy the constraints. This paper presents an efficient algorithm that uses data flow analysis to determine the value causing an increase in the number of executed instructions and improve the performance by spilling them on the stack. We developed a compiler that implements the proposed method using LLVM and evaluated using CoreMark as a benchmark. The number of executed instructions was reduced by approximately 31 %, and the execution performance improved by up to 32 %.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116127928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00048
Truong Thao Nguyen, M. Wahib, Ryousei Takano
Driven by the increase in complexity and size in Deep Learning models, training models on large-scale GPUs-accelerated clusters is becoming a commonplace. One of the main challenges for distributed training is the collective communication overhead for the very large message size: from several to hundreds of MB. In this paper, we exploit two hierarchical distributed-memory multi-leader allreduce algorithms optimized for GPU-accelerated clusters (named lr_lr and lr_rab). In which, one node performs the inter-node data transfer in parallel using other GPUs that are designated as node leaders. Each leader keeps and exchanges a partial result of local reduced values rather than the whole one. Hence we are capable of significantly reducing the time for injecting data into the internode network. We evaluate these algorithms on the discreteevent simulation Simgrid. We show that our algorithms, lr_lr and lr_rab, can cut down the execution time of an Allreduce microbenchmark that uses logical ring algorithm (lr) by up to 45% and 51%, respectively. In addition, saving the power consumption of network devices of up to 23% and 32% are projected.
{"title":"Hierarchical Distributed-Memory Multi-Leader MPI-Allreduce for Deep Learning Workloads","authors":"Truong Thao Nguyen, M. Wahib, Ryousei Takano","doi":"10.1109/CANDARW.2018.00048","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00048","url":null,"abstract":"Driven by the increase in complexity and size in Deep Learning models, training models on large-scale GPUs-accelerated clusters is becoming a commonplace. One of the main challenges for distributed training is the collective communication overhead for the very large message size: from several to hundreds of MB. In this paper, we exploit two hierarchical distributed-memory multi-leader allreduce algorithms optimized for GPU-accelerated clusters (named lr_lr and lr_rab). In which, one node performs the inter-node data transfer in parallel using other GPUs that are designated as node leaders. Each leader keeps and exchanges a partial result of local reduced values rather than the whole one. Hence we are capable of significantly reducing the time for injecting data into the internode network. We evaluate these algorithms on the discreteevent simulation Simgrid. We show that our algorithms, lr_lr and lr_rab, can cut down the execution time of an Allreduce microbenchmark that uses logical ring algorithm (lr) by up to 45% and 51%, respectively. In addition, saving the power consumption of network devices of up to 23% and 32% are projected.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00058
Kazuki Hazama, H. Ebara
In recent years, computer environment using multiple processors such as multi-core and many-core device attracts attention due to the limit of performance improvement per processor. In this paper, we propose a new algorithm for the combinatorial optimization problem using a parallel search method called LazySMP to efficiently use many-core processors. LazySMP is a method based on the iterative deepening depth-first search, which is used for board searching of chess and shogi software. In this method, the search results are saved in a table that all processes can share, and the results are used in the search of other processes to shorten the search time. In the proposed method, Lazy SMP is applied to the branch and bound method. Specifically, it performs a branch and bound method that iteratively deepens in all threads and save a part of the result of some nodes in the shared hash table. Then, when it performs the subsequent searches, the hash table is referred to instead of researching the nodes. Our aim is to make efficient use of many-core processors. We make computer experiments with the traveling salesman problem as the benchmark in order to verify the performance of the proposed method.
{"title":"Branch and Bound Algorithm for Parallel Many-Core Architecture","authors":"Kazuki Hazama, H. Ebara","doi":"10.1109/CANDARW.2018.00058","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00058","url":null,"abstract":"In recent years, computer environment using multiple processors such as multi-core and many-core device attracts attention due to the limit of performance improvement per processor. In this paper, we propose a new algorithm for the combinatorial optimization problem using a parallel search method called LazySMP to efficiently use many-core processors. LazySMP is a method based on the iterative deepening depth-first search, which is used for board searching of chess and shogi software. In this method, the search results are saved in a table that all processes can share, and the results are used in the search of other processes to shorten the search time. In the proposed method, Lazy SMP is applied to the branch and bound method. Specifically, it performs a branch and bound method that iteratively deepens in all threads and save a part of the result of some nodes in the shared hash table. Then, when it performs the subsequent searches, the hash table is referred to instead of researching the nodes. Our aim is to make efficient use of many-core processors. We make computer experiments with the traveling salesman problem as the benchmark in order to verify the performance of the proposed method.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122828180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00064
M. Nagatomo, K. Aburada, N. Okazaki, Mirang Park
With the advancement of wireless short-range technology, the number of mobile devices is also increasing. Consequently, devices often exchange information using wireless communications, but this communication has vulnerabilities, such as eavesdropping and man-in-the-middle attack. Therefore, it is necessary to perform secure pairing between devices before wireless communication begin. In this paper, we assume that devices are securely paired in limited space, such as a room using wireless communication. The method for secure pairing using Received signal strength (RSS) is simple, but RSS is easy to change due to environmental factors. Recently, pairing methods using camera and accelerometer are studied. However, these methods do not directly detect inclination of the device. We propose the one of secure device pairing method using camera and accelerometer. Our proposed method make the camera read a marker on the display of the device. The marker's inclination corresponds to the device's inclination, hence, we assume that the accuracy is higher than that of existing methods.
{"title":"Proposal and Evaluation of Secure Device Pairing Method with Camera and Accelerometer","authors":"M. Nagatomo, K. Aburada, N. Okazaki, Mirang Park","doi":"10.1109/CANDARW.2018.00064","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00064","url":null,"abstract":"With the advancement of wireless short-range technology, the number of mobile devices is also increasing. Consequently, devices often exchange information using wireless communications, but this communication has vulnerabilities, such as eavesdropping and man-in-the-middle attack. Therefore, it is necessary to perform secure pairing between devices before wireless communication begin. In this paper, we assume that devices are securely paired in limited space, such as a room using wireless communication. The method for secure pairing using Received signal strength (RSS) is simple, but RSS is easy to change due to environmental factors. Recently, pairing methods using camera and accelerometer are studied. However, these methods do not directly detect inclination of the device. We propose the one of secure device pairing method using camera and accelerometer. Our proposed method make the camera read a marker on the display of the device. The marker's inclination corresponds to the device's inclination, hence, we assume that the accuracy is higher than that of existing methods.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00056
H. Matsufuru, K. Sumiyoshi
To understand the mechanism of supernova explosions, large-scale numerical simulations are essential because of their complex dynamics described by a coupled equations of neutrino radiation transport and hydrodynamics of dense matter. In this work, we employ GPUs to accelerate such simulations. By adopting the implicit scheme for the evolution equation, an iterative linear equation solver for the coefficient matrix is the most time consuming part, which has been shown to be efficiently offloaded to GPUs. There are still several secondary bottlenecks which cost substantial time in the simulations, such as computation of the collision term of the Boltzmann equation of neutrinos, and parameter tuning of the matrices in the iterative solver. This paper focuses on these parts and offloads them to GPUs by employing CUDA in the case of spherically symmetric system. As a result, the time evolution is sufficiently accelerated for desirable model sizes toward systematic survey of stellar models with better grid resolution than that adopted so far.
{"title":"Accelerating Numerical Simulations of Supernovae with GPUs","authors":"H. Matsufuru, K. Sumiyoshi","doi":"10.1109/CANDARW.2018.00056","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00056","url":null,"abstract":"To understand the mechanism of supernova explosions, large-scale numerical simulations are essential because of their complex dynamics described by a coupled equations of neutrino radiation transport and hydrodynamics of dense matter. In this work, we employ GPUs to accelerate such simulations. By adopting the implicit scheme for the evolution equation, an iterative linear equation solver for the coefficient matrix is the most time consuming part, which has been shown to be efficiently offloaded to GPUs. There are still several secondary bottlenecks which cost substantial time in the simulations, such as computation of the collision term of the Boltzmann equation of neutrinos, and parameter tuning of the matrices in the iterative solver. This paper focuses on these parts and offloads them to GPUs by employing CUDA in the case of spherically symmetric system. As a result, the time evolution is sufficiently accelerated for desirable model sizes toward systematic survey of stellar models with better grid resolution than that adopted so far.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127121956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00092
Ryuga Matsumura, T. Sugawara, K. Sakiyama
Sensor spoofing attack is an emerging threat to laser-based ranging. In this paper, we propose a countermeasure that superimposes authentication fingerprint onto light wave itself. In the proposed method, amplification of laser output is directly modulated by power side-channel information leaked from a cryptographic device. The feasibility of the concept is verified through experiments.
{"title":"A Secure LiDAR with AES-Based Side-Channel Fingerprinting","authors":"Ryuga Matsumura, T. Sugawara, K. Sakiyama","doi":"10.1109/CANDARW.2018.00092","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00092","url":null,"abstract":"Sensor spoofing attack is an emerging threat to laser-based ranging. In this paper, we propose a countermeasure that superimposes authentication fingerprint onto light wave itself. In the proposed method, amplification of laser output is directly modulated by power side-channel information leaked from a cryptographic device. The feasibility of the concept is verified through experiments.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131185180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00032
Seiya Shirakuni, Ittetsu Taniguchi, H. Tomiyama
Due to the advances in semiconductor technologies, a recent FPGA device is capable of implementing a number of CPU cores, and manycore architecture on an FPGA attracts an increasing attention in the design of high-performance embedded systems. In embedded system design with FPGA-based manycore architectures, it is important to optimize not only the number and topology of cores but also memory architecture for each application in order to achieve high performance under limited FPGA resources. This paper presents a case study on memory architecture exploration for manycores on an FPGA. We design and implement three types of manycore architecture, together with an OpenCL-based software framework. The performance of the three architectures is evaluated based on actual measurement using various application programs.
{"title":"A Case Study on Memory Architecture Exploration for Manycores on an FPGA","authors":"Seiya Shirakuni, Ittetsu Taniguchi, H. Tomiyama","doi":"10.1109/CANDARW.2018.00032","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00032","url":null,"abstract":"Due to the advances in semiconductor technologies, a recent FPGA device is capable of implementing a number of CPU cores, and manycore architecture on an FPGA attracts an increasing attention in the design of high-performance embedded systems. In embedded system design with FPGA-based manycore architectures, it is important to optimize not only the number and topology of cores but also memory architecture for each application in order to achieve high performance under limited FPGA resources. This paper presents a case study on memory architecture exploration for manycores on an FPGA. We design and implement three types of manycore architecture, together with an OpenCL-based software framework. The performance of the three architectures is evaluated based on actual measurement using various application programs.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131302541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00046
Hiroto Kizuna, Hiroyuki Sato
Recently, needs of individual personal entering and exiting information are high by development of deep learning. In order to automatically acquire entering and exiting, it is necessary to acquire a facial image of a human who enters or exits within about one second, so a faster face detection technology is required. And the installation space of photography equipment is narrow. We developed a high-speed facial area estimation algorithm by reducing the facial search area using a high-speed image processing and speeding up with GPGPU. By executing on GPU of Jetson TX 2, execution time of the facial area estimation becomes about 14 ms and accelerating rate with respect to the conventional method is 60 times. This result shows that practical facial area estimation processing is possible even on an inexpensive and compact processor.
{"title":"Accelerating Facial Detection for Improvement of Person Identification Accuracy in Entering and Exiting Management System","authors":"Hiroto Kizuna, Hiroyuki Sato","doi":"10.1109/CANDARW.2018.00046","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00046","url":null,"abstract":"Recently, needs of individual personal entering and exiting information are high by development of deep learning. In order to automatically acquire entering and exiting, it is necessary to acquire a facial image of a human who enters or exits within about one second, so a faster face detection technology is required. And the installation space of photography equipment is narrow. We developed a high-speed facial area estimation algorithm by reducing the facial search area using a high-speed image processing and speeding up with GPGPU. By executing on GPU of Jetson TX 2, execution time of the facial area estimation becomes about 14 ms and accelerating rate with respect to the conventional method is 60 times. This result shows that practical facial area estimation processing is possible even on an inexpensive and compact processor.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128213333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-11-01DOI: 10.1109/CANDARW.2018.00069
H. Michizu, Y. Sudo, H. Kakugawa, T. Masuzawa
Wireless energy transfer is a technology to transmit electricity without wire, and it is a promising technology for charging battery of mobile devices. In battery powered sensor networks, it is important to balance electric energy of batteries of nodes in order to maximize the life time of networks. In this paper, we propose two distributed protocols to balance electric energy of batteries of nodes. The proposed algorithms are based on the population protocol model which is a computational model for networked nodes with very limited resources. The goals of the algorithms are twofold: minimizing the loss of electric energy caused by wireless transmission, and minimizing the time to balance. The proposed algorithms are evaluated by computer simulation.
{"title":"Energy Balancing by Wireless Energy Transfer in Sensor Networks","authors":"H. Michizu, Y. Sudo, H. Kakugawa, T. Masuzawa","doi":"10.1109/CANDARW.2018.00069","DOIUrl":"https://doi.org/10.1109/CANDARW.2018.00069","url":null,"abstract":"Wireless energy transfer is a technology to transmit electricity without wire, and it is a promising technology for charging battery of mobile devices. In battery powered sensor networks, it is important to balance electric energy of batteries of nodes in order to maximize the life time of networks. In this paper, we propose two distributed protocols to balance electric energy of batteries of nodes. The proposed algorithms are based on the population protocol model which is a computational model for networked nodes with very limited resources. The goals of the algorithms are twofold: minimizing the loss of electric energy caused by wireless transmission, and minimizing the time to balance. The proposed algorithms are evaluated by computer simulation.","PeriodicalId":329439,"journal":{"name":"2018 Sixth International Symposium on Computing and Networking Workshops (CANDARW)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131396840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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