Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913204
M. T. Higuera-Toledano
Conventional cache memories act to bridge the gap in speeds between the processor and main memory. However, typical cache memories do not take into account of the specific characteristics of objects-oriented programs. As result it may incur in a performance penalty. In this paper, we discuss how an objects-based cache device can support Java objects. This feature is especially useful in the field of real-time programming, where the determinism for memory cache accesses is a limiting factor. In order to do that, we propose an object layout which splits objects into the same sized blocks; in this way, each cache memory line supports a block. This memory model avoids external fragmentation, while minimizing internal fragmentation.
{"title":"Object representation model for a cache memory in a real-time Java environment","authors":"M. T. Higuera-Toledano","doi":"10.1109/ISORC.2013.6913204","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913204","url":null,"abstract":"Conventional cache memories act to bridge the gap in speeds between the processor and main memory. However, typical cache memories do not take into account of the specific characteristics of objects-oriented programs. As result it may incur in a performance penalty. In this paper, we discuss how an objects-based cache device can support Java objects. This feature is especially useful in the field of real-time programming, where the determinism for memory cache accesses is a limiting factor. In order to do that, we propose an object layout which splits objects into the same sized blocks; in this way, each cache memory line supports a block. This memory model avoids external fragmentation, while minimizing internal fragmentation.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130630722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913238
U. Brinkschulte
The Artificial Hormone System (AHS) is a completely decentralized operation principle for a middleware which can be used to allocate tasks in a system of heterogeneous processing elements (PEs) or cores. Tasks are scheduled according to their suitability for the heterogeneous PEs, the current PE load and task relationships. The AHS also provides properties like self-configuration, self-optimization and self-healing by task allocation. The AHS is able to guarantee real-time bounds for such self-X-properties. Clustering of related tasks is done by the AHS through the emission of accelerator hormones, which attract related tasks to neighboring PEs. However, accelerators may increase the task load of PEs and even cause instability. In this paper we present two new approaches to eliminate the destabilizing effect of accelerators but keeping their property to attract related tasks. The accelerator threshold approach and the accelerator saturation approach introduce two different kinds of accelerator bounds. A theoretical analysis and a practical evaluation show the effectiveness and the different properties of both approaches.
{"title":"Increasing the stability of an Artificial Hormone System for task allocation by accelerator bounds","authors":"U. Brinkschulte","doi":"10.1109/ISORC.2013.6913238","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913238","url":null,"abstract":"The Artificial Hormone System (AHS) is a completely decentralized operation principle for a middleware which can be used to allocate tasks in a system of heterogeneous processing elements (PEs) or cores. Tasks are scheduled according to their suitability for the heterogeneous PEs, the current PE load and task relationships. The AHS also provides properties like self-configuration, self-optimization and self-healing by task allocation. The AHS is able to guarantee real-time bounds for such self-X-properties. Clustering of related tasks is done by the AHS through the emission of accelerator hormones, which attract related tasks to neighboring PEs. However, accelerators may increase the task load of PEs and even cause instability. In this paper we present two new approaches to eliminate the destabilizing effect of accelerators but keeping their property to attract related tasks. The accelerator threshold approach and the accelerator saturation approach introduce two different kinds of accelerator bounds. A theoretical analysis and a practical evaluation show the effectiveness and the different properties of both approaches.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"1277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125571033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913243
T. Heller, D. Fey, M. Rehak
The field of non-destructive testing imposes rising performance requirements related to the compute resources necessary to satisfy application needs. The creation of scalable applications in that field, which efficiently utilize today's mostly heterogeneous compute resources has proven to be complicated. In order to allow domain experts coming from a materials science background, to exploit modern heterogenous computing architectures, new classes of frameworks for efficient applications need to be developed. This paper proposes a new framework to develop efficient operators and operator chains for applications in the field of non-destructive testing, based on a self-organizing autotuning approach. The framework provides a C++ Interface to define base operators and implements an Embedded Domain Specific Language (EDSL) using C++ Expression Templates (ETs) which allows a succinct definition of an Operator Chain. The framework applies various kinds of optimizations by utilizing C++ Template Metaprogramming techniques. These optimizations include feedback based auto-tuning and auto-parallelization of the resulting Pipeline based on the advanced dataflow and future's techniques provided by the High Performance ParalleX (HPX), a general purpose parallel C++ runtime system.
{"title":"An auto-tuning approach for optimizing base operators for non-destructive testing applications on heterogeneous multi-core architectures","authors":"T. Heller, D. Fey, M. Rehak","doi":"10.1109/ISORC.2013.6913243","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913243","url":null,"abstract":"The field of non-destructive testing imposes rising performance requirements related to the compute resources necessary to satisfy application needs. The creation of scalable applications in that field, which efficiently utilize today's mostly heterogeneous compute resources has proven to be complicated. In order to allow domain experts coming from a materials science background, to exploit modern heterogenous computing architectures, new classes of frameworks for efficient applications need to be developed. This paper proposes a new framework to develop efficient operators and operator chains for applications in the field of non-destructive testing, based on a self-organizing autotuning approach. The framework provides a C++ Interface to define base operators and implements an Embedded Domain Specific Language (EDSL) using C++ Expression Templates (ETs) which allows a succinct definition of an Operator Chain. The framework applies various kinds of optimizations by utilizing C++ Template Metaprogramming techniques. These optimizations include feedback based auto-tuning and auto-parallelization of the resulting Pipeline based on the advanced dataflow and future's techniques provided by the High Performance ParalleX (HPX), a general purpose parallel C++ runtime system.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"406 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126682928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913207
Benjamin Betting, U. Brinkschulte, Mathias Pacher
This article presents our concept of an artificial hormone system for realizing a completely decentralized self-organizing and real-time capable task control mechanism using self-X properties. Besides the fundamentals of the prior hormone concept and the implementation model, we present latest results of our research: evaluation and superiority analysis of a AHS-controlled SoC towards other approaches in centralized or partly decentralized manner like feedback controllers and complex multi-agents. Furthermore we validate and compare the overheads for size, communication and computation in relation to the improvement in system reliability.
{"title":"Evaluation and superiority analysis of a decentralized task control mechanism for dependable real-time SoC architectures","authors":"Benjamin Betting, U. Brinkschulte, Mathias Pacher","doi":"10.1109/ISORC.2013.6913207","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913207","url":null,"abstract":"This article presents our concept of an artificial hormone system for realizing a completely decentralized self-organizing and real-time capable task control mechanism using self-X properties. Besides the fundamentals of the prior hormone concept and the implementation model, we present latest results of our research: evaluation and superiority analysis of a AHS-controlled SoC towards other approaches in centralized or partly decentralized manner like feedback controllers and complex multi-agents. Furthermore we validate and compare the overheads for size, communication and computation in relation to the improvement in system reliability.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129555387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913226
S. Oikawa
Byte addressable non-volatile (NV) memory, such as STT-RAM, MRAM, and PCM, is the next generation memory that can be used as both main memory and secondary storage. While it can persistently store data without power supply, its access speed is comparable to DRAM. While there have been the active researches on its use for either main memory or secondary storage, these researches were conducted independently. This paper presents the integration methods of the main memory and file system management for NV memory, so that it can be used as both main memory and storage. The presented methods use a file system as their basis for the NV memory management; thus, the internal data structures of a file system can have impacts upon the performance of the integration methods. We implemented the proposed methods in the Linux kernel, and performed the evaluation on a system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory.
{"title":"Integration methods of main memory and file system management for non-volatile main memory and implications of file system structures","authors":"S. Oikawa","doi":"10.1109/ISORC.2013.6913226","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913226","url":null,"abstract":"Byte addressable non-volatile (NV) memory, such as STT-RAM, MRAM, and PCM, is the next generation memory that can be used as both main memory and secondary storage. While it can persistently store data without power supply, its access speed is comparable to DRAM. While there have been the active researches on its use for either main memory or secondary storage, these researches were conducted independently. This paper presents the integration methods of the main memory and file system management for NV memory, so that it can be used as both main memory and storage. The presented methods use a file system as their basis for the NV memory management; thus, the internal data structures of a file system can have impacts upon the performance of the integration methods. We implemented the proposed methods in the Linux kernel, and performed the evaluation on a system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124503410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913193
Leonidas Kosmidis, E. Quiñones, J. Abella, T. Vardanega, F. Cazorla
Probabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic dependence on execution history. This distinctive feature is a great facilitator to time composability, which is a must for industry needing incremental development and qualification. In this paper we show how time composability is achieved in PTA-conformant systems and how the pessimism of worst-case execution time bounds obtained from PTA is contained within a 5% to 25% range for representative application scenarios.
{"title":"Achieving timing composability with measurement-based probabilistic timing analysis","authors":"Leonidas Kosmidis, E. Quiñones, J. Abella, T. Vardanega, F. Cazorla","doi":"10.1109/ISORC.2013.6913193","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913193","url":null,"abstract":"Probabilistic Timing Analysis (PTA) allows complex hardware acceleration features, which defeat classic timing analysis, to be used in hard real-time systems. PTA can do that because it drastically reduces intrinsic dependence on execution history. This distinctive feature is a great facilitator to time composability, which is a must for industry needing incremental development and qualification. In this paper we show how time composability is achieved in PTA-conformant systems and how the pessimism of worst-case execution time bounds obtained from PTA is contained within a 5% to 25% range for representative application scenarios.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116731050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913221
Guoqing Zhang, T. Ahonen
LLVM has gained its popularity from both industrial side and academic side due to its well-defined architecture and good support for parallel programming. The purpose of this paper is to explain essential concepts which must be understood by complier developers in order to carry on the implementation of LLVM based compiler and also share experiences that we've gained during the implementation of our own LLVM compiler. For developers who have a working GCC compiler at hand, we propose a methodology to help them verify the new LLVM compiler by using the output of existing GCC compiler as reference. The COFFEE core (A Core For FrEE) is the hardware we are targeting, which supports both integer operations and single precision floating point operations. The paper will illustrate how the LLVM based compiler for the COFFEE core is implemented in both front end and back end.
LLVM由于其定义良好的架构和对并行编程的良好支持，在工业和学术方面都获得了广泛的欢迎。本文的目的是解释编译器开发人员必须理解的基本概念，以便进行基于LLVM的编译器的实现，并分享我们在实现自己的LLVM编译器过程中获得的经验。对于手头有GCC编译器的开发人员，我们提出了一种方法，通过使用现有GCC编译器的输出作为参考来帮助他们验证新的LLVM编译器。COFFEE核心(A core For FrEE)是我们的目标硬件，它既支持整数运算，也支持单精度浮点运算。本文将说明基于LLVM的COFFEE核心编译器是如何在前端和后端实现的。
{"title":"A LLVM based compiler for COFFEE","authors":"Guoqing Zhang, T. Ahonen","doi":"10.1109/ISORC.2013.6913221","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913221","url":null,"abstract":"LLVM has gained its popularity from both industrial side and academic side due to its well-defined architecture and good support for parallel programming. The purpose of this paper is to explain essential concepts which must be understood by complier developers in order to carry on the implementation of LLVM based compiler and also share experiences that we've gained during the implementation of our own LLVM compiler. For developers who have a working GCC compiler at hand, we propose a methodology to help them verify the new LLVM compiler by using the output of existing GCC compiler as reference. The COFFEE core (A Core For FrEE) is the hardware we are targeting, which supports both integer operations and single precision floating point operations. The paper will illustrate how the LLVM based compiler for the COFFEE core is implemented in both front end and back end.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134106911","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913228
Can Basaran, Homin Park, Taejoon Park, S. Son
Smart home environments require tight coupling between different types of sensors, actuators, and computer algorithms. To address the challenges in building a robust and effective smart home environment, it is essential to develop a systematic approach to handling a large number of components and their interactions. We describe a wholistic, multi-layered, and service oriented approach to smart home environment design that will enable abstractions needed for deploying system applications and analyzing individual modules. This paper presents our approach and modules, sensors, and actuators that are required for intelligent services in smart home environments.
{"title":"Towards intelligent services in smart home environments","authors":"Can Basaran, Homin Park, Taejoon Park, S. Son","doi":"10.1109/ISORC.2013.6913228","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913228","url":null,"abstract":"Smart home environments require tight coupling between different types of sensors, actuators, and computer algorithms. To address the challenges in building a robust and effective smart home environment, it is essential to develop a systematic approach to handling a large number of components and their interactions. We describe a wholistic, multi-layered, and service oriented approach to smart home environment design that will enable abstractions needed for deploying system applications and analyzing individual modules. This paper presents our approach and modules, sensors, and actuators that are required for intelligent services in smart home environments.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115862799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913192
Markus Becker, U. Kiffmeier, W. Müller
This article presents the HeroeS virtual platform driven methodology for embedded multi-core and real-time SW design. The methodology's focus is on early integration, testing and performance estimation of heterogeneous SW stacks, i.e., SW components and layers at mixed abstraction levels and/or targeting different instruction sets. We take into account current system-level methodologies such as Transaction Level Modeling (TLM) and Real-Time Operating System (RTOS) modeling. For this, a SystemC virtual platform framework is presented combining state of the art simulation techniques according to the proposed methodology. This includes host-compiled target SW abstraction, abstract RTOS and Hardware Abstraction Layer (HAL) models in SystemC, extended QEMU user and system mode emulation and TLM 2.0 bus models. Efficient but yet accurate performance estimates can be provided through static and dynamic annotation. We apply binary mutation testing, i.e, a test assessment and improvement approach for instruction level SW testing. Our approach was investigated by prototypical integration into a commercial AUTOSAR environment. Experimental results were obtained by an automotive case study: a fault-tolerant fuel injection control system, which is part of an in-car network.
{"title":"HeroeS: Virtual platform driven integration of heterogeneous software components for multi-core real-time architectures","authors":"Markus Becker, U. Kiffmeier, W. Müller","doi":"10.1109/ISORC.2013.6913192","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913192","url":null,"abstract":"This article presents the HeroeS virtual platform driven methodology for embedded multi-core and real-time SW design. The methodology's focus is on early integration, testing and performance estimation of heterogeneous SW stacks, i.e., SW components and layers at mixed abstraction levels and/or targeting different instruction sets. We take into account current system-level methodologies such as Transaction Level Modeling (TLM) and Real-Time Operating System (RTOS) modeling. For this, a SystemC virtual platform framework is presented combining state of the art simulation techniques according to the proposed methodology. This includes host-compiled target SW abstraction, abstract RTOS and Hardware Abstraction Layer (HAL) models in SystemC, extended QEMU user and system mode emulation and TLM 2.0 bus models. Efficient but yet accurate performance estimates can be provided through static and dynamic annotation. We apply binary mutation testing, i.e, a test assessment and improvement approach for instruction level SW testing. Our approach was investigated by prototypical integration into a commercial AUTOSAR environment. Experimental results were obtained by an automotive case study: a fault-tolerant fuel injection control system, which is part of an in-car network.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122975569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-06-19DOI: 10.1109/ISORC.2013.6913219
T. Heimfarth, Hewerton Enes de Oliveira, E. P. Freitas
This work presents a method of coordinating static ground sensors with Unmanned Aerial Vehicles using coordinators. The ground wireless sensors are responsible for the primary detection of an event (e.g. intrusion in the monitored area). After the initial detection, a suitable UAV, equipped with high quality surveillance devices, should be designed inspect the event's area. A method combining a geographic routing with a UAV-CoordinatorPosition function that is responsible to deliver the initial alarm to the selected UAV is presented. In this method, each UAV has a coordinator node on the ground network. This coordinator receive periodic updates of the UAV actual position. When an alarm is issued by any ground sensor, it is forwarded to the appropriated coordinator, and it is then responsible to forward using the geo-routing to the selected UAV. The position of the coordinator is determined by the UAV-CoordinatorPosition function which receives the characteristics of the UAV as input and returns the position of the corresponding coordinator. Results showed the efficiency of the proposed method, reducing by 45.39% the number of hops needed to find the appropriate UAV in comparison with the strategy using a bio-inspired method presented in the literature. In most cases, the UAV could handle at least 65% of the alarms.
{"title":"Alarm delivery to Unmanned Aerial Vehicles in wireless sensor networks using coordinators","authors":"T. Heimfarth, Hewerton Enes de Oliveira, E. P. Freitas","doi":"10.1109/ISORC.2013.6913219","DOIUrl":"https://doi.org/10.1109/ISORC.2013.6913219","url":null,"abstract":"This work presents a method of coordinating static ground sensors with Unmanned Aerial Vehicles using coordinators. The ground wireless sensors are responsible for the primary detection of an event (e.g. intrusion in the monitored area). After the initial detection, a suitable UAV, equipped with high quality surveillance devices, should be designed inspect the event's area. A method combining a geographic routing with a UAV-CoordinatorPosition function that is responsible to deliver the initial alarm to the selected UAV is presented. In this method, each UAV has a coordinator node on the ground network. This coordinator receive periodic updates of the UAV actual position. When an alarm is issued by any ground sensor, it is forwarded to the appropriated coordinator, and it is then responsible to forward using the geo-routing to the selected UAV. The position of the coordinator is determined by the UAV-CoordinatorPosition function which receives the characteristics of the UAV as input and returns the position of the corresponding coordinator. Results showed the efficiency of the proposed method, reducing by 45.39% the number of hops needed to find the appropriate UAV in comparison with the strategy using a bio-inspired method presented in the literature. In most cases, the UAV could handle at least 65% of the alarms.","PeriodicalId":330873,"journal":{"name":"16th IEEE International Symposium on Object/component/service-oriented Real-time distributed Computing (ISORC 2013)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126086857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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