Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974266
N. Lamberti, M. Mura, Nicola Greco, P. D'Uva, Valerio Apuzzo
Due to the growing demand for humidity control systems, there is a need for small, cheap, accurate and reliable sensors for air relative humidity (RH) measurements. In this paper, a resonant air relative humidity sensor is presented. The sensor is based on a quartz crystal coated on both surfaces with a hygroscopic polymer. Due to the adsorption of water molecules, the polymer mass increases accordingly with the surrounding air humidity, causing the decrease of the device resonance frequency. By measuring the sensor resonance frequency, an accurate RH measurement can be obtained. Experimental results are shown, comparing the fabricated sensor behavior with a commercially available RH sensor.
{"title":"A resonant sensor for relative humidity measurements based on a polymer-coated quartz crystal","authors":"N. Lamberti, M. Mura, Nicola Greco, P. D'Uva, Valerio Apuzzo","doi":"10.1109/IWASI.2017.7974266","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974266","url":null,"abstract":"Due to the growing demand for humidity control systems, there is a need for small, cheap, accurate and reliable sensors for air relative humidity (RH) measurements. In this paper, a resonant air relative humidity sensor is presented. The sensor is based on a quartz crystal coated on both surfaces with a hygroscopic polymer. Due to the adsorption of water molecules, the polymer mass increases accordingly with the surrounding air humidity, causing the decrease of the device resonance frequency. By measuring the sensor resonance frequency, an accurate RH measurement can be obtained. Experimental results are shown, comparing the fabricated sensor behavior with a commercially available RH sensor.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115122978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974248
Javed Iqbal, M. Lazarescu, Osama Bin Tariq, L. Lavagno
Capacitive sensors have important advantages and are widely used, but typically up to sensing distances comparable to sensor size. We present the design and experimental results of a self-contained long range capacitive sensor that is suitable for indoor human localization. We make differential measurements of the reactance effects of sensor plate capacitance using a constant excitation frequency, which is both less prone to noise and easier to filter. The experimental results show good sensor sensitivity up to 200 cm for a 16 cm square sensor plate, low noise and good measurement stability.
{"title":"Long range, high sensitivity, low noise capacitive sensor for tagless indoor human localization","authors":"Javed Iqbal, M. Lazarescu, Osama Bin Tariq, L. Lavagno","doi":"10.1109/IWASI.2017.7974248","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974248","url":null,"abstract":"Capacitive sensors have important advantages and are widely used, but typically up to sensing distances comparable to sensor size. We present the design and experimental results of a self-contained long range capacitive sensor that is suitable for indoor human localization. We make differential measurements of the reactance effects of sensor plate capacitance using a constant excitation frequency, which is both less prone to noise and easier to filter. The experimental results show good sensor sensitivity up to 200 cm for a 16 cm square sensor plate, low noise and good measurement stability.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132756788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974215
F. Sebastiano, H. Homulle, Jeroen P. G. van Dijk, R. M. Incandela, B. Patra, M. Mehrpoo, M. Babaie, A. Vladimirescu, E. Charbon
Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.
{"title":"Cryogenic CMOS interfaces for quantum devices","authors":"F. Sebastiano, H. Homulle, Jeroen P. G. van Dijk, R. M. Incandela, B. Patra, M. Mehrpoo, M. Babaie, A. Vladimirescu, E. Charbon","doi":"10.1109/IWASI.2017.7974215","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974215","url":null,"abstract":"Quantum computers could efficiently solve problems that are intractable by today's computers, thus offering the possibility to radically change entire industries and revolutionize our lives. A quantum computer comprises a quantum processor operating at cryogenic temperature and an electronic interface for its control, which is currently implemented at room temperature for the few qubits available today. However, this approach becomes impractical as the number of qubits grows towards the tens of thousands required for complex quantum algorithms with practical applications. We propose an electronic interface for sensing and controlling qubits operating at cryogenic temperature implemented in standard CMOS.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126479836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974237
M. Matteis, A. Donno, Stefano Marinaci, S. D’Amico, A. Baschirotto
A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.
{"title":"A 0.9V 3rd-order single-OPAMP analog filter in 28nm CMOS-bulk","authors":"M. Matteis, A. Donno, Stefano Marinaci, S. D’Amico, A. Baschirotto","doi":"10.1109/IWASI.2017.7974237","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974237","url":null,"abstract":"A 3rd-order 132MHz cut-off frequency low-pass filter in 28nm CMOS-bulk technology is presented. Challenges related to the design of analog circuits in 28nm CMOS-bulk process node have been faced and mitigated operating at both architecture and circuit design level. The filter is based on an improved Active-gm-RC structure, where both poles of a Miller-compensated Opamp have been used for synthesizing the 3rd order filter transfer function. The proposed circuit solution enables high linearity (IIP3=11.5dBm at 21&22MHz input tones) even if the supply voltage is limited to 0.9V. Moreover, the power consumption is kept as low as 340μν without that the Signal-to-Noise ratio (60dB) is penalized. The achieved Figure-of-Merit is 164dB resulting the highest with respect to the state-of-the-art.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124880481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974250
K. Makinwa
Today, CMOS Temperature sensors are predominantly based on parasitic bipolar junction transistors (BJTs). This is because such sensors can achieve high accuracy (< 0.1C error) after a single room-temperature calibration. Although resistor-based temperature sensors can achieve higher resolution and energy-efficiency, they usually require multi-point calibration to reach similar levels of accuracy. In a recent breakthrough, we have discovered that temperature sensors based on silicided poly resistors are an exception to this rule. Two temperature sensor architectures will be presented that use such resistors to achieve good accuracy (<0.2C) after a one or two-point calibration, as well as state-of-the-art energy-efficiency and resolution.
{"title":"Next generation CMOS temperature sensors","authors":"K. Makinwa","doi":"10.1109/IWASI.2017.7974250","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974250","url":null,"abstract":"Today, CMOS Temperature sensors are predominantly based on parasitic bipolar junction transistors (BJTs). This is because such sensors can achieve high accuracy (< 0.1C error) after a single room-temperature calibration. Although resistor-based temperature sensors can achieve higher resolution and energy-efficiency, they usually require multi-point calibration to reach similar levels of accuracy. In a recent breakthrough, we have discovered that temperature sensors based on silicided poly resistors are an exception to this rule. Two temperature sensor architectures will be presented that use such resistors to achieve good accuracy (<0.2C) after a one or two-point calibration, as well as state-of-the-art energy-efficiency and resolution.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122852588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974222
F. Licciulli, P. Aspell, Mieczyslaw Dabrowski, G. Lentdecker, G. Robertis, M. Idzik, A. Irshad, F. Loddo, H. Petrow, J. Rosa, T. Tuuva
VFAT3 is the last version of a family of multichannel trigger and tracking ASICs designed for the upgrade of the CMS experiment in the LHC. The chip has been developed to provide fast trigger information from the readout of gas particle detectors improving the resolution of the time measurement. The VFAT3 architecture comprises 128 analog channels, each one composed by a low noise and low power charge sensitive amplifier, shaper and constant fraction discriminator. The comparator output is synchronized with the LHC clock and sent both to a fixed latency path for trigger signal generation and to a variable latency path for storage and readout. The front-end amplifier is programmable in terms of gain and pulse shaping time, in order to adapt it to a wide range of gaseous detectors as well as silicon detectors. The chip also comprises a programmable calibration system that can provide both voltage and current pulses. There are also two internal 10 bit ADCs for the monitoring of the internal bias references. The digital logic provides trigger generation, digital data tagging and storage, data formatting and data packet transmission with error protection on 320Mbps e-link. The digital design is triplicated in order to improve the radiation hardness of the system. A first run of the chip of 9.1×6.1mm2 in 130nm technology node has been submitted and produced. Chip architecture, measurements and characterization of the calibration, bias and monitoring system will be shown.
{"title":"Calibration, bias and monitoring system for the VFAT3 ASIC of the CMS GEM detector","authors":"F. Licciulli, P. Aspell, Mieczyslaw Dabrowski, G. Lentdecker, G. Robertis, M. Idzik, A. Irshad, F. Loddo, H. Petrow, J. Rosa, T. Tuuva","doi":"10.1109/IWASI.2017.7974222","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974222","url":null,"abstract":"VFAT3 is the last version of a family of multichannel trigger and tracking ASICs designed for the upgrade of the CMS experiment in the LHC. The chip has been developed to provide fast trigger information from the readout of gas particle detectors improving the resolution of the time measurement. The VFAT3 architecture comprises 128 analog channels, each one composed by a low noise and low power charge sensitive amplifier, shaper and constant fraction discriminator. The comparator output is synchronized with the LHC clock and sent both to a fixed latency path for trigger signal generation and to a variable latency path for storage and readout. The front-end amplifier is programmable in terms of gain and pulse shaping time, in order to adapt it to a wide range of gaseous detectors as well as silicon detectors. The chip also comprises a programmable calibration system that can provide both voltage and current pulses. There are also two internal 10 bit ADCs for the monitoring of the internal bias references. The digital logic provides trigger generation, digital data tagging and storage, data formatting and data packet transmission with error protection on 320Mbps e-link. The digital design is triplicated in order to improve the radiation hardness of the system. A first run of the chip of 9.1×6.1mm2 in 130nm technology node has been submitted and produced. Chip architecture, measurements and characterization of the calibration, bias and monitoring system will be shown.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131830170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974264
L. D. Benedetto, G. Licciardo, A. Rubino
In this paper we report the experimental results of lateral 4H-SiC UV p-i-n photodiodes, whose p-type anode and n-type cathode regions are made by Aluminum and Nitrogen, respectively, ion-implantation. The dark reverse current is −31.5pA at −10V and increases at −1.24nA under 320nm UV radiation with an optical power at the surface of the device equal to 7.5nW. The peak of the responsivity is 0.074A/W at 0V and 0.169AAV at −10V for 320nm, corresponding to an external quantum efficiency of, respectively, 30% and 69%. Respect to other proposed photodiodes, our devices are fully compatible with standard 4H-SiC device process fabrication and they can be easily integrated in an electronic circuit.
{"title":"Experimental results on lateral 4H-SiC UV photodiodes","authors":"L. D. Benedetto, G. Licciardo, A. Rubino","doi":"10.1109/IWASI.2017.7974264","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974264","url":null,"abstract":"In this paper we report the experimental results of lateral 4H-SiC UV p-i-n photodiodes, whose p-type anode and n-type cathode regions are made by Aluminum and Nitrogen, respectively, ion-implantation. The dark reverse current is −31.5pA at −10V and increases at −1.24nA under 320nm UV radiation with an optical power at the surface of the device equal to 7.5nW. The peak of the responsivity is 0.074A/W at 0V and 0.169AAV at −10V for 320nm, corresponding to an external quantum efficiency of, respectively, 30% and 69%. Respect to other proposed photodiodes, our devices are fully compatible with standard 4H-SiC device process fabrication and they can be easily integrated in an electronic circuit.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130366363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974255
G. Licciardo, Carmine Cappetta, L. D. Benedetto
A new Application Specific Image Processor for the enhancement of the dynamic range of medical images is presented, capable to process images at different resolutions up to 4K. An algorithm has been derived, adapted and tailored for the specific hardware design, in order to adapt the complexity of the processor to required performances or to constraints of different field programmable platforms. The proposed design achieves such results by the reduction of frame buffer elimination that reduces the amount of memory for processing and allows the implementation of smart image sensors. The implemented design returns state-of-the-art performances for both FPGA and std_cell implementation.
{"title":"Dynamic range enhancement for medical image processing","authors":"G. Licciardo, Carmine Cappetta, L. D. Benedetto","doi":"10.1109/IWASI.2017.7974255","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974255","url":null,"abstract":"A new Application Specific Image Processor for the enhancement of the dynamic range of medical images is presented, capable to process images at different resolutions up to 4K. An algorithm has been derived, adapted and tailored for the specific hardware design, in order to adapt the complexity of the processor to required performances or to constraints of different field programmable platforms. The proposed design achieves such results by the reduction of frame buffer elimination that reduces the amount of memory for processing and allows the implementation of smart image sensors. The implemented design returns state-of-the-art performances for both FPGA and std_cell implementation.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124964785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-06-01DOI: 10.1109/IWASI.2017.7974247
Jorge Marin, E. Sacco, Johan Vergauwen, G. Gielen
This paper presents the drift analysis and improvement of integrated resistive sensor interfaces, focusing on BBPLL-based architectures. This architecture is intrinsically resilient to drift generated by environmental and circuit degradation effects due to its time-domain and highly-digital implementation. Nevertheless, for applications aiming at nearly zero drift, non-ideal effects resulting from mismatch and nonlinearity are still creating residual drift. Two proposed feedback mechanisms are studied under non-ideal circuit conditions. System-level analysis and simulations predict the remaining output error when the main non-ideal effects produced by environmental changes and circuit degradation occur. The chopping technique is included in the analysis as a drift-compensation mechanism. This technique fits well with a single-ended bridge to effectively remove drift effects. The results show that the drift error due to mismatch is attenuated within ±0.05% of the full scale, corresponding to a 10X improvement with respect to previous publications.
{"title":"Analysis and modeling of drift-resilient time-based integrated resistive sensor interfaces","authors":"Jorge Marin, E. Sacco, Johan Vergauwen, G. Gielen","doi":"10.1109/IWASI.2017.7974247","DOIUrl":"https://doi.org/10.1109/IWASI.2017.7974247","url":null,"abstract":"This paper presents the drift analysis and improvement of integrated resistive sensor interfaces, focusing on BBPLL-based architectures. This architecture is intrinsically resilient to drift generated by environmental and circuit degradation effects due to its time-domain and highly-digital implementation. Nevertheless, for applications aiming at nearly zero drift, non-ideal effects resulting from mismatch and nonlinearity are still creating residual drift. Two proposed feedback mechanisms are studied under non-ideal circuit conditions. System-level analysis and simulations predict the remaining output error when the main non-ideal effects produced by environmental changes and circuit degradation occur. The chopping technique is included in the analysis as a drift-compensation mechanism. This technique fits well with a single-ended bridge to effectively remove drift effects. The results show that the drift error due to mismatch is attenuated within ±0.05% of the full scale, corresponding to a 10X improvement with respect to previous publications.","PeriodicalId":332606,"journal":{"name":"2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126912638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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