Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405496
Obaidallah Elshafiey, T. A. Latef
Passive radar systems are used to detect targets in various applications by analyzing the acquired reflected signals. This paper presents a design of passive radar that can operate with signals transmitted from various commercial broadcast and communication systems. Vivaldi antenna structure is designed using CST Microwave studio environment to provide wideband characteristics. A phased array of this antenna is developed to allow digital beamforming to differentiate between direct source and target reflected signals. Signal processing scheme is investigated using Simulink environment to correlated source and target signals. Target range and velocity are estimated based on delay and Doppler shift in the received signal. Analysis revealed that more than one target can be identified using the developed system.
{"title":"Design of wideband passive radar system","authors":"Obaidallah Elshafiey, T. A. Latef","doi":"10.1109/ISCAIE.2018.8405496","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405496","url":null,"abstract":"Passive radar systems are used to detect targets in various applications by analyzing the acquired reflected signals. This paper presents a design of passive radar that can operate with signals transmitted from various commercial broadcast and communication systems. Vivaldi antenna structure is designed using CST Microwave studio environment to provide wideband characteristics. A phased array of this antenna is developed to allow digital beamforming to differentiate between direct source and target reflected signals. Signal processing scheme is investigated using Simulink environment to correlated source and target signals. Target range and velocity are estimated based on delay and Doppler shift in the received signal. Analysis revealed that more than one target can be identified using the developed system.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124846355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405508
S. Ismail, A. R. Zainal, A. Mustapha
Mushrooms have high benefits in the human body. However, not all mushrooms are edible. While some have medical properties to cure cancer, some other types of mushrooms may contain viruses that carry infectious diseases. This paper is set to study mushroom behavioural features such as the shape, surface and colour of the cap, gill and stalk, as well as the odour, population and habitat of the mushrooms. The Principal Component Analysis (PCA) algorithm is used for selecting the best features for the classification experiment using Decision Tree (DT) algorithm. The classification accuracy, coefficient metric, and time taken to build a classification model on a standard Mushroom dataset were measured. The behavioural feature of ‘odour’ was selected as the highest ranked feature that contribute to the high classification accuracy.
{"title":"Behavioural features for mushroom classification","authors":"S. Ismail, A. R. Zainal, A. Mustapha","doi":"10.1109/ISCAIE.2018.8405508","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405508","url":null,"abstract":"Mushrooms have high benefits in the human body. However, not all mushrooms are edible. While some have medical properties to cure cancer, some other types of mushrooms may contain viruses that carry infectious diseases. This paper is set to study mushroom behavioural features such as the shape, surface and colour of the cap, gill and stalk, as well as the odour, population and habitat of the mushrooms. The Principal Component Analysis (PCA) algorithm is used for selecting the best features for the classification experiment using Decision Tree (DT) algorithm. The classification accuracy, coefficient metric, and time taken to build a classification model on a standard Mushroom dataset were measured. The behavioural feature of ‘odour’ was selected as the highest ranked feature that contribute to the high classification accuracy.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130427781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405458
Excel B. Villanueva, Ruji P. Medina, B. Gerardo
RC5 algorithm is lighweight in nature because it has low memory and low power requirement which makes it suitable to be implemented in devices with limited power and memory supply. However, it suffers from slow encryption speed compared to other encryption algorithms. The main purpose of this paper is to enhance this algorithm to increase its encryption speed through a simple yet fast random number addition-then-append key expansion technique. The enhancement includes the generation of random number to be added to the generated key which will be repeated for two rounds and later to be appended, to produce a key material. Additional blocks and bitwise operations are also included in the enhancement. Results show that the enhanced RC5 (ERC5) algorithm positively outperforms the traditional RC5 algorithm and successfully increased its encryption speed.
{"title":"An enhanced RC5 (ERC5) algorithm based on simple random number key expansion technique","authors":"Excel B. Villanueva, Ruji P. Medina, B. Gerardo","doi":"10.1109/ISCAIE.2018.8405458","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405458","url":null,"abstract":"RC5 algorithm is lighweight in nature because it has low memory and low power requirement which makes it suitable to be implemented in devices with limited power and memory supply. However, it suffers from slow encryption speed compared to other encryption algorithms. The main purpose of this paper is to enhance this algorithm to increase its encryption speed through a simple yet fast random number addition-then-append key expansion technique. The enhancement includes the generation of random number to be added to the generated key which will be repeated for two rounds and later to be appended, to produce a key material. Additional blocks and bitwise operations are also included in the enhancement. Results show that the enhanced RC5 (ERC5) algorithm positively outperforms the traditional RC5 algorithm and successfully increased its encryption speed.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125172398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405493
Chi Qin Lai, H. Ibrahim, M. Abdullah, J. Abdullah, S. A. Suandi, A. Azman
Electroencephalogram (EEG) is a signal collected from the human brain to study and analyze the brain activities. However, raw EEG may be contaminated with unwanted components such as noises and artifacts caused by power source, environment, eye blinks, heart rate and muscle movements, which are unavoidable. These unwanted components will effect the analysis of EEG and provide inaccurate information. Therefore, researchers have proposed all kind of approaches to eliminate unwanted noises and artifacts from EEG. In this paper, a literature review is carried out to study the works that have been done for noise and artifact removal from year 2010 up to the present. It is found that conventional approaches include ICA, wavelet based analysis, statistical analysis and others. However, the existing ways of artifacts removal cannot eliminate certain noise and will cause information lost by directly discard the contaminated components. From the study, it is shown that combination of conventional with other methods is popularly used, as it is able to improve the removal of artifacts. The current trend of artifacts removal makes use of machine learning to provide an automated solution with higher efficiency.
{"title":"Artifacts and noise removal for electroencephalogram (EEG): A literature review","authors":"Chi Qin Lai, H. Ibrahim, M. Abdullah, J. Abdullah, S. A. Suandi, A. Azman","doi":"10.1109/ISCAIE.2018.8405493","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405493","url":null,"abstract":"Electroencephalogram (EEG) is a signal collected from the human brain to study and analyze the brain activities. However, raw EEG may be contaminated with unwanted components such as noises and artifacts caused by power source, environment, eye blinks, heart rate and muscle movements, which are unavoidable. These unwanted components will effect the analysis of EEG and provide inaccurate information. Therefore, researchers have proposed all kind of approaches to eliminate unwanted noises and artifacts from EEG. In this paper, a literature review is carried out to study the works that have been done for noise and artifact removal from year 2010 up to the present. It is found that conventional approaches include ICA, wavelet based analysis, statistical analysis and others. However, the existing ways of artifacts removal cannot eliminate certain noise and will cause information lost by directly discard the contaminated components. From the study, it is shown that combination of conventional with other methods is popularly used, as it is able to improve the removal of artifacts. The current trend of artifacts removal makes use of machine learning to provide an automated solution with higher efficiency.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115518438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405506
Boon-Chiao Chang, B. Goi, R. Phan, W. Lee
Multiplication plays an important role in scientific computing and cryptography. When the size of multiplicands grow large (e.g. more than 100K-bit), the multiplication process become time consuming. In this paper, we present implementation techniques to multiply very large integer in state of the art GPU architecture. The implementation relies on Number Theoretic Transform with 64-bit prime. The implementation results show that multiplication of 768K-bit integer takes 1.37 milliseconds on GTX1070 (GPU with Pascal architecture). The work presented in this paper can be used to implement various advanced cryptosystem, including Homomorphic Encryption and Lattice based cryptography.
{"title":"Multiplying very large integer in GPU with pascal architecture","authors":"Boon-Chiao Chang, B. Goi, R. Phan, W. Lee","doi":"10.1109/ISCAIE.2018.8405506","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405506","url":null,"abstract":"Multiplication plays an important role in scientific computing and cryptography. When the size of multiplicands grow large (e.g. more than 100K-bit), the multiplication process become time consuming. In this paper, we present implementation techniques to multiply very large integer in state of the art GPU architecture. The implementation relies on Number Theoretic Transform with 64-bit prime. The implementation results show that multiplication of 768K-bit integer takes 1.37 milliseconds on GTX1070 (GPU with Pascal architecture). The work presented in this paper can be used to implement various advanced cryptosystem, including Homomorphic Encryption and Lattice based cryptography.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122993597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405457
M. Ati, Kamil Kabir, H. Abdullahi, Masud Ahmed
Learning to write can be exhausting for young children. In Traditional teaching, children with a different learning abilities are taught with the same rubric. This, in turn, impacts children that need extra attention to catch up with their pairs, which leads children to suffer right from the early learning stages. Traditional teaching methods also are so rigid that makes them unable to automatically identify those children with less abilities and in need of extra work. Hence, with the rapid development of ICT, an innovative learning methods are sought to be important to allow children to be taught with different rubrics. The aim of this research is to improve learning process for pre-school children via introducing Augmented Reality (AR) in the process which, in turn, simplify the learning process as well as identifying children abilities. The research introduces gamification to the process in order to ease the burden on children. Furthermore, we are trying to involve both school as well home to be part of the educational cycle that makes parents to be part of the learning/educational process of their young children. Augmented reality combined with pleasing sound make the learning more interactive and enjoyable. The outcome of this research also helps parents to keep track of their children's learning. The paper also describes the deployment of the application in a local schools as a pilot study so teachers can get feedback on student's learning curve and to fine tune the work further.
{"title":"Augmented reality enhanced computer aided learning for young children","authors":"M. Ati, Kamil Kabir, H. Abdullahi, Masud Ahmed","doi":"10.1109/ISCAIE.2018.8405457","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405457","url":null,"abstract":"Learning to write can be exhausting for young children. In Traditional teaching, children with a different learning abilities are taught with the same rubric. This, in turn, impacts children that need extra attention to catch up with their pairs, which leads children to suffer right from the early learning stages. Traditional teaching methods also are so rigid that makes them unable to automatically identify those children with less abilities and in need of extra work. Hence, with the rapid development of ICT, an innovative learning methods are sought to be important to allow children to be taught with different rubrics. The aim of this research is to improve learning process for pre-school children via introducing Augmented Reality (AR) in the process which, in turn, simplify the learning process as well as identifying children abilities. The research introduces gamification to the process in order to ease the burden on children. Furthermore, we are trying to involve both school as well home to be part of the educational cycle that makes parents to be part of the learning/educational process of their young children. Augmented reality combined with pleasing sound make the learning more interactive and enjoyable. The outcome of this research also helps parents to keep track of their children's learning. The paper also describes the deployment of the application in a local schools as a pilot study so teachers can get feedback on student's learning curve and to fine tune the work further.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130820209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-01DOI: 10.1109/ISCAIE.2018.8405479
Hani Alrifai, Yamen Hatahet, Sirine Dhaouadi, F. Almabrouk, L. Albasha, H. Mir
This paper presents the implementation of a frequency synthesizer based on a Phase Locked Loop (PLL) system for an architecture that aims to miniaturize a digital radar test bed previously implemented using discrete microwave components. The designed synthesizer was capable of providing three distinct frequencies of 800 MHz, 2.0 GHz, and 2.4 GHz to respective chips of a digital radar system while minimizing the number of components needed. The paper focuses on obtaining the three distinct frequencies from a single PLL and frequency divider circuits. The issues caused by the loading of chips are addressed, allowing the three frequencies to be fed to 18 different chips. The final result consists of a PLL connected to an integrated circuits of dividers to output the three frequencies.
{"title":"Frequency synthesizer system implementation for digital radar","authors":"Hani Alrifai, Yamen Hatahet, Sirine Dhaouadi, F. Almabrouk, L. Albasha, H. Mir","doi":"10.1109/ISCAIE.2018.8405479","DOIUrl":"https://doi.org/10.1109/ISCAIE.2018.8405479","url":null,"abstract":"This paper presents the implementation of a frequency synthesizer based on a Phase Locked Loop (PLL) system for an architecture that aims to miniaturize a digital radar test bed previously implemented using discrete microwave components. The designed synthesizer was capable of providing three distinct frequencies of 800 MHz, 2.0 GHz, and 2.4 GHz to respective chips of a digital radar system while minimizing the number of components needed. The paper focuses on obtaining the three distinct frequencies from a single PLL and frequency divider circuits. The issues caused by the loading of chips are addressed, allowing the three frequencies to be fed to 18 different chips. The final result consists of a PLL connected to an integrated circuits of dividers to output the three frequencies.","PeriodicalId":333327,"journal":{"name":"2018 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133580340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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