Martin Hilscher, M. Braun, Michael Richter, A. Leininger, M. Gössel
In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are driven by a clock which is k times faster than the slower test clock of the scan chains. For each test clock cycle only one out of the k different outputs of each shift register is evaluated by the ATE. To mitigate the negative effects of consecutive X values within the scan chains, a permutation of the NF-MISR inputs is periodically applied. Thus, no additional external control signals or test set dependent control logic is required. The possibilities of an implementation on a Verigy ATE will be described. The presented results for three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial ATPG tool.
{"title":"Accelerated Shift Registers for X-tolerant Test Data Compaction","authors":"Martin Hilscher, M. Braun, Michael Richter, A. Leininger, M. Gössel","doi":"10.1109/ETS.2008.38","DOIUrl":"https://doi.org/10.1109/ETS.2008.38","url":null,"abstract":"In this paper we present a method for compacting test response data without the need for additional X-masking logic by using the timing flexibility of modern automatic test equipment (ATE). In our design the test response is compacted by several multiple input shift registers without feedback (NF-MISR). The shift registers are driven by a clock which is k times faster than the slower test clock of the scan chains. For each test clock cycle only one out of the k different outputs of each shift register is evaluated by the ATE. To mitigate the negative effects of consecutive X values within the scan chains, a permutation of the NF-MISR inputs is periodically applied. Thus, no additional external control signals or test set dependent control logic is required. The possibilities of an implementation on a Verigy ATE will be described. The presented results for three industrial circuits demonstrate the effectiveness of the proposed approach in comparison to a commercial ATPG tool.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128256081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. D. Natale, M. Doulcier, M. Flottes, B. Rouzeyre
In this paper we propose an on-line self-test architecture for hardware implementations of advanced encryption standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with respect to side-channel attacks based on power analysis.
{"title":"A Reliable Architecture for the Advanced Encryption Standard","authors":"G. D. Natale, M. Doulcier, M. Flottes, B. Rouzeyre","doi":"10.1109/ETS.2008.26","DOIUrl":"https://doi.org/10.1109/ETS.2008.26","url":null,"abstract":"In this paper we propose an on-line self-test architecture for hardware implementations of advanced encryption standard (AES). The solution assumes a parallel architecture and exploits the inherent spatial replications of this implementation. We show that our solution is very effective for on-line fault detection while keeping the area overhead very low. Moreover, it does not weak the device with respect to side-channel attacks based on power analysis.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125490720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, B. Becker
We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects.
{"title":"A Simulator of Small-Delay Faults Caused by Resistive-Open Defects","authors":"A. Czutro, N. Houarche, P. Engelke, I. Polian, M. Comte, M. Renovell, B. Becker","doi":"10.1109/ETS.2008.19","DOIUrl":"https://doi.org/10.1109/ETS.2008.19","url":null,"abstract":"We present a simulator which determines the coverage of small-delay faults, i.e., delay faults with a size below one clock cycle, caused by resistive-open defects. These defects are likely to escape detection by stuck-at or transition fault patterns. For the first time, we couple the calculation of the critical size of a small-delay fault with the computation of the resistance range of the corresponding resistive-open defect for which this size is exceeded. By doing so, we are able to extend probabilistic fault coverage metrics initially developed for static resistive bridging faults to small-delay defects.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125510653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in PSL. Other contributions of the paper are methodology for direct conversion of PSL properties to HLDD and HLDD-based simulator modification for assertions checking support. Experimental results show the feasibility and efficiency of the proposed approach.
{"title":"Temporally Extended High-Level Decision Diagrams for PSL Assertions Simulation","authors":"M. Jenihhin, J. Raik, A. Chepurov, R. Ubar","doi":"10.1109/ETS.2008.22","DOIUrl":"https://doi.org/10.1109/ETS.2008.22","url":null,"abstract":"The paper proposes a novel method for PSL language assertions simulation-based checking. The method uses a system representation model called High-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and convenient for diagnosis and debug. The presented approach proposes a temporal extension for the existing HLDD model aimed at supporting temporal properties expressed in PSL. Other contributions of the paper are methodology for direct conversion of PSL properties to HLDD and HLDD-based simulator modification for assertions checking support. Experimental results show the feasibility and efficiency of the proposed approach.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"1948 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129248999","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For fault models with large numbers of faults, such as bridging faults, fault collapsing based on dominance relations can be effective in reducing the test generation time by reducing the number of target faults. When dominance relations are used for fault collapsing, a fault fj is excluded from the set of target faults F if it dominates a fault fi in F. However, if fi remains undetected after test generation, fj may remain undetected as well. We define safe fault collapsing to address this issue. For safe fault collapsing with a parameter s, fj is excluded from the set of target faults F only if fj dominates at least s faults fi1, fi2, hellip ,f is in F. In this way, if any of the s faults dominated by fj is detected, fj will be detected as well. A higher value of s increases the likelihood of detecting fj without targeting it. We describe a procedure for computing safe collapsed fault sets, and present experimental results of test generation for four-way bridging faults.
{"title":"Safe Fault Collapsing Based on Dominance Relations","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ETS.2008.11","DOIUrl":"https://doi.org/10.1109/ETS.2008.11","url":null,"abstract":"For fault models with large numbers of faults, such as bridging faults, fault collapsing based on dominance relations can be effective in reducing the test generation time by reducing the number of target faults. When dominance relations are used for fault collapsing, a fault f<sub>j</sub> is excluded from the set of target faults F if it dominates a fault f<sub>i</sub> in F. However, if f<sub>i</sub> remains undetected after test generation, f<sub>j</sub> may remain undetected as well. We define safe fault collapsing to address this issue. For safe fault collapsing with a parameter s, f<sub>j</sub> is excluded from the set of target faults F only if f<sub>j</sub> dominates at least s faults f<sub>i1,</sub> f<sub>i2</sub>, hellip ,f <sub>is</sub> in F. In this way, if any of the s faults dominated by f<sub>j</sub> is detected, f<sub>j</sub> will be detected as well. A higher value of s increases the likelihood of detecting f<sub>j</sub> without targeting it. We describe a procedure for computing safe collapsed fault sets, and present experimental results of test generation for four-way bridging faults.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129781149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Aldrete-Vidrio, M. Salhi, J. Altet, S. Grauby, D. Mateo, H. Michel, L. Clerjaud, J. Rampnoux, A. Rubio, W. Claeys, S. Dilhaire
The power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements on the silicon surface. In this paper, the frequency response of a RF LNA is observed by measuring spectral components of the sensed temperature. Results prove that temperature can be used to debug and observe figures of merit of analog blocks in a RFIC. Experimental measurements have been done in a 0.25 mum CMOS process. Laser probing techniques have been used as temperature sensors; specifically, a thermoreflectometer and a Michaelson interferometer.
集成电路器件的功耗可以被认为是电路性能的标志。在不干扰电路运行的情况下，这种功耗可以通过硅表面的温度测量来监测。本文通过测量被测温度的频谱分量来观察射频LNA的频率响应。结果表明，温度可以用来调试和观察RFIC中模拟模块的性能值。在0.25 μ m CMOS工艺中进行了实验测量。激光探测技术已被用作温度传感器;具体来说，是一个热反射计和一个迈克尔逊干涉仪。
{"title":"Using Temperature as Observable of the Frequency Response of RF CMOS Amplifiers","authors":"E. Aldrete-Vidrio, M. Salhi, J. Altet, S. Grauby, D. Mateo, H. Michel, L. Clerjaud, J. Rampnoux, A. Rubio, W. Claeys, S. Dilhaire","doi":"10.1109/ETS.2008.15","DOIUrl":"https://doi.org/10.1109/ETS.2008.15","url":null,"abstract":"The power dissipated by the devices of an integrated circuit can be considered a signature of the circuit's performance. Without disturbing the circuit operation, this power consumption can be monitored by temperature measurements on the silicon surface. In this paper, the frequency response of a RF LNA is observed by measuring spectral components of the sensed temperature. Results prove that temperature can be used to debug and observe figures of merit of analog blocks in a RFIC. Experimental measurements have been done in a 0.25 mum CMOS process. Laser probing techniques have been used as temperature sensors; specifically, a thermoreflectometer and a Michaelson interferometer.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129075278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniele Rossi, Paolo Angelini, C. Metra, G. Campardo, G. Vanalli
We analyze the electrical phenomena that can affect the integrity of the communication among different chips within a system in package (SiP). We address these issues for a real case, for which electrical parameters are extracted from layout and used to build a netlist employed for electrical characterization. We show that crosstalk, and in particular inductive crosstalk, is the electrical phenomenon mainly affecting signal transmission within the SiP. Then, we evaluate the kinds of errors that can be originated. We show that errors caused by inductive coupling among SiP interconnects can be unidirectional only, thus allowing designers to implement error control coding techniques based on all unidirectional error detecting codes. This allows significant cost reduction over the alternate use of non-unidirectional error detecting codes.
{"title":"Risks for Signal Integrity in System in Package and Possible Remedies","authors":"Daniele Rossi, Paolo Angelini, C. Metra, G. Campardo, G. Vanalli","doi":"10.1109/ETS.2008.23","DOIUrl":"https://doi.org/10.1109/ETS.2008.23","url":null,"abstract":"We analyze the electrical phenomena that can affect the integrity of the communication among different chips within a system in package (SiP). We address these issues for a real case, for which electrical parameters are extracted from layout and used to build a netlist employed for electrical characterization. We show that crosstalk, and in particular inductive crosstalk, is the electrical phenomenon mainly affecting signal transmission within the SiP. Then, we evaluate the kinds of errors that can be originated. We show that errors caused by inductive coupling among SiP interconnects can be unidirectional only, thus allowing designers to implement error control coding techniques based on all unidirectional error detecting codes. This allows significant cost reduction over the alternate use of non-unidirectional error detecting codes.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114705003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an improved stimulus identification algorithm for histogram-based A/D converter testing. The mathematical theory behind the improvements is described and simulation results supporting this theory are presented. The stimulus identification method enables the linearity of ADCs to be tested without a highly linear or pure test stimulus. Simulations predict that the INL of 16-b ADCs can be measured with an accuracy of 0.5 LSB using only a 75 dBc pure sinusoidal test stimulus, whereas the standardized histogram test method requires a pure test stimulus of over 105 dBc.
{"title":"An Improved Algorithm to Identify the Test Stimulus in Histogram-Based A/D Converter Testing","authors":"Esa Korhonen, J. Kostamovaara","doi":"10.1109/ETS.2008.17","DOIUrl":"https://doi.org/10.1109/ETS.2008.17","url":null,"abstract":"This paper presents an improved stimulus identification algorithm for histogram-based A/D converter testing. The mathematical theory behind the improvements is described and simulation results supporting this theory are presented. The stimulus identification method enables the linearity of ADCs to be tested without a highly linear or pure test stimulus. Simulations predict that the INL of 16-b ADCs can be measured with an accuracy of 0.5 LSB using only a 75 dBc pure sinusoidal test stimulus, whereas the standardized histogram test method requires a pure test stimulus of over 105 dBc.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124157862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Christian G. Zoellin, H. Wunderlich, I. Polian, B. Becker
Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.
{"title":"Selective Hardening in Early Design Steps","authors":"Christian G. Zoellin, H. Wunderlich, I. Polian, B. Becker","doi":"10.1109/ETS.2008.30","DOIUrl":"https://doi.org/10.1109/ETS.2008.30","url":null,"abstract":"Hardening a circuit against soft errors should be performed in early design steps before the circuit is laid out. A viable approach to achieve soft error rate (SER) reduction at a reasonable cost is to harden only parts of a circuit. When selecting which locations in the circuit to harden, priority should be given to critical spots for which an error is likely to cause a system malfunction. The criticality of the spots depends on parameters not all available in early design steps. We employ a selection strategy which takes only gate-level information into account and does not use any low-level electrical or timing information. We validate the quality of the solution using an accurate SER estimator based on the new UGC particle strike model. Although only partial information is utilized for hardening, the exact validation shows that the susceptibility of a circuit to soft errors is reduced significantly. The results of the hardening strategy presented are also superior to known purely topological strategies in terms of both hardware overhead and protection.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125259640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jitter impairs the bit-error rate in high-speed communication systems. Jitter decomposition is important for accurately deriving the total jitter in a system and for aiding in identifying the root causes of jitter. We extend a previous approach for jitter decomposition in clock signals is to enable separation of correlated and uncorrelated jitter in both data and clock signals. We use time lag correlation functions with special test patterns to estimate the characteristic parameters of different jitter components such as peak-to-peak value of DDJ and RMS value of RJ. Our approach can be implemented using only one-shot capture instead of multiple captures to average out the uncorrelated jitter from the correlated jitter. Hardware measurements are presented to validate the proposed technique.
{"title":"Jitter Decomposition in High-Speed Communication Systems","authors":"Qingqi Dou, J. Abraham","doi":"10.1109/ETS.2008.35","DOIUrl":"https://doi.org/10.1109/ETS.2008.35","url":null,"abstract":"Jitter impairs the bit-error rate in high-speed communication systems. Jitter decomposition is important for accurately deriving the total jitter in a system and for aiding in identifying the root causes of jitter. We extend a previous approach for jitter decomposition in clock signals is to enable separation of correlated and uncorrelated jitter in both data and clock signals. We use time lag correlation functions with special test patterns to estimate the characteristic parameters of different jitter components such as peak-to-peak value of DDJ and RMS value of RJ. Our approach can be implemented using only one-shot capture instead of multiple captures to average out the uncorrelated jitter from the correlated jitter. Hardware measurements are presented to validate the proposed technique.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122342021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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