Convolutional coding is usually exploited to protect data transmitted over channels, where they are more susceptible to errors. However in recent years, an increasing interest has been drawn to the problem of radiation-induced temporary faults, also called soft errors, which corrupt memory content even during the normal functioning of a system. In this paper, a mitigation technique for the protection of critical data in electronic devices from transient errors that manifest themselves as bit-flips in memory is proposed. In order to cope with this problem we take advantage of convolutional codes and we introduce two architectures to protect memory content with little area and performance overheads. A coding-decoding scheme implemented using sequential logic. The encoding is performed as in classical convolutional encoding, processing the input stream with a shift-register based architecture. The decoder, however, differs from classical decoding schemes in terms of complexity.
{"title":"Convolutional Coding for SEU mitigation","authors":"L. Frigerio, Matteo Alan Radaelli, F. Salice","doi":"10.1109/ETS.2008.32","DOIUrl":"https://doi.org/10.1109/ETS.2008.32","url":null,"abstract":"Convolutional coding is usually exploited to protect data transmitted over channels, where they are more susceptible to errors. However in recent years, an increasing interest has been drawn to the problem of radiation-induced temporary faults, also called soft errors, which corrupt memory content even during the normal functioning of a system. In this paper, a mitigation technique for the protection of critical data in electronic devices from transient errors that manifest themselves as bit-flips in memory is proposed. In order to cope with this problem we take advantage of convolutional codes and we introduce two architectures to protect memory content with little area and performance overheads. A coding-decoding scheme implemented using sequential logic. The encoding is performed as in classical convolutional encoding, processing the input stream with a shift-register based architecture. The decoder, however, differs from classical decoding schemes in terms of complexity.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129592940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system test. The application of test algorithms for SRAM memories to cache memories thus requires opportune transformations. In this paper we present a procedure to adapt traditional march tests to testing the data and the directory array of k-way set-associative cache memories with LRU replacement. The basic idea is to translate each march test operation into an equivalent sequence of cache operations able to reproduce the desired marching sequence into the data and the directory array of the cache.
{"title":"Applying March Tests to K-Way Set-Associative Cache Memories","authors":"S. Alpe, S. Carlo, P. Prinetto, A. Savino","doi":"10.1109/ETS.2008.25","DOIUrl":"https://doi.org/10.1109/ETS.2008.25","url":null,"abstract":"Embedded microprocessor cache memories suffer from limited observability and controllability creating problems during in-system test. The application of test algorithms for SRAM memories to cache memories thus requires opportune transformations. In this paper we present a procedure to adapt traditional march tests to testing the data and the directory array of k-way set-associative cache memories with LRU replacement. The basic idea is to translate each march test operation into an equivalent sequence of cache operations able to reproduce the desired marching sequence into the data and the directory array of the cache.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125998818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article describes an analog test bus infrastructure as a straightforward approach to grant the accessibility to embedded RF or Analog modules in core-based design. This DfT method increases the testability and provides debug/diagnosis facilities. The standardized analog test bus architecture is suited for an automated test development flow. In addition, the entire infrastructure is to a large extent reusable, through its design independence. This industrially innovative and practical approach has been applied to several products within our company, and two RF chips are chosen to illustrate its benefits.
{"title":"Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design","authors":"V. Zivkovic, F. Heyden, G. Gronthoud, F. Jong","doi":"10.1109/ETS.2008.18","DOIUrl":"https://doi.org/10.1109/ETS.2008.18","url":null,"abstract":"This article describes an analog test bus infrastructure as a straightforward approach to grant the accessibility to embedded RF or Analog modules in core-based design. This DfT method increases the testability and provides debug/diagnosis facilities. The standardized analog test bus architecture is suited for an automated test development flow. In addition, the entire infrastructure is to a large extent reusable, through its design independence. This industrially innovative and practical approach has been applied to several products within our company, and two RF chips are chosen to illustrate its benefits.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132833331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. S. Khursheed, P. Rosinger, B. Al-Hashimi, S. Reddy, P. Harrod
Multiple-voltage is an effective dynamic power reduction design technique, commonly used in low power ICs. To the best of our knowledge there is no reported work for diagnosing multiple-Vdd enabled ICs and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. Using synthesized ISCAS benchmarks, with realistic extracted bridges and parametric fault model; the paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multi-Vdd diagnosis algorithm.
{"title":"Bridge Defect Diagnosis for Multiple-Voltage Design","authors":"S. S. Khursheed, P. Rosinger, B. Al-Hashimi, S. Reddy, P. Harrod","doi":"10.1109/ETS.2008.14","DOIUrl":"https://doi.org/10.1109/ETS.2008.14","url":null,"abstract":"Multiple-voltage is an effective dynamic power reduction design technique, commonly used in low power ICs. To the best of our knowledge there is no reported work for diagnosing multiple-Vdd enabled ICs and the aim of this paper is to propose a method for diagnosing bridge defects in such ICs. Using synthesized ISCAS benchmarks, with realistic extracted bridges and parametric fault model; the paper investigates the impact of varying supply voltage on the accuracy of diagnosis and demonstrates how the additional voltage settings can be leveraged to improve the diagnosis resolution through a novel multi-Vdd diagnosis algorithm.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"733 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132229038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso
This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing. The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90 nm technology.
{"title":"An Innovative and Low-Cost Industrial Flow for Reliability Characterization of SoCs","authors":"D. Appello, P. Bernardi, R. Cagliesi, M. Giancarlini, M. Grosso","doi":"10.1109/ETS.2008.27","DOIUrl":"https://doi.org/10.1109/ETS.2008.27","url":null,"abstract":"This paper describes a novel approach to enhance the process of reliability characterization for VLSI SoC products. To do this, we exploit Design for Test and Diagnosis structures in combination with new low-cost tester features and architecture. The main focus of our work is to obtain a modeling of the degradation of selected parameters measurable through at-speed testing. The paper reviews the current approach for reliability characterization and shows the achieved enhancement on efficiency and effectiveness. Results shown are related to experiments run on a vehicle released on a 90 nm technology.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"63 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132604907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Senguttuvan, H. Choi, Donghoon Han, A. Chatterjee
Frequency modulation is used in many important communication and wireless applications. A key defining characteristic of frequency modulated systems is the constant amplitude of the transmitted signal making it impossible to use envelope-based built-in test (BIT) techniques. In this paper, an efficient BIT technique for such transmitters using lowpass filters is proposed. The proposed BIT technique is low-cost and has minimal impact on RF transmitter performance. It can also be used to efficiently test devices such as voltage-controlled oscillators (VCOs), phase locked loops (PLL) etc through frequency discrimination. Simulation results and hardware measurements demonstrate the feasibility of the proposed approach.
{"title":"Built-in Test of Frequency Modulated RF Transmitters Using Embedded Low-Pass Filters","authors":"R. Senguttuvan, H. Choi, Donghoon Han, A. Chatterjee","doi":"10.1109/ETS.2008.33","DOIUrl":"https://doi.org/10.1109/ETS.2008.33","url":null,"abstract":"Frequency modulation is used in many important communication and wireless applications. A key defining characteristic of frequency modulated systems is the constant amplitude of the transmitted signal making it impossible to use envelope-based built-in test (BIT) techniques. In this paper, an efficient BIT technique for such transmitters using lowpass filters is proposed. The proposed BIT technique is low-cost and has minimal impact on RF transmitter performance. It can also be used to efficiently test devices such as voltage-controlled oscillators (VCOs), phase locked loops (PLL) etc through frequency discrimination. Simulation results and hardware measurements demonstrate the feasibility of the proposed approach.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129778827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The framework of this article lies in the dynamic management of the reliability in NOR embedded Flash memories (eFlash). The main objective is to build a new reliability management scheme and to predict its efficiency to improve the eFlash reliability using error correction code and redundancy. The originality of the proposed approach relies on the use of a dedicated error correcting code well suited to NOR flash memories operational conditions. This code, named hierarchical code, improves the correction capabilities with a minimal impact on performance and area. The proposed solution furthermore enables selecting different built-in self strategies allowing to tune reliability strategies to the targeted application domain.
{"title":"Hierarchical Code Correction and Reliability Management in Embedded nor Flash Memories","authors":"B. Godard, J. Daga, L. Torres, G. Sassatelli","doi":"10.1109/ETS.2008.21","DOIUrl":"https://doi.org/10.1109/ETS.2008.21","url":null,"abstract":"The framework of this article lies in the dynamic management of the reliability in NOR embedded Flash memories (eFlash). The main objective is to build a new reliability management scheme and to predict its efficiency to improve the eFlash reliability using error correction code and redundancy. The originality of the proposed approach relies on the use of a dedicated error correcting code well suited to NOR flash memories operational conditions. This code, named hierarchical code, improves the correction capabilities with a minimal impact on performance and area. The proposed solution furthermore enables selecting different built-in self strategies allowing to tune reliability strategies to the targeted application domain.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"2002 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129571239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Yuta Yamato, Atsushi Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. Saluja
Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.
{"title":"A Capture-Safe Test Generation Scheme for At-Speed Scan Testing","authors":"X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Yuta Yamato, Atsushi Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K. Saluja","doi":"10.1109/ETS.2008.13","DOIUrl":"https://doi.org/10.1109/ETS.2008.13","url":null,"abstract":"Capture-safety, defined as the avoidance of any timing error due to unduly high launch switching activity in capture mode during at-speed scan testing, is critical for avoiding test- induced yield loss. Although point techniques are available for reducing capture IR-drop, there is a lack of complete capture-safe test generation flows. The paper addresses this problem by proposing a novel and practical capture-safe test generation scheme, featuring (1) reliable capture-safety checking and (2) effective capture-safety improvement by combining X-bit identification & X-filling with low launch- switching-activity test generation. This scheme is compatible with existing ATPG flows, and achieves capture-safety with no changes in the circuit-under-test or the clocking scheme.","PeriodicalId":334529,"journal":{"name":"2008 13th European Test Symposium","volume":"57 15","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113943166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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