This paper deals with one idea to minimize cost of development and test for standard analog IC. At the same time it gives an industrial approach to a method with the aim of optimizing the time-to-market of a whole family of products. This can be implemented without losing the product quality and with the opportunity of proceeding to a fast technical improvement of the family performances. The process methodology, based on array of devices on a single wafer is described. Particular emphasis is given to the design and test phases. A short comparison of virtual cycle time between a conventional standard analog IC and a product following the method is illustrated. An estimation of gain on a voltage references family development, in term of test resources, mask levels and time-to-market is given.
{"title":"Faster time-to-market, lower cost of development and test for standard analog IC","authors":"P. Migliavacca","doi":"10.1109/OLT.2000.856630","DOIUrl":"https://doi.org/10.1109/OLT.2000.856630","url":null,"abstract":"This paper deals with one idea to minimize cost of development and test for standard analog IC. At the same time it gives an industrial approach to a method with the aim of optimizing the time-to-market of a whole family of products. This can be implemented without losing the product quality and with the opportunity of proceeding to a fast technical improvement of the family performances. The process methodology, based on array of devices on a single wafer is described. Particular emphasis is given to the design and test phases. A short comparison of virtual cycle time between a conventional standard analog IC and a product following the method is illustrated. An estimation of gain on a voltage references family development, in term of test resources, mask levels and time-to-market is given.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Rebaudengo, M. Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco
This paper deals with a method able to provide a microprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations which can automatically be applied, thus greatly reducing the cost of designing a safe system, and increasing the confidence in its correctness. Fault Injection experiments have been performed on a sample application using two different systems based on CISC and RISC processors. Results demonstrate that the method effectiveness is rather independent of the adopted platform.
{"title":"Evaluating the effectiveness of a software fault-tolerance technique on RISC- and CISC-based architectures","authors":"M. Rebaudengo, M. Reorda, M. Violante, P. Cheynet, B. Nicolescu, R. Velazco","doi":"10.1109/OLT.2000.856606","DOIUrl":"https://doi.org/10.1109/OLT.2000.856606","url":null,"abstract":"This paper deals with a method able to provide a microprocessor-based system with safety capabilities by modifying the source code of the executed application, only. The method exploits a set of transformations which can automatically be applied, thus greatly reducing the cost of designing a safe system, and increasing the confidence in its correctness. Fault Injection experiments have been performed on a sample application using two different systems based on CISC and RISC processors. Results demonstrate that the method effectiveness is rather independent of the adopted platform.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117241285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Morosov, V. Saposhnikov, V. Saposhnikov, M. Gössel
In this paper a new approach for concurrent checking by Berger codes is proposed. We modify a subset of outputs of the original circuit by adding modulo 2 the outputs of a complementary circuit. In the error free case the unmodified outputs together with their corresponding modified outputs are elements of a Berger code. The number of outputs of the original circuit does not increase. Compared to the traditional method of concurrent checking by Berger codes, a smaller checker is needed.
{"title":"New self-checking circuits by use of Berger-codes","authors":"A. Morosov, V. Saposhnikov, V. Saposhnikov, M. Gössel","doi":"10.1109/OLT.2000.856626","DOIUrl":"https://doi.org/10.1109/OLT.2000.856626","url":null,"abstract":"In this paper a new approach for concurrent checking by Berger codes is proposed. We modify a subset of outputs of the original circuit by adding modulo 2 the outputs of a complementary circuit. In the error free case the unmodified outputs together with their corresponding modified outputs are elements of a Berger code. The number of outputs of the original circuit does not increase. Compared to the traditional method of concurrent checking by Berger codes, a smaller checker is needed.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116914157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Benso, S. Chiusano, G. D. Natale, P. Prinetto, Monica Lobetti Bodoni
In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed on-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed ranging from an external test to an on-line concurrent BIST.
{"title":"A family of self-repair SRAM cores","authors":"A. Benso, S. Chiusano, G. D. Natale, P. Prinetto, Monica Lobetti Bodoni","doi":"10.1109/OLT.2000.856639","DOIUrl":"https://doi.org/10.1109/OLT.2000.856639","url":null,"abstract":"In the present paper a family of BISR SRAM cores is proposed, characterized by a self-repair strategy performed on-line and without user intervention. Moreover, w.r.t. the BISR approaches presented so far, the proposed method is independent from the memory physical layout. In addition to the BISR architecture, to detect the faulty cells to be repaired, a complete set of test solutions is proposed ranging from an external test to an on-line concurrent BIST.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123862079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. A. Sainz, R. Muñoz, J. Maiz, L. A. Aguado, M. Roca
This paper presents an approach for measuring crosstalk interference in digital CMOS VLSI circuits. The crosstalk sensor has been implemented in 0.8 /spl mu/m AMS (Austria Mikro Systeme) technology and its design is based on NOR and NAND RS latches. The interference is produced by an up (down) transition in an affecting line. The crosstalk sensor is designed to measure crosstalk interference amplitude produced by capacitive coupling between long metal lines. The sensor is programmable for measuring some ranges of crosstalk amplitude. The sensor design is based on the dynamic behavior of basic NOR and NAND gates depending on the MOS transistor sizes.
{"title":"A crosstalk sensor implementation for measuring interferences in digital CMOS VLSI circuits","authors":"J. A. Sainz, R. Muñoz, J. Maiz, L. A. Aguado, M. Roca","doi":"10.1109/OLT.2000.856611","DOIUrl":"https://doi.org/10.1109/OLT.2000.856611","url":null,"abstract":"This paper presents an approach for measuring crosstalk interference in digital CMOS VLSI circuits. The crosstalk sensor has been implemented in 0.8 /spl mu/m AMS (Austria Mikro Systeme) technology and its design is based on NOR and NAND RS latches. The interference is produced by an up (down) transition in an affecting line. The crosstalk sensor is designed to measure crosstalk interference amplitude produced by capacitive coupling between long metal lines. The sensor is programmable for measuring some ranges of crosstalk amplitude. The sensor design is based on the dynamic behavior of basic NOR and NAND gates depending on the MOS transistor sizes.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"86 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126284941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper presents a software toolkit that allows one to enhance the fault tolerant characteristics of a user application running under a Windows NT platform through sets of interchangeable and customizable fault tolerant interposition agents (FTI agents). Interposition agents are non-application software programs executed in an intermediate layer between the software application and the operating system in order to "wrap" the application software, intercepting and possibly modifying all the communications between the application and the surrounding hardware and software environment. The process is completely transparent to both the user application and the operating system and allows the achievement of a high degree of software based reliability in a wide variety of domains.
{"title":"A COTS wrapping toolkit for fault tolerant applications under Windows NT","authors":"A. Benso, S. Chiusano, P. Prinetto","doi":"10.1109/OLT.2000.856605","DOIUrl":"https://doi.org/10.1109/OLT.2000.856605","url":null,"abstract":"The paper presents a software toolkit that allows one to enhance the fault tolerant characteristics of a user application running under a Windows NT platform through sets of interchangeable and customizable fault tolerant interposition agents (FTI agents). Interposition agents are non-application software programs executed in an intermediate layer between the software application and the operating system in order to \"wrap\" the application software, intercepting and possibly modifying all the communications between the application and the surrounding hardware and software environment. The process is completely transparent to both the user application and the operating system and allows the achievement of a high degree of software based reliability in a wide variety of domains.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121066501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An online and direct estimator used for measuring the post-decoder error probability of communication links that employ both error control coding and modulation is discussed. The estimator is solely dependent on the information available in the received signal and therefore, it does not require transmission of test patterns. The performance bounds are found using both theoretical analysis and computer simulations. A number of block codes are considered for the analysis and it is shown that the estimation accuracy is best once the link is overlaid with the shortest possible block code.
{"title":"Theoretical performance bounds of a probability of bit error estimator used in digital links employing binary block codes","authors":"K. Jagath-Kumara","doi":"10.1109/OLT.2000.856631","DOIUrl":"https://doi.org/10.1109/OLT.2000.856631","url":null,"abstract":"An online and direct estimator used for measuring the post-decoder error probability of communication links that employ both error control coding and modulation is discussed. The estimator is solely dependent on the information available in the received signal and therefore, it does not require transmission of test patterns. The performance bounds are found using both theoretical analysis and computer simulations. A number of block codes are considered for the analysis and it is shown that the estimation accuracy is best once the link is overlaid with the shortest possible block code.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132640422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off-the shelf VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis.
{"title":"Improving fault coverage in system tests","authors":"J. Sosnowski","doi":"10.1109/OLT.2000.856638","DOIUrl":"https://doi.org/10.1109/OLT.2000.856638","url":null,"abstract":"The paper is devoted to the problem of self-testing in system environment (field diagnosis and maintenance at the end user). It discusses test process decomposition in the context of increasing hardware complexity and proliferation of embedded DFT and BIST circuitry in the commercial off-the shelf VLSI chips (COTS). Test observability is improved with the use of various on-line monitoring mechanisms. To optimize test effectiveness we use special tools based on direct and indirect fault coverage analysis.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"9 Suppl 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134578903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dedicated to a wide range of power supplies current monitoring, a new version of a CMOS built-in current sensor is proposed. It takes advantage of the classical parasitic resistor attached to an interconnection layer, as well as to a feedback circuit with high static gain capability. Analysis and simulation reveal that the transducer is accurate, linear and transparent. Process dependencies are taken into account. The sensor was designed in a 0.6 /spl mu/m technology and its simulated characteristics are reported in this paper.
{"title":"An improved CMOS BICS for on-line testing","authors":"Y. Maidon, Y. Deval, J. Bégueret","doi":"10.1109/OLT.2000.856620","DOIUrl":"https://doi.org/10.1109/OLT.2000.856620","url":null,"abstract":"Dedicated to a wide range of power supplies current monitoring, a new version of a CMOS built-in current sensor is proposed. It takes advantage of the classical parasitic resistor attached to an interconnection layer, as well as to a feedback circuit with high static gain capability. Analysis and simulation reveal that the transducer is accurate, linear and transparent. Process dependencies are taken into account. The sensor was designed in a 0.6 /spl mu/m technology and its simulated characteristics are reported in this paper.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"22 24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123423593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of VLSI technology, large numbers of processing elements which cooperate with each other to achieve a complex function have become feasible. A major concern in the design of these complex devices has been the ability to verify and in some instances guarantee their fault free operation. Since any error in processed data may have catastrophic effects, therefore some levels of fault detection must be incorporated in order to increase the reliability of systems. This paper presents a general method for concurrent error detection in linear digital systems using analytical redundancy, i.e., relations between the measured variables. The fault detection mission can be performed using only the available connectable (measurable) variables, e.g. the external inputs and outputs, while the hardware overhead of the test circuit can be optimized through connecting on some internal mensurable state variables. Generally, this method is applicable to all linear digital systems while the test circuit obtained for on-line detector implementation is still very reasonable.
{"title":"Analytical redundancy based approach for concurrent fault detection in linear digital systems","authors":"A. Abdelhay, E. Simeu","doi":"10.1109/OLT.2000.856622","DOIUrl":"https://doi.org/10.1109/OLT.2000.856622","url":null,"abstract":"With the advent of VLSI technology, large numbers of processing elements which cooperate with each other to achieve a complex function have become feasible. A major concern in the design of these complex devices has been the ability to verify and in some instances guarantee their fault free operation. Since any error in processed data may have catastrophic effects, therefore some levels of fault detection must be incorporated in order to increase the reliability of systems. This paper presents a general method for concurrent error detection in linear digital systems using analytical redundancy, i.e., relations between the measured variables. The fault detection mission can be performed using only the available connectable (measurable) variables, e.g. the external inputs and outputs, while the hardware overhead of the test circuit can be optimized through connecting on some internal mensurable state variables. Generally, this method is applicable to all linear digital systems while the test circuit obtained for on-line detector implementation is still very reasonable.","PeriodicalId":334770,"journal":{"name":"Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130425865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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